Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.82	100.00	71.27			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	92.82	100.00	71.27			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.82	100.00	71.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.28	94.71	86.10			96.32	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.06	94.85	88.00	77.46		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_en_0	100.00	100.00	100.00			100.00
u_alert_en_1	100.00	100.00	100.00			100.00
u_alert_en_10	100.00	100.00	100.00			100.00
u_alert_en_2	100.00	100.00	100.00			100.00
u_alert_en_3	100.00	100.00	100.00			100.00
u_alert_en_4	100.00	100.00	100.00			100.00
u_alert_en_5	100.00	100.00	100.00			100.00
u_alert_en_6	100.00	100.00	100.00			100.00
u_alert_en_7	100.00	100.00	100.00			100.00
u_alert_en_8	100.00	100.00	100.00			100.00
u_alert_en_9	100.00	100.00	100.00			100.00
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_10	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_7	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_8	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_9	100.00	100.00	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	47.78	33.33	50.00			60.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	96.30	88.89	100.00			100.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_manual_pad_attr_0	80.00	80.00
u_manual_pad_attr_1	80.00	80.00
u_manual_pad_attr_2	80.00	80.00
u_manual_pad_attr_3	80.00	80.00
u_manual_pad_attr_regwen_0	100.00	100.00	100.00			100.00
u_manual_pad_attr_regwen_1	100.00	100.00	100.00			100.00
u_manual_pad_attr_regwen_2	89.63	88.89	80.00			100.00
u_manual_pad_attr_regwen_3	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	89.30	94.29	76.54			86.36	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		272	272	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	441	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	807	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	935	1	1	100.00
CONT_ASSIGN	967	1	1	100.00
CONT_ASSIGN	999	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1095	1	1	100.00
CONT_ASSIGN	1127	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	2261	1	1	100.00
CONT_ASSIGN	2264	1	1	100.00
CONT_ASSIGN	2278	1	1	100.00
CONT_ASSIGN	2285	1	1	100.00
CONT_ASSIGN	2288	1	1	100.00
CONT_ASSIGN	2302	1	1	100.00
CONT_ASSIGN	2309	1	1	100.00
CONT_ASSIGN	2312	1	1	100.00
CONT_ASSIGN	2326	1	1	100.00
CONT_ASSIGN	2333	1	1	100.00
CONT_ASSIGN	2336	1	1	100.00
CONT_ASSIGN	2350	1	1	100.00
ALWAYS	2356	30	30	100.00
CONT_ASSIGN	2388	1	1	100.00
ALWAYS	2392	1	1	100.00
CONT_ASSIGN	2425	1	1	100.00
CONT_ASSIGN	2427	1	1	100.00
CONT_ASSIGN	2429	1	1	100.00
CONT_ASSIGN	2430	1	1	100.00
CONT_ASSIGN	2432	1	1	100.00
CONT_ASSIGN	2434	1	1	100.00
CONT_ASSIGN	2435	1	1	100.00
CONT_ASSIGN	2437	1	1	100.00
CONT_ASSIGN	2439	1	1	100.00
CONT_ASSIGN	2440	1	1	100.00
CONT_ASSIGN	2442	1	1	100.00
CONT_ASSIGN	2444	1	1	100.00
CONT_ASSIGN	2445	1	1	100.00
CONT_ASSIGN	2447	1	1	100.00
CONT_ASSIGN	2448	1	1	100.00
CONT_ASSIGN	2450	1	1	100.00
CONT_ASSIGN	2452	1	1	100.00
CONT_ASSIGN	2454	1	1	100.00
CONT_ASSIGN	2456	1	1	100.00
CONT_ASSIGN	2458	1	1	100.00
CONT_ASSIGN	2460	1	1	100.00
CONT_ASSIGN	2462	1	1	100.00
CONT_ASSIGN	2464	1	1	100.00
CONT_ASSIGN	2466	1	1	100.00
CONT_ASSIGN	2468	1	1	100.00
CONT_ASSIGN	2470	1	1	100.00
CONT_ASSIGN	2471	1	1	100.00
CONT_ASSIGN	2473	1	1	100.00
CONT_ASSIGN	2474	1	1	100.00
CONT_ASSIGN	2476	1	1	100.00
CONT_ASSIGN	2477	1	1	100.00
CONT_ASSIGN	2479	1	1	100.00
CONT_ASSIGN	2480	1	1	100.00
CONT_ASSIGN	2482	1	1	100.00
CONT_ASSIGN	2483	1	1	100.00
CONT_ASSIGN	2485	1	1	100.00
CONT_ASSIGN	2486	1	1	100.00
CONT_ASSIGN	2488	1	1	100.00
CONT_ASSIGN	2489	1	1	100.00
CONT_ASSIGN	2491	1	1	100.00
CONT_ASSIGN	2492	1	1	100.00
CONT_ASSIGN	2494	1	1	100.00
CONT_ASSIGN	2495	1	1	100.00
CONT_ASSIGN	2497	1	1	100.00
CONT_ASSIGN	2498	1	1	100.00
CONT_ASSIGN	2500	1	1	100.00
CONT_ASSIGN	2501	1	1	100.00
CONT_ASSIGN	2503	1	1	100.00
CONT_ASSIGN	2504	1	1	100.00
CONT_ASSIGN	2506	1	1	100.00
CONT_ASSIGN	2508	1	1	100.00
CONT_ASSIGN	2510	1	1	100.00
CONT_ASSIGN	2512	1	1	100.00
CONT_ASSIGN	2514	1	1	100.00
CONT_ASSIGN	2516	1	1	100.00
CONT_ASSIGN	2518	1	1	100.00
CONT_ASSIGN	2520	1	1	100.00
CONT_ASSIGN	2522	1	1	100.00
CONT_ASSIGN	2524	1	1	100.00
CONT_ASSIGN	2526	1	1	100.00
CONT_ASSIGN	2527	1	1	100.00
CONT_ASSIGN	2529	1	1	100.00
CONT_ASSIGN	2531	1	1	100.00
CONT_ASSIGN	2533	1	1	100.00
CONT_ASSIGN	2535	1	1	100.00
CONT_ASSIGN	2537	1	1	100.00
CONT_ASSIGN	2539	1	1	100.00
CONT_ASSIGN	2541	1	1	100.00
CONT_ASSIGN	2543	1	1	100.00
CONT_ASSIGN	2545	1	1	100.00
CONT_ASSIGN	2547	1	1	100.00
CONT_ASSIGN	2549	1	1	100.00
CONT_ASSIGN	2550	1	1	100.00
CONT_ASSIGN	2552	1	1	100.00
CONT_ASSIGN	2553	1	1	100.00
CONT_ASSIGN	2555	1	1	100.00
CONT_ASSIGN	2556	1	1	100.00
CONT_ASSIGN	2558	1	1	100.00
CONT_ASSIGN	2559	1	1	100.00
CONT_ASSIGN	2561	1	1	100.00
CONT_ASSIGN	2562	1	1	100.00
CONT_ASSIGN	2563	1	1	100.00
CONT_ASSIGN	2565	1	1	100.00
CONT_ASSIGN	2566	1	1	100.00
CONT_ASSIGN	2567	1	1	100.00
CONT_ASSIGN	2569	1	1	100.00
CONT_ASSIGN	2570	1	1	100.00
CONT_ASSIGN	2571	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2574	1	1	100.00
CONT_ASSIGN	2575	1	1	100.00
CONT_ASSIGN	2577	1	1	100.00
ALWAYS	2581	30	30	100.00
ALWAYS	2615	77	77	100.00
CONT_ASSIGN	2790	0	0
CONT_ASSIGN	2798	1	1	100.00
CONT_ASSIGN	2799	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
404	1	1
419	1	1
435	1	1
441	1	1
456	1	1
472	1	1
807	1	1
839	1	1
871	1	1
903	1	1
935	1	1
967	1	1
999	1	1
1031	1	1
1063	1	1
1095	1	1
1127	1	1
1159	1	1
2261	1	1
2264	1	1
2278	1	1
2285	1	1
2288	1	1
2302	1	1
2309	1	1
2312	1	1
2326	1	1
2333	1	1
2336	1	1
2350	1	1
2356	1	1
2357	1	1
2358	1	1
2359	1	1
2360	1	1
2361	1	1
2362	1	1
2363	1	1
2364	1	1
2365	1	1
2366	1	1
2367	1	1
2368	1	1
2369	1	1
2370	1	1
2371	1	1
2372	1	1
2373	1	1
2374	1	1
2375	1	1
2376	1	1
2377	1	1
2378	1	1
2379	1	1
2380	1	1
2381	1	1
2382	1	1
2383	1	1
2384	1	1
2385	1	1
2388	1	1
2392	1	1
2425	1	1
2427	1	1
2429	1	1
2430	1	1
2432	1	1
2434	1	1
2435	1	1
2437	1	1
2439	1	1
2440	1	1
2442	1	1
2444	1	1
2445	1	1
2447	1	1
2448	1	1
2450	1	1
2452	1	1
2454	1	1
2456	1	1
2458	1	1
2460	1	1
2462	1	1
2464	1	1
2466	1	1
2468	1	1
2470	1	1
2471	1	1
2473	1	1
2474	1	1
2476	1	1
2477	1	1
2479	1	1
2480	1	1
2482	1	1
2483	1	1
2485	1	1
2486	1	1
2488	1	1
2489	1	1
2491	1	1
2492	1	1
2494	1	1
2495	1	1
2497	1	1
2498	1	1
2500	1	1
2501	1	1
2503	1	1
2504	1	1
2506	1	1
2508	1	1
2510	1	1
2512	1	1
2514	1	1
2516	1	1
2518	1	1
2520	1	1
2522	1	1
2524	1	1
2526	1	1
2527	1	1
2529	1	1
2531	1	1
2533	1	1
2535	1	1
2537	1	1
2539	1	1
2541	1	1
2543	1	1
2545	1	1
2547	1	1
2549	1	1
2550	1	1
2552	1	1
2553	1	1
2555	1	1
2556	1	1
2558	1	1
2559	1	1
2561	1	1
2562	1	1
2563	1	1
2565	1	1
2566	1	1
2567	1	1
2569	1	1
2570	1	1
2571	1	1
2573	1	1
2574	1	1
2575	1	1
2577	1	1
2581	1	1
2582	1	1
2583	1	1
2584	1	1
2585	1	1
2586	1	1
2587	1	1
2588	1	1
2589	1	1
2590	1	1
2591	1	1
2592	1	1
2593	1	1
2594	1	1
2595	1	1
2596	1	1
2597	1	1
2598	1	1
2599	1	1
2600	1	1
2601	1	1
2602	1	1
2603	1	1
2604	1	1
2605	1	1
2606	1	1
2607	1	1
2608	1	1
2609	1	1
2610	1	1
2615	1	1
2616	1	1
2618	1	1
2619	1	1
2623	1	1
2624	1	1
2628	1	1
2629	1	1
2633	1	1
2634	1	1
2638	1	1
2642	1	1
2643	1	1
2644	1	1
2645	1	1
2646	1	1
2647	1	1
2648	1	1
2649	1	1
2650	1	1
2651	1	1
2652	1	1
2656	1	1
2660	1	1
2664	1	1
2668	1	1
2672	1	1
2676	1	1
2680	1	1
2684	1	1
2688	1	1
2692	1	1
2696	1	1
2700	1	1
2701	1	1
2702	1	1
2703	1	1
2704	1	1
2705	1	1
2706	1	1
2707	1	1
2708	1	1
2709	1	1
2710	1	1
2714	1	1
2715	1	1
2716	1	1
2717	1	1
2718	1	1
2719	1	1
2720	1	1
2721	1	1
2722	1	1
2723	1	1
2724	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2743	1	1
2744	1	1
2748	1	1
2752	1	1
2756	1	1
2760	1	1
2764	1	1
2768	1	1
2772	1	1
2776	1	1
2790		unreachable
2798	1	1
2799	1	1

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	369	263	71.27
Logical	369	263	71.27
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T156,T19

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T338,T339,T340
1	0	Not Covered

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T338,T339,T340
0	1	0	Not Covered
1	0	0	Covered	T338,T339,T340

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       807
 EXPRESSION (alert_en_0_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       839
 EXPRESSION (alert_en_1_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T156,T19

 LINE       871
 EXPRESSION (alert_en_2_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       903
 EXPRESSION (alert_en_3_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       935
 EXPRESSION (alert_en_4_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T156,T19

 LINE       967
 EXPRESSION (alert_en_5_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       999
 EXPRESSION (alert_en_6_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       1031
 EXPRESSION (alert_en_7_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T67
1	1	Covered	T17,T19,T47

 LINE       1063
 EXPRESSION (alert_en_8_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       1095
 EXPRESSION (alert_en_9_we & cfg_regwen_qs)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       1127
 EXPRESSION (alert_en_10_we & cfg_regwen_qs)
             -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T19,T47

 LINE       1159
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T156,T67,T161

 LINE       2264
 EXPRESSION (manual_pad_attr_0_we & manual_pad_attr_regwen_0_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T31,T32

 LINE       2288
 EXPRESSION (manual_pad_attr_1_we & manual_pad_attr_regwen_1_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T31,T32

 LINE       2312
 EXPRESSION (manual_pad_attr_2_we & manual_pad_attr_regwen_2_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T31,T32

 LINE       2336
 EXPRESSION (manual_pad_attr_3_we & manual_pad_attr_regwen_3_qs)
             ----------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T31,T32

 LINE       2357
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2358
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2359
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2360
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2361
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2362
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2363
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2364
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2365
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2366
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2367
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2368
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2369
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2370
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2371
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2372
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2373
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_EN_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2374
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2375
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2376
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2377
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2378
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_0_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2379
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_1_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2380
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_2_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2381
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_REGWEN_3_OFFSET)
            ---------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2382
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2383
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2384
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2385
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_MANUAL_PAD_ATTR_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2388
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2388
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T156,T19
1	0	Covered	T1,T2,T3

 LINE       2392
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T156,T19
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0011 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
29 (addr_hit[28] & ((|(4'...	Not Covered
28 (addr_hit[27] & ((|(4'...	Not Covered
27 (addr_hit[26] & ((|(4'...	Not Covered
26 (addr_hit[25] & ((|(4'...	Not Covered
25 (addr_hit[24] & ((|(4'...	Not Covered
24 (addr_hit[23] & ((|(4'...	Not Covered
23 (addr_hit[22] & ((|(4'...	Not Covered
22 (addr_hit[21] & ((|(4'...	Not Covered
21 (addr_hit[20] & ((|(4'...	Not Covered
20 (addr_hit[19] & ((|(4'...	Covered	T30,T31,T32
19 (addr_hit[18] & ((|(4'...	Covered	T30,T31,T32
18 (addr_hit[17] & ((|(4'...	Covered	T30,T31,T32
17 (addr_hit[16] & ((|(4'...	Not Covered
16 (addr_hit[15] & ((|(4'...	Not Covered
15 (addr_hit[14] & ((|(4'...	Not Covered
14 (addr_hit[13] & ((|(4'...	Not Covered
13 (addr_hit[12] & ((|(4'...	Not Covered
12 (addr_hit[11] & ((|(4'...	Not Covered
11 (addr_hit[10] & ((|(4'...	Not Covered
10 (addr_hit[9] & ((|(4'b...	Not Covered
9 (addr_hit[8] & ((|(4'b...	Not Covered
8 (addr_hit[7] & ((|(4'b...	Not Covered
7 (addr_hit[6] & ((|(4'b...	Not Covered
6 (addr_hit[5] & ((|(4'b...	Covered	T30,T31,T32
5 (addr_hit[4] & ((|(4'b...	Not Covered
4 (addr_hit[3] & ((|(4'b...	Not Covered
3 (addr_hit[2] & ((|(4'b...	Not Covered
2 (addr_hit[1] & ((|(4'b...	Not Covered
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       2392
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2392
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       2392
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       2392
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       2392
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T30,T31,T32

 LINE       2392
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2392
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       2425
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T173,T106,T324

 LINE       2430
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T173,T67,T106

 LINE       2435
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T106,T107,T108

 LINE       2440
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T73,T67,T124

 LINE       2445
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T67

 LINE       2448
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T156,T19

 LINE       2471
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2474
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T156,T19

 LINE       2477
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2480
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2483
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T156,T19

 LINE       2486
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2489
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2492
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2495
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2498
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2501
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T19,T47

 LINE       2504
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T156,T67,T161

 LINE       2527
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T17,T156,T19

 LINE       2550
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T67

 LINE       2553
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T67

 LINE       2556
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T67

 LINE       2559
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T67

 LINE       2562
 EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2563
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T30,T31,T32

 LINE       2566
 EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2567
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T30,T31,T32

 LINE       2570
 EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2571
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T30,T31,T32

 LINE       2574
 EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       2575
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T156,T19
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T30,T31,T32

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	2388	2	2	100.00
IF	68	3	3	100.00
CASE	2616	30	30	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2388	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T338,T339,T340
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2616	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	77821703	3376	0	0
reAfterRv	77821703	3376	0	0
rePulse	77821703	2485	0	0
wePulse	77821703	891	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	77821703	3376	0	0
T1	360326	1	0	0
T2	138206	2	0	0
T3	122909	1	0	0
T4	66885	3	0	0
T33	30442	2	0	0
T59	31285	1	0	0
T60	57882	1	0	0
T98	55314	1	0	0
T102	414496	1	0	0
T132	267231	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	77821703	3376	0	0
T1	360326	1	0	0
T2	138206	2	0	0
T3	122909	1	0	0
T4	66885	3	0	0
T33	30442	2	0	0
T59	31285	1	0	0
T60	57882	1	0	0
T98	55314	1	0	0
T102	414496	1	0	0
T132	267231	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	77821703	2485	0	0
T1	360326	1	0	0
T2	138206	2	0	0
T3	122909	1	0	0
T4	66885	3	0	0
T33	30442	2	0	0
T59	31285	1	0	0
T60	57882	1	0	0
T98	55314	1	0	0
T102	414496	1	0	0
T132	267231	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	77821703	891	0	0
T17	36326	14	0	0
T18	707146	0	0	0
T19	0	80	0	0
T47	0	14	0	0
T67	0	22	0	0
T73	0	2	0	0
T95	392098	0	0	0
T113	46021	0	0	0
T142	0	80	0	0
T145	94464	0	0	0
T146	120052	0	0	0
T147	35829	0	0	0
T148	39785	0	0	0
T149	79915	0	0	0
T150	33252	0	0	0
T156	0	26	0	0
T157	0	55	0	0
T173	0	12	0	0
T250	0	28	0	0