Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.54	96.47	89.29	98.77		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.79	96.47	89.29	100.00		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.79	96.47	89.29	100.00		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	97.67	95.97	98.57		98.66	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	92.37	97.67	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.26			96.26
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.24	98.69	98.69			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T113,T232,T114
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T233,T234,T235
1	0	Covered	T45,T46,T236

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T46,T236

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T124,T51

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T73,T50,T124
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T109

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T50,T124

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T50,T124

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T46,T236
0	1	0	Covered	T113,T232,T114
1	0	0	Covered	T237,T238,T239

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T102
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T63,T240,T241	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T62,T64,T242	Yes	T62,T242,T240	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T89,T90,T185	Yes	T89,T90,T185	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T217,T218,T210	Yes	T217,T218,T210	INPUT
irq_timer_i	Yes	Yes	T243,T106,T244	Yes	T243,T106,T244	INPUT
irq_external_i	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
esc_tx_i.esc_n	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
esc_tx_i.esc_p	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
esc_rx_o.resp_n	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
nmi_wdog_i	Yes	Yes	T90,T185,T245	Yes	T90,T185,T245	INPUT
debug_req_i	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T59,T33	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T3,T102,T33	Yes	T3,T102,T98	INPUT
edn_i.edn_fips	Yes	Yes	T102,T155,T149	Yes	T102,T155,T101	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T116,T117,T103	Yes	T116,T117,T103	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T33,T45	Yes	T1,T102,T33	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T59	INPUT
icache_otp_key_i.ack	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T45,T46,T83	Yes	T45,T46,T83	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T83,T113,T237	Yes	T83,T113,T237	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T45,T46,T83	Yes	T45,T46,T83	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T83,T113,T237	Yes	T83,T113,T237	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T236
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T233,T234,T235
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T102,T59
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	312252910	7	0	0
FpvSecCmIbexFetchEnable1_A	312252910	18568940	0	32
FpvSecCmIbexFetchEnable2_A	312252910	52384921	0	42
FpvSecCmIbexFetchEnable3Rev_A	312252910	255664699	0	1690
FpvSecCmIbexFetchEnable3_A	312252910	255666266	0	1647
FpvSecCmIbexInstrIntgErrCheck_A	312252910	228	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	312252910	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	312252910	0	0	0
FpvSecCmIbexPcMismatchCheck_A	312252910	0	0	0
FpvSecCmIbexRfEccErrCheck_A	312252910	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	312252910	0	0	0
FpvSecCmRegWeOnehotCheck_A	312252910	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	312252910	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	312252910	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	312252910	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	846	846	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	846	846	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	312252910	159	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	312252910	200	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	7	0	0
T66	112941	0	0	0
T233	257227	1	0	0
T234	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	140207	0	0	0
T251	184823	0	0	0
T252	141864	0	0	0
T253	136356	0	0	0
T254	232157	0	0	0
T255	153985	0	0	0
T256	143336	0	0	0
T257	146985	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	18568940	0	32
T1	149968	9931	0	0
T2	572665	19854	0	0
T3	510515	9931	0	0
T4	273933	29769	0	0
T5	0	0	0	2
T30	0	0	0	2
T31	0	0	0	2
T32	0	0	0	2
T33	123646	20377	0	0
T50	0	0	0	2
T51	0	0	0	2
T59	128774	9931	0	0
T60	239585	9927	0	0
T66	0	0	0	2
T67	0	0	0	2
T98	228885	9923	0	0
T102	108799	9919	0	0
T132	111181	9919	0	0
T201	0	0	0	2
T258	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	52384921	0	42
T1	149968	34775	0	0
T2	572665	69555	0	0
T3	510515	34775	0	0
T4	273933	105851	0	0
T5	0	0	0	2
T8	0	0	0	2
T9	0	0	0	2
T33	123646	69554	0	0
T50	0	0	0	2
T51	0	0	0	2
T59	128774	38304	0	0
T60	239585	34775	0	0
T66	0	0	0	2
T67	0	0	0	2
T98	228885	34775	0	0
T102	108799	34775	0	0
T132	111181	34775	0	0
T259	0	0	0	2
T260	0	0	0	2
T261	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	255664699	0	1690
T1	149968	146485	0	2
T2	572665	502991	0	2
T3	510515	475679	0	2
T4	273933	167905	0	2
T33	123646	53172	0	2
T59	128774	90404	0	2
T60	239585	204749	0	2
T98	228885	194056	0	2
T102	108799	105315	0	2
T132	111181	107698	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	255666266	0	1647
T1	149968	146485	0	2
T2	572665	502993	0	2
T3	510515	475680	0	2
T4	273933	167908	0	2
T33	123646	53174	0	2
T59	128774	90406	0	2
T60	239585	204750	0	2
T98	228885	194057	0	2
T102	108799	105315	0	2
T132	111181	107698	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	228	0	0
T36	194353	0	0	0
T206	193162	0	0	0
T208	284356	0	0	0
T223	437502	0	0	0
T232	305182	76	0	0
T262	0	76	0	0
T263	0	76	0	0
T264	151301	0	0	0
T265	96297	0	0	0
T266	256339	0	0	0
T267	599699	0	0	0
T268	561276	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	586	0	0
T18	294467	0	0	0
T95	163206	0	0	0
T113	176189	32	0	0
T114	0	31	0	0
T145	391999	0	0	0
T146	338091	0	0	0
T147	147704	0	0	0
T148	164194	0	0	0
T149	331381	0	0	0
T150	136964	0	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	0	31	0	0
T272	0	100	0	0
T273	0	32	0	0
T274	0	32	0	0
T275	0	99	0	0
T276	0	32	0	0
T277	150814	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	3	0	0
T21	104395	0	0	0
T65	236135	0	0	0
T181	210908	0	0	0
T182	108546	0	0	0
T237	291842	1	0	0
T238	0	1	0	0
T239	0	1	0	0
T278	180065	0	0	0
T279	365406	0	0	0
T280	249811	0	0	0
T281	147721	0	0	0
T282	164845	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	159	0	0
T5	113076	0	0	0
T16	71097	0	0	0
T112	234342	0	0	0
T116	80539	26	0	0
T117	0	16	0	0
T118	0	36	0	0
T155	382556	0	0	0
T184	272452	0	0	0
T185	676908	0	0	0
T186	263598	0	0	0
T187	99119	0	0	0
T283	0	17	0	0
T284	0	16	0	0
T285	0	48	0	0
T286	42221	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	200	0	0
T5	113076	0	0	0
T16	71097	0	0	0
T103	0	16	0	0
T112	234342	0	0	0
T116	80539	6	0	0
T117	0	42	0	0
T118	0	9	0	0
T155	382556	0	0	0
T184	272452	0	0	0
T185	676908	0	0	0
T186	263598	0	0	0
T187	99119	0	0	0
T283	0	42	0	0
T284	0	42	0	0
T285	0	11	0	0
T286	42221	0	0	0
T287	0	16	0	0
T288	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T113,T232,T114
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T233,T234,T235
1	0	Covered	T45,T46,T236

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T46,T236

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T124,T51

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T73,T50,T124
1	0	Covered	T1,T2,T3
1	1	Covered	T45,T46,T109

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T50,T124

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T109
1	0	Covered	T1,T2,T3
1	1	Covered	T73,T50,T124

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T45,T46,T236
0	1	0	Covered	T113,T232,T114
1	0	0	Covered	T237,T238,T239

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T102
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T63,T240,T241	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T62,T64,T242	Yes	T62,T242,T240	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T89,T185,T186	Yes	T89,T185,T186	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T5,T66,T67	Yes	T5,T66,T67	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T66,T51,T62	Yes	T66,T51,T62	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T89,T90,T185	Yes	T89,T90,T185	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T217,T218,T210	Yes	T217,T218,T210	INPUT
irq_timer_i	Yes	Yes	T243,T106,T244	Yes	T243,T106,T244	INPUT
irq_external_i	Yes	Yes	T1,T3,T59	Yes	T1,T3,T59	INPUT
esc_tx_i.esc_n	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
esc_tx_i.esc_p	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	INPUT
esc_rx_o.resp_n	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T59,T45,T89	Yes	T59,T45,T89	OUTPUT
nmi_wdog_i	Yes	Yes	T90,T185,T245	Yes	T90,T185,T245	INPUT
debug_req_i	Yes	Yes	T65,T75,T76	Yes	T65,T75,T76	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T59,T33	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T62,*T63,*T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T50,T51,T62	Yes	T50,T51,T62	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T3,T102,T59	Yes	T3,T102,T59	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T50,*T51,*T62	Yes	T50,T51,T62	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T62,T63,T64	Yes	T62,T63,T64	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T3,T102,T33	Yes	T3,T102,T98	INPUT
edn_i.edn_fips	Yes	Yes	T102,T155,T149	Yes	T102,T155,T101	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T116,T117,T103	Yes	T116,T117,T103	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T2,T33,T4	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T33,T45	Yes	T1,T102,T33	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T59	INPUT
icache_otp_key_i.ack	Yes	Yes	T116,T117,T118	Yes	T116,T117,T118	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T45,T46,T83	Yes	T45,T46,T83	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T83,T113,T237	Yes	T83,T113,T237	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T45,T46,T83	Yes	T45,T46,T83	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T83,T113,T237	Yes	T83,T113,T237	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T83,T73,T84	Yes	T83,T73,T84	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T236
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T233,T234,T235
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T102,T59
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	312252910	7	0	0
FpvSecCmIbexFetchEnable1_A	312252910	18568940	0	32
FpvSecCmIbexFetchEnable2_A	312252910	52384921	0	42
FpvSecCmIbexFetchEnable3Rev_A	312252910	255664699	0	1690
FpvSecCmIbexFetchEnable3_A	312252910	255666266	0	1647
FpvSecCmIbexInstrIntgErrCheck_A	312252910	228	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	312252910	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	312252910	0	0	0
FpvSecCmIbexPcMismatchCheck_A	312252910	0	0	0
FpvSecCmIbexRfEccErrCheck_A	312252910	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	312252910	0	0	0
FpvSecCmRegWeOnehotCheck_A	312252910	3	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	312252910	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	312252910	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	312252910	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	846	846	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	846	846	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	846	846	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	312252910	159	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	312252910	200	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	7	0	0
T66	112941	0	0	0
T233	257227	1	0	0
T234	0	1	0	0
T235	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	140207	0	0	0
T251	184823	0	0	0
T252	141864	0	0	0
T253	136356	0	0	0
T254	232157	0	0	0
T255	153985	0	0	0
T256	143336	0	0	0
T257	146985	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	18568940	0	32
T1	149968	9931	0	0
T2	572665	19854	0	0
T3	510515	9931	0	0
T4	273933	29769	0	0
T5	0	0	0	2
T30	0	0	0	2
T31	0	0	0	2
T32	0	0	0	2
T33	123646	20377	0	0
T50	0	0	0	2
T51	0	0	0	2
T59	128774	9931	0	0
T60	239585	9927	0	0
T66	0	0	0	2
T67	0	0	0	2
T98	228885	9923	0	0
T102	108799	9919	0	0
T132	111181	9919	0	0
T201	0	0	0	2
T258	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	52384921	0	42
T1	149968	34775	0	0
T2	572665	69555	0	0
T3	510515	34775	0	0
T4	273933	105851	0	0
T5	0	0	0	2
T8	0	0	0	2
T9	0	0	0	2
T33	123646	69554	0	0
T50	0	0	0	2
T51	0	0	0	2
T59	128774	38304	0	0
T60	239585	34775	0	0
T66	0	0	0	2
T67	0	0	0	2
T98	228885	34775	0	0
T102	108799	34775	0	0
T132	111181	34775	0	0
T259	0	0	0	2
T260	0	0	0	2
T261	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	255664699	0	1690
T1	149968	146485	0	2
T2	572665	502991	0	2
T3	510515	475679	0	2
T4	273933	167905	0	2
T33	123646	53172	0	2
T59	128774	90404	0	2
T60	239585	204749	0	2
T98	228885	194056	0	2
T102	108799	105315	0	2
T132	111181	107698	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	255666266	0	1647
T1	149968	146485	0	2
T2	572665	502993	0	2
T3	510515	475680	0	2
T4	273933	167908	0	2
T33	123646	53174	0	2
T59	128774	90406	0	2
T60	239585	204750	0	2
T98	228885	194057	0	2
T102	108799	105315	0	2
T132	111181	107698	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	228	0	0
T36	194353	0	0	0
T206	193162	0	0	0
T208	284356	0	0	0
T223	437502	0	0	0
T232	305182	76	0	0
T262	0	76	0	0
T263	0	76	0	0
T264	151301	0	0	0
T265	96297	0	0	0
T266	256339	0	0	0
T267	599699	0	0	0
T268	561276	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	586	0	0
T18	294467	0	0	0
T95	163206	0	0	0
T113	176189	32	0	0
T114	0	31	0	0
T145	391999	0	0	0
T146	338091	0	0	0
T147	147704	0	0	0
T148	164194	0	0	0
T149	331381	0	0	0
T150	136964	0	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	0	31	0	0
T272	0	100	0	0
T273	0	32	0	0
T274	0	32	0	0
T275	0	99	0	0
T276	0	32	0	0
T277	150814	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	3	0	0
T21	104395	0	0	0
T65	236135	0	0	0
T181	210908	0	0	0
T182	108546	0	0	0
T237	291842	1	0	0
T238	0	1	0	0
T239	0	1	0	0
T278	180065	0	0	0
T279	365406	0	0	0
T280	249811	0	0	0
T281	147721	0	0	0
T282	164845	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	846	846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T33	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T98	1	1	0	0
T102	1	1	0	0
T132	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	159	0	0
T5	113076	0	0	0
T16	71097	0	0	0
T112	234342	0	0	0
T116	80539	26	0	0
T117	0	16	0	0
T118	0	36	0	0
T155	382556	0	0	0
T184	272452	0	0	0
T185	676908	0	0	0
T186	263598	0	0	0
T187	99119	0	0	0
T283	0	17	0	0
T284	0	16	0	0
T285	0	48	0	0
T286	42221	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	312252910	200	0	0
T5	113076	0	0	0
T16	71097	0	0	0
T103	0	16	0	0
T112	234342	0	0	0
T116	80539	6	0	0
T117	0	42	0	0
T118	0	9	0	0
T155	382556	0	0	0
T184	272452	0	0	0
T185	676908	0	0	0
T186	263598	0	0	0
T187	99119	0	0	0
T283	0	42	0	0
T284	0	42	0	0
T285	0	11	0	0
T286	42221	0	0	0
T287	0	16	0	0
T288	0	16	0	0