Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.79 96.47 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 624505820 2966 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 624505820 2966 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 624505820 2966 0 0
T1 149968 1 0 0
T2 572665 2 0 0
T3 510515 2 0 0
T4 273933 3 0 0
T5 113076 0 0 0
T16 71097 0 0 0
T33 123646 2 0 0
T59 128774 2 0 0
T60 239585 1 0 0
T98 228885 1 0 0
T102 108799 20 0 0
T112 234342 0 0 0
T116 80539 6 0 0
T117 0 4 0 0
T118 0 9 0 0
T132 111181 1 0 0
T155 382556 0 0 0
T184 272452 0 0 0
T185 676908 0 0 0
T186 263598 0 0 0
T187 99119 0 0 0
T283 0 4 0 0
T284 0 4 0 0
T285 0 11 0 0
T286 42221 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 624505820 2966 0 0
T1 149968 1 0 0
T2 572665 2 0 0
T3 510515 2 0 0
T4 273933 3 0 0
T5 113076 0 0 0
T16 71097 0 0 0
T33 123646 2 0 0
T59 128774 2 0 0
T60 239585 1 0 0
T98 228885 1 0 0
T102 108799 20 0 0
T112 234342 0 0 0
T116 80539 6 0 0
T117 0 4 0 0
T118 0 9 0 0
T132 111181 1 0 0
T155 382556 0 0 0
T184 272452 0 0 0
T185 676908 0 0 0
T186 263598 0 0 0
T187 99119 0 0 0
T283 0 4 0 0
T284 0 4 0 0
T285 0 11 0 0
T286 42221 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 312252910 38 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 312252910 38 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 312252910 38 0 0
T5 113076 0 0 0
T16 71097 0 0 0
T112 234342 0 0 0
T116 80539 6 0 0
T117 0 4 0 0
T118 0 9 0 0
T155 382556 0 0 0
T184 272452 0 0 0
T185 676908 0 0 0
T186 263598 0 0 0
T187 99119 0 0 0
T283 0 4 0 0
T284 0 4 0 0
T285 0 11 0 0
T286 42221 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 312252910 38 0 0
T5 113076 0 0 0
T16 71097 0 0 0
T112 234342 0 0 0
T116 80539 6 0 0
T117 0 4 0 0
T118 0 9 0 0
T155 382556 0 0 0
T184 272452 0 0 0
T185 676908 0 0 0
T186 263598 0 0 0
T187 99119 0 0 0
T283 0 4 0 0
T284 0 4 0 0
T285 0 11 0 0
T286 42221 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 312252910 2928 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 312252910 2928 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 312252910 2928 0 0
T1 149968 1 0 0
T2 572665 2 0 0
T3 510515 2 0 0
T4 273933 3 0 0
T33 123646 2 0 0
T59 128774 2 0 0
T60 239585 1 0 0
T98 228885 1 0 0
T102 108799 20 0 0
T132 111181 1 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 312252910 2928 0 0
T1 149968 1 0 0
T2 572665 2 0 0
T3 510515 2 0 0
T4 273933 3 0 0
T33 123646 2 0 0
T59 128774 2 0 0
T60 239585 1 0 0
T98 228885 1 0 0
T102 108799 20 0 0
T132 111181 1 0 0

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