CHIP Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.365m	2.465ms	3	3	100.00
		chip_sw_example_rom	2.235m	1.662ms	3	3	100.00
		chip_sw_example_manufacturer	4.997m	2.710ms	3	3	100.00
		chip_sw_example_concurrency	4.854m	3.423ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.567m	7.302ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.639m	5.866ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	18.613m	11.412ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.741h	56.181ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.954m	1.921ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.741h	56.181ms	4	5	80.00
		chip_csr_rw	10.639m	5.866ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.820s	252.664us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.826m	3.884ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.826m	3.884ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.826m	3.884ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	9.994m	3.818ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	9.994m	3.818ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	10.917m	4.557ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	13.479m	4.387ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.026m	4.289ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	38.482m	13.056ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	46.610m	12.972ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.897m	13.426ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.464m	4.720ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.464m	4.720ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.517m	2.843ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.789m	4.978ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.734m	3.901ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	26.317m	18.136ms	5	5	100.00
		chip_tap_straps_testunlock0	13.256m	8.090ms	5	5	100.00
		chip_tap_straps_rma	10.949m	6.935ms	4	5	80.00
		chip_tap_straps_prod	21.689m	12.369ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.216m	2.870ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	27.447m	7.370ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.395m	5.966ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.395m	5.966ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.582m	7.463ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	46.057m	20.569ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.734m	4.519ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.187m	5.803ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.009h	19.233ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.265m	2.900ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.146m	6.877ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.353m	2.680ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	26.928m	8.962ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.170m	3.184ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.417m	4.373ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.893m	3.081ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.683m	3.678ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	13.381m	8.000ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.573m	5.301ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.095m	2.717ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.573m	5.301ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.198m	2.609ms	3	3	100.00
		chip_sw_aes_smoketest	5.168m	2.923ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.720m	3.418ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.188m	2.232ms	3	3	100.00
		chip_sw_csrng_smoketest	4.832m	3.298ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.339m	3.350ms	3	3	100.00
		chip_sw_gpio_smoketest	5.224m	2.931ms	3	3	100.00
		chip_sw_hmac_smoketest	7.359m	3.385ms	3	3	100.00
		chip_sw_kmac_smoketest	5.590m	3.137ms	3	3	100.00
		chip_sw_otbn_smoketest	34.579m	9.303ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.271m	2.580ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.273m	5.155ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.893m	4.450ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.645m	2.978ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.996m	3.369ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.571m	3.179ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.534m	3.170ms	3	3	100.00
		chip_sw_uart_smoketest	4.888m	2.744ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.841m	4.712ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.800h	76.607ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.243h	17.438ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.084m	3.921ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	12.386m	10.821ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	6.923m	5.179ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.323h	63.182ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.996m	4.378ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	6.996m	4.378ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.741h	56.181ms	4	5	80.00
		chip_same_csr_outstanding	1.190h	29.460ms	19	20	95.00
		chip_csr_hw_reset	6.567m	7.302ms	5	5	100.00
		chip_csr_rw	10.639m	5.866ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.741h	56.181ms	4	5	80.00
		chip_same_csr_outstanding	1.190h	29.460ms	19	20	95.00
		chip_csr_hw_reset	6.567m	7.302ms	5	5	100.00
		chip_csr_rw	10.639m	5.866ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.751m	2.651ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.530s	57.764us	100	100	100.00
		xbar_smoke_large_delays	2.026m	10.794ms	100	100	100.00
		xbar_smoke_slow_rsp	2.016m	6.641ms	100	100	100.00
		xbar_random_zero_delays	57.660s	574.417us	100	100	100.00
		xbar_random_large_delays	23.060m	115.669ms	100	100	100.00
		xbar_random_slow_rsp	21.399m	67.846ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.024m	1.400ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.065m	1.414ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.502m	2.467ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.065m	1.414ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.494m	3.326ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.188m	163.463ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.403m	2.707ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	10.653m	15.566ms	100	100	100.00
		xbar_stress_all_with_error	11.549m	18.337ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	13.476m	15.228ms	100	100	100.00
		xbar_stress_all_with_reset_error	23.406m	26.248ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.243h	17.438ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.770s	10.160us	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	40.390s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	37.620s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	38.430s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	38.580s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	37.790s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	42.050s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	39.510s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	38.060s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	38.220s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	37.840s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	37.740s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	38.590s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	39.220s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	38.120s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	39.190s	10.380us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	3	0.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	44.000s	10.180us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.855m	2.604ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.265m	2.900ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.421m	2.767ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.080m	3.377ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	27.172m	8.151ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.011m	19.941ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.011m	19.941ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.430m	3.892ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.273m	5.155ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.430m	3.892ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.884m	9.622ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.884m	9.622ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.020m	6.477ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.002m	5.679ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.974m	5.177ms	3	3	100.00
		chip_sw_aes_idle	5.080m	3.377ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.677m	3.428ms	3	3	100.00
		chip_sw_kmac_idle	5.145m	3.089ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.520m	4.879ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.443m	5.714ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	11.720m	5.203ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.445m	5.226ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	26.704m	9.921ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.081m	4.078ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.452m	4.071ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638m	3.476ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.889m	4.667ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.535m	3.891ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.538m	5.288ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.582m	7.463ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.677m	4.132ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638m	3.476ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.889m	4.667ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	10.734m	4.519ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.187m	5.803ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.009h	19.233ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.265m	2.900ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	15.146m	6.877ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.353m	2.680ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	26.928m	8.962ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.170m	3.184ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.417m	4.373ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.893m	3.081ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.274m	3.461ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.888m	4.759ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.654m	7.597ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.002h	24.748ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.247m	2.495ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	3.933m	2.992ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	27.467m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.598m	2.996ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.506m	4.093ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.071m	23.934ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.017h	18.920ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.582m	7.463ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.819m	3.999ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.642m	3.030ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	23.703m	6.772ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	29.898m	8.651ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.177m	4.855ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.675m	6.677ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.605m	3.103ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.060m	8.139ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	30.237m	21.997ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.842m	3.048ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.510s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.992m	4.541ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	30.237m	21.997ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	30.237m	21.997ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	55.946m	20.799ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	55.946m	20.799ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.326m	5.706ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.011m	19.941ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	46.866m	12.257ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.594m	2.687ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.600m	7.065ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.594m	2.687ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	29.898m	8.651ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.296m	3.498ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	35.529m	20.047ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.964m	5.908ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.187m	5.803ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.351m	3.819ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	10.734m	4.519ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	6.781m	5.413ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	35.529m	20.047ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.448m	3.389ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	6.781m	5.413ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.143m	8.250ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.318m	5.398ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.375m	5.180ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.375m	5.180ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.758m	2.761ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.353m	2.680ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.677m	3.428ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	19.275m	4.975ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	13.223m	5.266ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.823m	4.834ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.598m	4.687ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	26.928m	8.962ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	38.363m	10.010ms	1	3	33.33
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	27.172m	8.151ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.208h	13.842ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.996m	2.745ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.538m	3.084ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.170m	3.184ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.899m	2.491ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.439m	2.385ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.145m	3.089ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.680m	5.284ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	26.317m	18.136ms	5	5	100.00
		chip_tap_straps_rma	10.949m	6.935ms	4	5	80.00
		chip_tap_straps_prod	21.689m	12.369ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.635m	3.039ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	34.547m	10.010ms	1	3	33.33
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.843m	3.366ms	0	3	0.00
		chip_sw_flash_rma_unlocked	6.781m	5.413ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.101m	4.247ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.518m	7.721ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.297m	7.578ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.638m	8.736ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
		chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
		chip_sw_rom_ctrl_integrity_check	9.465m	9.079ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	13.593m	9.779ms	3	3	100.00
		chip_prim_tl_access	5.143m	8.250ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.677m	4.132ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.081m	4.078ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.452m	4.071ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.638m	3.476ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.889m	4.667ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.535m	3.891ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.538m	5.288ms	3	3	100.00
		chip_tap_straps_dev	26.317m	18.136ms	5	5	100.00
		chip_tap_straps_rma	10.949m	6.935ms	4	5	80.00
		chip_tap_straps_prod	21.689m	12.369ms	5	5	100.00
		chip_rv_dm_lc_disabled	9.469m	15.829ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	7.494m	4.395ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	3.337m	3.097ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.752m	2.948ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	6.848m	3.602ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	3.796m	4.065ms	0	3	0.00
		chip_rv_dm_lc_disabled	9.469m	15.829ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3.234m	2.963ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	4.235m	4.380ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	2.902m	3.194ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.268m	3.445ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	3.796m	4.065ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.577m	4.052ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.932m	3.350ms	0	3	0.00
		rom_volatile_raw_unlock			0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	35.529m	20.047ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.932m	4.220ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	11.844m	5.474ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.429m	2.806ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	35.529m	20.047ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.932m	4.220ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.749m	9.971ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	11.844m	5.474ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.429m	2.806ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.137m	15.061ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.635m	3.039ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.101m	4.247ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	23.518m	7.721ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.297m	7.578ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.638m	8.736ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.748m	3.694ms	0	15	0.00
		chip_prim_tl_access	5.143m	8.250ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.143m	8.250ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.721m	9.337ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.889m	20.656ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.348m	7.656ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.829m	6.732ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.458m	6.284ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	25.927m	22.105ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	31.375m	12.713ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	13.884m	9.622ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.982m	13.527ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.214m	4.234ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.721m	9.337ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.398m	4.343ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	55.124m	29.273ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	6.976m	4.696ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.227m	5.250ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.812m	21.204ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	23.060m	8.139ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	34.037m	13.312ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	41.202m	28.535ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.828m	3.224ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.465m	9.079ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.465m	9.079ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	34.037m	13.312ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	36.812m	21.204ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.214m	4.234ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.273m	5.155ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.523m	5.190ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.752m	7.487ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.272m	3.511ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.066m	14.486ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.112m	3.208ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	27.364m	7.553ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.302m	6.428ms	3	3	100.00
		chip_plic_all_irqs_10	9.272m	3.198ms	3	3	100.00
		chip_plic_all_irqs_20	14.893m	4.743ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.433m	2.916ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.100m	3.177ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.243h	17.438ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.015m	6.700ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.672m	4.784ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.631m	3.322ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.573m	2.686ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.844m	5.474ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.417m	4.373ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.881m	8.374ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.044m	8.182ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.593m	9.779ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.395m	5.966ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.944m	2.725ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.776m	3.023ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.602m	3.572ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.082m	3.625ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	34.450m	7.476ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.871h	31.807ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	44.894m	12.159ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	4.891m	3.216ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.680m	5.284ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.561m	3.992ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.066m	14.486ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.671m	6.043ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.336m	3.915ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	28.421m	12.656ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	23.703m	6.772ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	27.364m	7.553ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.331h	255.958ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	37.438m	20.579ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.212m	13.578ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.523m	5.190ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.929m	5.527ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	7.962m	3.607ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	10.949m	6.935ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.469m	15.829ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2480	2627	94.40
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.237m	3.014ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.306m	5.531ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.829m	2.036ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.132m	2.790ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.897m	1.917ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.080h	55.847ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.215h	55.651ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.078h	57.662ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.125m	3.978ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.024m	3.223ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	27.790m	6.505ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	28.212m	7.263ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.143m	3.363ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.790m	6.266ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.739m	4.204ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	8.942m	4.721ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.327m	23.456ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.105m	4.763ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	34.037m	13.312ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.393m	5.292ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	9.994m	3.818ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.178h	19.321ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.829m	2.036ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.132m	2.790ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.897m	1.917ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.051m	6.284ms	3	3	100.00
V3		TOTAL			26	45	57.78
	Unmapped tests	chip_sival_flash_info_access	6.020m	3.437ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.345m	5.283ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.013h	17.250ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	21.018m	5.474ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.544m	4.670ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.341m	5.406ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.981m	2.863ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.939m	3.055ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.717m	3.245ms	3	3	100.00
		TOTAL			2735	2922	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	9	100.00
V1	18	18	16	88.89
V2	281	266	196	69.75
V2S	1	1	1	100.00
V3	90	21	10	11.11

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.67	95.60	94.48	91.84	--	95.40	97.20	99.53

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 48 failures:

Test rom_e2e_shutdown_output has 3 failures.

0.rom_e2e_shutdown_output.28051859418471117601105448145852916865636753392071487588597266998398792753158
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

  (15:57:18) Loading:
  (15:57:19) Loading:
  (15:57:19) Loading: 4 packages loaded
  (15:57:20) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:20) WARNING: Target pattern parsing failed.
  (15:57:20) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:20) INFO: Elapsed time: 29.840s
  (15:57:20) INFO: 0 processes.
  (15:57:20) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_shutdown_output.3023582042618986941536433580500306826804977484365687621932538090871966701135
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

  (16:13:00) Loading:
  (16:13:01) Loading:
  (16:13:01) Loading: 4 packages loaded
  (16:13:01) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:13:01) WARNING: Target pattern parsing failed.
  (16:13:01) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:13:01) INFO: Elapsed time: 18.148s
  (16:13:01) INFO: 0 processes.
  (16:13:01) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.75457696429895398078616653125289464607727220067968777457216553728955784449793
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

  (15:57:19) Loading:
  (15:57:19) Loading:
  (15:57:19) Loading: 4 packages loaded
  (15:57:19) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:19) WARNING: Target pattern parsing failed.
  (15:57:19) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:19) INFO: Elapsed time: 24.488s
  (15:57:19) INFO: 0 processes.
  (15:57:19) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.38784126187892014020541818343632146012718181455741037185646755479926653527624
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  (15:57:16) Loading:
  (15:57:17) Loading:
  (15:57:17) Loading: 4 packages loaded
  (15:57:17) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:17) WARNING: Target pattern parsing failed.
  (15:57:17) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:17) INFO: Elapsed time: 28.449s
  (15:57:17) INFO: 0 processes.
  (15:57:17) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.6789597130356064588459797139944019139224643983953178327398484295399530561246
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  (15:57:14) Loading:
  (15:57:14) Loading:
  (15:57:14) Loading: 4 packages loaded
  (15:57:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:15) WARNING: Target pattern parsing failed.
  (15:57:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:15) INFO: Elapsed time: 19.858s
  (15:57:15) INFO: 0 processes.
  (15:57:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.39716523228918028443435356733350455378079004176171340654271725233034549184823
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  (15:57:53) Loading:
  (15:57:53) Loading:
  (15:57:53) Loading: 4 packages loaded
  (15:57:54) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:54) WARNING: Target pattern parsing failed.
  (15:57:54) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (15:57:54) INFO: Elapsed time: 56.530s
  (15:57:54) INFO: 0 processes.
  (15:57:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 21 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.5252073832984264404658551027769679991550080579597360624470723007984378620977
    Line 393, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2674.012466 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2674.012466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.111167409035016713119127240367373845656111327646384038126398998338866695336463
    Line 379, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2585.731816 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2585.731816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

Test chip_sw_lc_ctrl_transition has 15 failures.

0.chip_sw_lc_ctrl_transition.25974599878072464473332348218569481903836818447883076361166037845835700977670
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 2816.097067 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2816.097067 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_transition.105738601729865906306846178000849781606022875521647234280949119529858931163277
Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4482.603175 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4482.603175 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

0.chip_sw_clkmgr_external_clk_src_for_lc.3771536567791924103941069466111950503414168879645196368068325501640335154990
Line 812, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 4131.600056 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4131.600056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_external_clk_src_for_lc.22276055564696625000605598731761687782793856382313563135982871032042668506920
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3540.934510 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3540.934510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.41605777855983256786113480490175632712099352968306319238515020675340921352766
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 4730.385783 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4730.385783 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.82626767551031544364716998467672775779849751396196780125576003696201022097204
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 3725.914638 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3725.914638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.93069477306759830311221682068258763290650441810205228411488267443763458146933
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 2900.010105 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2900.010105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.11578194053085684458223936126165202938740069309806989837404631385659747236325
Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 4903.543028 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4903.543028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prodend has 3 failures.

0.chip_sw_lc_walkthrough_prodend.1528672238700219768692353833313734963068314890214362781770241607876433424763
Line 837, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3193.817269 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3193.817269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prodend.19129668727407093142270823514277264298421217568946341021817928802553855424571
Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 2875.074584 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2875.074584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.107411962720379838943669517546152034367346015601118063586672882844629872634684
Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 3763.850139 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3763.850139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.106309791984461361392217523890997144569934008480618749058076227417818114237619
Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 3444.959837 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3444.959837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_rma_to_scrap.92795789428725667227669448436760043126359495104815524452299225184119893618458
Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

  UVM_FATAL @ 4395.405072 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4395.405072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_raw_to_scrap.69067841483002796810785280212002406178191807173354075345929791751013710632579
Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

  UVM_FATAL @ 3096.853993 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3096.853993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_test_locked0_to_scrap.16516248869776157185442993058586673328478173607297697337069860507088232680517
Line 731, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

  UVM_FATAL @ 2947.978338 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2947.978338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

0.chip_sw_lc_ctrl_rand_to_scrap.96253838733505865596350161188872815704335378237679544917027237165381913666537
Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3855.587409 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3855.587409 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_rand_to_scrap.81201229672411308713937979334129264242668803181062988503758491209542197476712
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3288.791152 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3288.791152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:
- Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.
  - 0.chip_sw_lc_ctrl_volatile_raw_unlock.89609267343735625930552502524941485014085499727104940648259787797182520282849
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
```
  UVM_FATAL @ 4573.668192 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4573.668192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_ctrl_volatile_raw_unlock.91475113591680496720561919258827714651006800045643247555282535122679471962683
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
```
  UVM_FATAL @ 2936.995677 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2936.995677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.
  - 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.92072922992919593835946804128256478050496831631993990440458385806261810952795
    Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
```
  UVM_FATAL @ 3349.812087 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3349.812087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.25441772274418290544696271347670487945436166584418117853093213714513184146891
    Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
```
  UVM_FATAL @ 3755.976987 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3755.976987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 6 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.84843342154786826749461768612805245929371308653101502051741026668018229081491
    Line 1121, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.94940806211530668518216379387462579202721456607692149043976187107128133307123
    Line 1038, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.115044493186139552881090181837134736508733636689095911107519087306932878988958
    Line 971, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.66168657090361887311945488986496391655457909942446676686327391529195772571200
    Line 965, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.53648343722270772859705686642756002771949454572447146498775009899105879049999
    Line 997, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.74781779607873862903745622303326006148952207137125527007296903538561437547407
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:916c51d7-a5e8-4722-8e94-fb10542165a8
```
  - 1.chip_sw_rv_timer_systick_test.43185731906489578213392959614642979460053698352963937280906459823847797228068
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:6a588fa9-f663-41f0-b80c-b41d03cd980e
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.65410452293403982431452997686752448436662017040527161638694512756055845852949
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:0c2f3d23-2bde-4261-9af5-7426bc394657
```
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.38185746481460112151381608273709808843011413368111146841380740866665039582686
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:89098d80-17ca-4538-a5c9-b8098bf568a3
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 4 failures:
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_key_derivation.23802980140621790660394500704031339276529981890698134501214729279265913577800
    Line 837, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
```
  UVM_FATAL @ 10010.300001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_prod has 2 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.17633396105153090268311735318681577459001096883203468308760878686940380746690
    Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.220001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_prod.115120091187484577587589708538606840666820058159254785042789464007768748835889
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.180001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.7845807788676216622847897972225558243066215876498159496427072556273195601960
    Line 865, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 4.chip_sw_alert_handler_lpg_sleep_mode_alerts.74841985001570232632691369389497919300645794748001331123584345840126795962811
    Line 846, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3915.197216 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3915.197216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.chip_sw_alert_handler_lpg_sleep_mode_alerts.22511362062577939968507923771338901757511121417280572202657823143663244666826
    Line 882, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3310.324400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3310.324400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.9491688389445224890209327193297921091323480498503218744653726864240951292193
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 5179.118761 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 5179.118761 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.112462958594623277084907913955994472588292879548364491296854095038758711487576
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3053.576066 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3053.576066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.29330219426602605257548861740847587752498702196807550409936144068651925958726
    Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3421.603650 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 3421.603650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.10210703143975577033667031654106269493708744689971698271200876802887937753324
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2544.199708 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2544.199708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.17796129272766180146046423796282576973544067311950643496657918694286256576009
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4550.667424 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4550.667424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.16699510702304501351517167688167037318594098064712943942479673760225036069515
    Line 733, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 5413.496360 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 5413.496360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.
  - 0.chip_sw_otp_ctrl_vendor_test_csr_access.77303165862283431546456071923584514010542715423659561412868147969728082832429
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 4636.387218 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4636.387218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_vendor_test_csr_access.1312527722262886731605015837538889587182333878090425583973247948141241306530
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 4203.519255 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4203.519255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 3 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.67686600781601314084473957814199283497187712811802456950295893016900946648649
    Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 2879.976850 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2879.976850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_walkthrough_testunlocks.92055227784382396588283941896210824828018188781363337657763936678864701611114
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 4065.397412 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4065.397412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.111121740462240330892837207705611078555636244563091734466540100038739294237911
    Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.69043179601005819735396864016771972577528067120197522544352133406062030976648
    Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.98413305771139973938820855854990285245189146215769328049485547658595604519818
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15060.604680 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15060.604680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.31117547943509913943297609955131616090871921868526977482071925706036451892185
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15196.711470 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15196.711470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:713) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.93282304204803810689995848888823533994148002760197427511256156908489053522686
    Line 901, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23034.876470 us: (chip_if.sv:713) [chip_if] wait timeout occurred!
  UVM_INFO @ 23034.876470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.45867815941751834017804949115116277055449340459113316589883589832038818111349
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23009.084252 us: (chip_if.sv:713) [chip_if] wait timeout occurred!
  UVM_INFO @ 23009.084252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.99462890636755050622274119905496954040512222995225678624565133853820870600944
    Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3607.268354 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3607.268354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.6388312674002268568883660919158504888036855010581980181537406172094925920140
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3950.087080 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3950.087080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.107328526869538699975635331339051180755948588472282249126777905844643000074451
    Line 1019, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_shutdown_exception_c.35609266607415957736302672059889592195065352278077124208430387591486238460315
    Line 1010, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.27788686896129358845995798378104919515341548925625646654557680767264478957628
    Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.51646095701949380946475461620541591265843538790607121212984023170269789623073
    Line 1001, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.113996011608134372784795259092504468855552194746050001378554727472372441185391
    Line 1106, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.94216755888024209995784402753276420293974998376318887055131484886711129947101
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2035.558000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2035.558000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.4406686477975875364180019266648759049795217052838751264171312962657954443593
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2790.422500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2790.422500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.76390454666789656518353661266389661937863491567541607100357440529024499523762
    Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 1917.344500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1917.344500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.34668806792089428311173314867138181071307566208337864655519148500922284583436
    Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 55847.296319 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 55847.296319 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.10814738208958433893854274375954841660326810050082684399468810390336876638401
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 55650.842454 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 55650.842454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.77936956778612620385481769600231093125096256344604351795239088859939201612158
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 57661.916663 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 57661.916663 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.6803457620372280947379857269646349160134944561601714765813915401078062536747
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_static_critical.45694864790344205014444944132880067587441990814494128792409031674395840294005
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 31.chip_sw_all_escalation_resets.1351281708347386351679044296930027284010662233741132569620841436983508354749
    Line 871, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2571.147600 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2571.147600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 73.chip_sw_all_escalation_resets.69054179009633274347886787496202767483372860916924540219668865895090010138616
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/73.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3331.117172 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3331.117172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 2 failures:
- Test chip_sw_keymgr_sideload_kmac has 2 failures.
  - 0.chip_sw_keymgr_sideload_kmac.69540937764282639919441448522102568728954633489762139192522047156339304591599
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_sideload_kmac.5553025770827619922796536631225715949199067102603940141007984278792466436672
    Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.87242526268151970846138681683858293378891002340777838252217263216925002407595
    Line 1051, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.61378936696153394434236027015431591788485945154095109138056953539210002162097
    Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.6431644494804428872565703899393990089182235527438812876571821074364684684705
    Line 1103, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.115084915591766460724247805535417930910421344389804005359200864402257918475024
    Line 1092, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.60279588356918925578420959215861032430913062183457764076483231113521370996123
    Line 989, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5082.873872 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5082.873872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.4916266378443918771768636205416411799071105116096687471510651806438689076558
    Line 1159, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5530.705643 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5530.705643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test chip_tap_straps_rma has 1 failures.
  - 0.chip_tap_straps_rma.32492357903980438171433392819534492440906445478249779022014397732805561206169
    Line 5953, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_rma/latest/run.log
```
  UVM_ERROR @ 4381.552925 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 4381.552925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.50448147427141750782424964852569595577727072915161170107844067931956697978023
    Line 968, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.107795155773211416533626947774279269915638427801604038851413606384262002254593
    Line 1069, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 1.chip_csr_aliasing.106831802585075596431426315451352315233621042437092987437418097368197429151141
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:d300c665-a8f1-48c8-a378-257eef10e9a3
```
UVM_ERROR @ * us: (cip_base_vseq.sv:250) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 11.chip_same_csr_outstanding.32111364928593411751440891195303220127997249297467643732000077330048346780150
    Line 3803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/11.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 16894.905534 us: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x40090078 read out mismatch
  UVM_INFO @ 16894.905534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```