CHIP Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.848m	2.541ms	3	3	100.00
		chip_sw_example_rom	2.226m	2.886ms	3	3	100.00
		chip_sw_example_manufacturer	4.448m	2.653ms	3	3	100.00
		chip_sw_example_concurrency	5.396m	2.454ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.702m	6.330ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.127m	6.496ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.573h	84.550ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.626h	55.429ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.272m	2.577ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.626h	55.429ms	5	5	100.00
		chip_csr_rw	13.127m	6.496ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.180s	243.500us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.227m	4.376ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.227m	4.376ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.227m	4.376ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	11.651m	3.896ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	11.651m	3.896ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.128m	4.399ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	11.673m	4.114ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.195m	4.773ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	35.733m	13.263ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	45.387m	12.982ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.263m	7.933ms	5	5	100.00
V1		TOTAL			200	220	90.91
V2	chip_pin_mux	chip_padctrl_attributes	6.034m	4.385ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.034m	4.385ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.174m	3.410ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.272m	4.594ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.263m	4.426ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	27.821m	14.657ms	5	5	100.00
		chip_tap_straps_testunlock0	14.066m	8.949ms	5	5	100.00
		chip_tap_straps_rma	16.577m	9.940ms	5	5	100.00
		chip_tap_straps_prod	26.236m	13.369ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.203m	3.772ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.268m	8.722ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.701m	6.233ms	5	6	83.33
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.701m	6.233ms	5	6	83.33
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.215m	6.904ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	46.065m	21.559ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.446m	4.516ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.875m	6.139ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.389m	18.220ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.912m	3.162ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.690m	6.269ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.369m	2.752ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.689m	9.901ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	6.482m	3.470ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.949m	4.703ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.950m	3.100ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.068m	2.669ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	19.518m	8.731ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.698m	4.646ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.630m	2.563ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.698m	4.646ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.124m	3.248ms	3	3	100.00
		chip_sw_aes_smoketest	4.625m	3.009ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.421m	2.887ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.646m	3.325ms	3	3	100.00
		chip_sw_csrng_smoketest	4.186m	2.774ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.076m	3.644ms	3	3	100.00
		chip_sw_gpio_smoketest	5.133m	2.791ms	3	3	100.00
		chip_sw_hmac_smoketest	7.096m	3.264ms	3	3	100.00
		chip_sw_kmac_smoketest	7.196m	3.410ms	3	3	100.00
		chip_sw_otbn_smoketest	35.441m	10.179ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.556m	2.497ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	11.004m	5.927ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.533m	5.587ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.596m	2.796ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.051m	2.312ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.921m	3.172ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.371m	2.900ms	3	3	100.00
		chip_sw_uart_smoketest	4.574m	2.807ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.613m	4.714ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.826h	77.955ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.490m	4.709ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.947m	11.223ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.052h	57.545ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.250h	65.467ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.859m	5.580ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.859m	5.580ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.626h	55.429ms	5	5	100.00
		chip_same_csr_outstanding	1.382h	30.265ms	20	20	100.00
		chip_csr_hw_reset	6.702m	6.330ms	5	5	100.00
		chip_csr_rw	13.127m	6.496ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.626h	55.429ms	5	5	100.00
		chip_same_csr_outstanding	1.382h	30.265ms	20	20	100.00
		chip_csr_hw_reset	6.702m	6.330ms	5	5	100.00
		chip_csr_rw	13.127m	6.496ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.674m	2.689ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.470s	54.707us	100	100	100.00
		xbar_smoke_large_delays	2.084m	11.339ms	100	100	100.00
		xbar_smoke_slow_rsp	2.051m	7.161ms	100	100	100.00
		xbar_random_zero_delays	57.680s	635.423us	100	100	100.00
		xbar_random_large_delays	23.078m	109.561ms	100	100	100.00
		xbar_random_slow_rsp	21.092m	71.196ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.102m	1.350ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.003m	1.447ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.628m	2.443ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.003m	1.447ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.710m	3.700ms	100	100	100.00
		xbar_access_same_device_slow_rsp	48.490m	149.171ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.478m	2.553ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	18.921m	23.600ms	100	100	100.00
		xbar_stress_all_with_error	14.664m	24.634ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.202m	22.360ms	100	100	100.00
		xbar_stress_all_with_reset_error	11.919m	6.431ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.780s	10.100us	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	37.780s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	40.510s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	39.720s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	38.770s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	41.060s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	41.700s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	39.680s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	40.320s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	38.960s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	41.270s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	40.380s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	39.410s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	41.110s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	38.570s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	37.820s	10.300us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	3	0.00
		rom_e2e_asm_init_dev			0	3	0.00
		rom_e2e_asm_init_prod			0	3	0.00
		rom_e2e_asm_init_prod_end			0	3	0.00
		rom_e2e_asm_init_rma			0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.920s	10.140us	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.125m	2.224ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.912m	3.162ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.968m	3.306ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.160m	2.714ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	39.601m	10.010ms	2	3	66.67
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.834m	18.518ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.834m	18.518ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.972m	4.276ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	11.004m	5.927ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.972m	4.276ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.860m	9.568ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.860m	9.568ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.218m	7.263ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.901m	6.049ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.056m	5.392ms	3	3	100.00
		chip_sw_aes_idle	5.160m	2.714ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.733m	2.621ms	3	3	100.00
		chip_sw_kmac_idle	5.619m	3.425ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.550m	5.488ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.865m	3.955ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.204m	5.527ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.719m	6.000ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	23.388m	11.261ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.477m	4.464ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.654m	4.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.515m	4.475ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.213m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.563m	4.015ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.532m	4.634ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.215m	6.904ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.968m	8.966ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.515m	4.475ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.213m	4.449ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.446m	4.516ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.875m	6.139ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.389m	18.220ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.912m	3.162ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.690m	6.269ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.369m	2.752ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	29.689m	9.901ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	6.482m	3.470ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.949m	4.703ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.950m	3.100ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.480m	3.316ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.423m	5.520ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.648m	6.954ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.228h	25.187ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.668m	3.213ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.416m	3.183ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	32.631m	10.010ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.234m	3.047ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.425m	5.569ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	34.997m	24.716ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	52.215m	16.400ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.215m	6.904ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.183m	5.364ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.750m	3.119ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	35.501m	8.831ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	33.576m	7.402ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.656m	3.809ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.787m	5.837ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.732m	2.746ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.907m	6.497ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	25.147m	22.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.215m	2.825ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	46.000s	10.180us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	14.474m	4.855ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	25.147m	22.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	25.147m	22.731ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	57.532m	19.998ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	57.532m	19.998ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.318m	4.854ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.834m	18.518ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	50.845m	15.732ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.461m	2.737ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.565m	6.739ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.461m	2.737ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	33.576m	7.402ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.941m	3.067ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	40.873m	26.080ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.235m	6.230ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.875m	6.139ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.428m	4.386ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.446m	4.516ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.344h	44.077ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	40.873m	26.080ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.918m	3.951ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.344h	44.077ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.789m	12.315ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.926m	5.822ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.169m	5.050ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.169m	5.050ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.604m	3.008ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.369m	2.752ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.733m	2.621ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.584m	6.081ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.152m	4.765ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.831m	4.958ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.422m	3.492ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	29.689m	9.901ms	0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	33.940m	9.864ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	39.601m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.172h	20.016ms	2	3	66.67
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	6.109m	2.991ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.902m	2.965ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.482m	3.470ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.007m	2.007ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.763m	2.703ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.619m	3.425ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.713m	4.829ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	27.821m	14.657ms	5	5	100.00
		chip_tap_straps_rma	16.577m	9.940ms	5	5	100.00
		chip_tap_straps_prod	26.236m	13.369ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.193m	2.929ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	32.192m	10.010ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	6.126m	3.009ms	0	3	0.00
		chip_sw_flash_rma_unlocked	1.344h	44.077ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.291m	4.366ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.810m	3.568ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.495m	3.939ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	8.295m	3.371ms	0	3	0.00
		chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
		chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	11.242m	8.287ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.116m	8.525ms	3	3	100.00
		chip_prim_tl_access	9.789m	12.315ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.968m	8.966ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.477m	4.464ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.654m	4.512ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.515m	4.475ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.213m	4.449ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.563m	4.015ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.532m	4.634ms	3	3	100.00
		chip_tap_straps_dev	27.821m	14.657ms	5	5	100.00
		chip_tap_straps_rma	16.577m	9.940ms	5	5	100.00
		chip_tap_straps_prod	26.236m	13.369ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.392m	11.313ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.760m	3.293ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.994m	2.704ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.289m	3.069ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.400m	2.842ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	34.462m	28.637ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.392m	11.313ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.530h	47.037ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.674h	47.178ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.137m	9.781ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.529h	45.300ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	34.462m	28.637ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.093m	2.456ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.015m	2.655ms	3	3	100.00
		rom_volatile_raw_unlock			0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	40.873m	26.080ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.717m	3.772ms	3	3	100.00
		chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.038m	4.489ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.400m	3.287ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	40.873m	26.080ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.717m	3.772ms	3	3	100.00
		chip_sw_keymgr_key_derivation	28.060m	10.079ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.038m	4.489ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.400m	3.287ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.529m	15.516ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.193m	2.929ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	10.291m	4.366ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.810m	3.568ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.495m	3.939ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	8.295m	3.371ms	0	3	0.00
		chip_sw_lc_ctrl_transition	16.345m	9.333ms	15	15	100.00
		chip_prim_tl_access	9.789m	12.315ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.789m	12.315ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.767m	7.477ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	33.357m	19.050ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.264m	7.277ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.717m	7.875ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.019m	6.224ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	27.418m	22.415ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	24.101m	14.803ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.860m	9.568ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.238m	12.789ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.739m	3.836ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.767m	7.477ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.627m	4.895ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	47.117m	45.950ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.206m	6.020ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.212m	5.662ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.758m	26.943ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.907m	6.497ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	33.830m	13.507ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.816m	25.714ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.044m	3.109ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.242m	8.287ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.242m	8.287ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	33.830m	13.507ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.758m	26.943ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.739m	3.836ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	11.004m	5.927ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.177m	4.488ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.933m	6.150ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.758m	3.545ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	29.748m	13.421ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.564m	2.477ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	32.860m	8.904ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	19.971m	6.644ms	3	3	100.00
		chip_plic_all_irqs_10	10.310m	3.520ms	3	3	100.00
		chip_plic_all_irqs_20	13.784m	4.675ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.586m	2.709ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.978m	3.073ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.149m	7.644ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.452m	5.004ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.376m	2.684ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.163m	2.755ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.038m	4.489ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.949m	4.703ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.376m	7.215ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.289m	6.162ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.116m	8.525ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
		chip_sw_data_integrity_escalation	14.701m	6.233ms	5	6	83.33
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.404m	3.110ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.445m	2.922ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.037m	4.104ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.955m	3.591ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	33.275m	8.204ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.853h	31.861ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	46.584m	12.670ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.592m	2.722ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.713m	4.829ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.856m	2.960ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	29.748m	13.421ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.867m	5.405ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.844m	3.570ms	84	90	93.33
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	28.024m	10.822ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	35.501m	8.831ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	32.860m	8.904ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.534h	254.664ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	21.053m	10.706ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	31.858m	13.371ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.177m	4.488ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.404m	5.116ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.414m	4.160ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	16.577m	9.940ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.392m	11.313ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2506	2627	95.39
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.156m	3.378ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.366m	5.886ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.732m	2.098ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.275m	2.747ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.762m	2.387ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.248h	50.567ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.304h	50.441ms	0	1	0.00
		rom_e2e_jtag_inject_rma	52.994m	60.000ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.391m	3.442ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.610m	2.486ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.894m	4.392ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	32.523m	8.458ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.230m	3.036ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	19.760m	5.875ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	6.321m	2.697ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.570m	5.216ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	7.906m	23.311ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.370m	5.619ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	33.830m	13.507ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.262m	4.479ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	11.651m	3.896ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.128h	19.111ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.732m	2.098ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.275m	2.747ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.762m	2.387ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.671m	5.179ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.002m	2.572ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.763m	5.133ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.065h	17.742ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.207m	5.479ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.981m	4.637ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.850m	6.356ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.834m	3.249ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.326m	2.278ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2762	2922	94.52

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	18	18	17	94.44
V2	280	266	204	72.86
V2S	1	1	1	100.00
V3	91	21	11	12.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.00	95.32	93.72	95.59	--	94.49	97.38	99.52

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 54 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.51022048853953631942025601807502978571652177546121332907827363259275298609474
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:16:01) Loading:
  (16:16:02) Loading:
  (16:16:02) Loading: 4 packages loaded
  (16:16:02) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:16:02) WARNING: Target pattern parsing failed.
  (16:16:02) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:16:02) INFO: Elapsed time: 17.352s
  (16:16:02) INFO: 0 processes.
  (16:16:02) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.39060361286809903268849583375324349713241804948460737464383358665391314710822
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:27:21) Loading:
  (16:27:21) Loading:
  (16:27:21) Loading: 4 packages loaded
  (16:27:21) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:27:21) WARNING: Target pattern parsing failed.
  (16:27:21) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:27:21) INFO: Elapsed time: 17.917s
  (16:27:21) INFO: 0 processes.
  (16:27:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_smoke has 3 failures.

0.rom_e2e_smoke.26988753118177628294557064014159923479188939123503327539906113198910991778274
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log

  (16:17:29) Loading:
  (16:17:31) Loading:
  (16:17:31) Loading: 4 packages loaded
  (16:17:31) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:31) WARNING: Target pattern parsing failed.
  (16:17:31) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:32) INFO: Elapsed time: 75.569s
  (16:17:32) INFO: 0 processes.
  (16:17:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_smoke.79953946014842229481526739588971664667321565014066940389412816866052088089417
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log

  (16:28:26) Loading:
  (16:28:27) Loading:
  (16:28:27) Loading: 4 packages loaded
  (16:28:27) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:28:27) WARNING: Target pattern parsing failed.
  (16:28:27) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:28:27) INFO: Elapsed time: 20.757s
  (16:28:27) INFO: 0 processes.
  (16:28:27) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_shutdown_output has 3 failures.

0.rom_e2e_shutdown_output.76713084790340442999866544231280206868434885951913057792720455054062483824886
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

  (16:17:00) Loading:
  (16:17:01) Loading:
  (16:17:01) Loading: 4 packages loaded
  (16:17:01) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:01) WARNING: Target pattern parsing failed.
  (16:17:01) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:01) INFO: Elapsed time: 24.490s
  (16:17:01) INFO: 0 processes.
  (16:17:01) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_shutdown_output.3387584457702707925537780250136770991175550374983638629930318371547795733243
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

  (16:28:31) Loading:
  (16:28:32) Loading:
  (16:28:32) Loading: 4 packages loaded
  (16:28:32) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:28:32) WARNING: Target pattern parsing failed.
  (16:28:32) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:28:32) INFO: Elapsed time: 17.774s
  (16:28:32) INFO: 0 processes.
  (16:28:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.61143909938818397322291345243642984874054436576233992594192392600582763819188
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

  (16:17:28) Loading:
  (16:17:28) Loading:
  (16:17:28) Loading: 4 packages loaded
  (16:17:29) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:29) WARNING: Target pattern parsing failed.
  (16:17:29) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:29) INFO: Elapsed time: 47.558s
  (16:17:29) INFO: 0 processes.
  (16:17:29) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.112835046974474876732338025464481302425909933903565355771333471360818776893170
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  (16:17:07) Loading:
  (16:17:08) Loading:
  (16:17:08) Loading: 4 packages loaded
  (16:17:08) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:08) WARNING: Target pattern parsing failed.
  (16:17:08) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
  (16:17:09) INFO: Elapsed time: 25.712s
  (16:17:09) INFO: 0 processes.
  (16:17:09) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 23 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.103441102276625865083950691413034884782306538156433128187170621609157963215095
    Line 364, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2576.625835 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2576.625835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.77657834560222823999482207777429060109924734447886810987449326234896512560501
    Line 371, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3082.558061 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3082.558061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: *, expected to be * has 9 failures:
- Test chip_sw_otp_ctrl_lc_signals_dev has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_dev.7903317610345434889598431381502307213766181449365928562786092764541153338788
    Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log
```
  UVM_ERROR @ 3568.180180 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 3568.180180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_lc_signals_dev.58372254872702062292492519459117083560395876965128308753713815380665216560044
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log
```
  UVM_ERROR @ 4361.087440 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 4361.087440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_otp_ctrl_lc_signals_prod has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_prod.775561281719860666741140128695903883031021163780416559303045520261452438712
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log
```
  UVM_ERROR @ 2971.301300 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 2971.301300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_lc_signals_prod.78468256926809981998566879040772841208847567800130421489522235183782198158880
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log
```
  UVM_ERROR @ 3546.073934 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 3546.073934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_otp_ctrl_lc_signals_rma has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.12560534446308487634872811832602803175221575809167019628948727720594807424358
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 3284.996864 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 3284.996864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_lc_signals_rma.104228767558753989730440347467942719293924343677415373521461704313714597034582
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 2981.273280 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
  UVM_INFO @ 2981.273280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 7 failures:
- Test chip_sw_keymgr_key_derivation_jitter_en has 2 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en.41306302973337086708892410685699944398608032889491042758114172828523096859533
    Line 859, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @ 10010.260001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_keymgr_key_derivation_jitter_en.79484327837720962432142300385707311749141647729184648987440974937647697229760
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.94267131118328492580483408734423908242611693420223568408259169084842346665015
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.77817842021957332790220863777280917647715242181441881643169269275348772937640
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation_prod has 2 failures.
  - 1.chip_sw_keymgr_key_derivation_prod.84478256495249912276561203407334025167298769538352039663391647823453666057128
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.260001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_keymgr_key_derivation_prod.80567510741646008234442198198845209734555192163991273673563613363464112266783
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.300001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.40709017351288236520505531477211555835823665628061327900457083350454005759247
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:b6fd5fe1-73b8-4411-b49e-725dfcd29619
```
  - 1.chip_sw_rv_timer_systick_test.34058880060180867627568263467332352113238655440786387463755671487401025581532
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:abe24053-e8c6-4af8-b692-29eaf06d84ae
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.72408062775329048523578431977959344981385424985096112637427619658057599029631
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:29456756-ae57-4bf6-8a32-6310d4db79c7
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.72127517631531163853383072901850475632845582148216230286495785871557006889807
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:bafb8a5a-5bd9-4698-a098-fffc8b871892
```
- Test chip_sw_power_virus has 1 failures.
  - 2.chip_sw_power_virus.103169749170742705522436809319237628584262801378021985554452049573466370008176
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:64edc011-0900-4b4c-8254-4322a37d7df1
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 6 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.64082646271472988402568983851370284558873115148628126063198276740842901625813
    Line 1026, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.107023631639880230908103616101514589588238835047108733661504012208158464906317
    Line 1051, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.37027233342435083612000982219649868452188457856361095857290541826323665047087
    Line 1037, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.97755333503355840069467697697797911484474017973910799594099912338408143022360
    Line 1005, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.74696001740312608422646602203564437755804707071832703639670877132731796737689
    Line 1022, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 6 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 6 failures.
  - 34.chip_sw_alert_handler_lpg_sleep_mode_alerts.105375691120673674369620301163585769235266035331516595106066473995963162561415
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3530.745840 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 3530.745840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.chip_sw_alert_handler_lpg_sleep_mode_alerts.28748968321458617922554703439441948717057873444511639922194660794844276334945
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4012.091996 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
  UVM_INFO @ 4012.091996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '$stable(key_data_i)' has 5 failures:
- Test chip_sw_keymgr_key_derivation has 3 failures.
  - 0.chip_sw_keymgr_key_derivation.69860346569010645987018181041617095236090570584949981551635118077984909450021
    Line 856, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 6979.059356 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 6979.059356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_keymgr_key_derivation.107392837388819599217146589238680603371851942877152568059361398060529342889794
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 10078.949120 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 10078.949120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.88852321725238225886904537691247037503780387754973540582389958460505186496486
    Line 850, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 6782.851878 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 6782.851878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.
  - 1.chip_sw_keymgr_key_derivation_jitter_en.41177692284044596222128522949171195289904757830300339515210616947994877570715
    Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 9901.032405 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 9901.032405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 1.chip_sw_all_escalation_resets.59351726496698955703163759422558825974589241143929907067130824249614237909815
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3169.153350 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3169.153350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.chip_sw_all_escalation_resets.76452707490222614993245372151544912574080660103523581167897510051779529879089
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3421.986632 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3421.986632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.1867440447473028773485071674983484449033604464861646363525642055620394099269
    Line 740, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3009.074680 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 3009.074680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.87815470963376195630889939070593502532811717000408748810319892066044513454171
    Line 889, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2891.670382 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2891.670382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.106302967469497851605656543277957534116163143468210225006890257542682411893154
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.106128512086763073772485105621522174560935997913533991468255616670357478759025
    Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.84778877600010187155001360401063766703128936576073043692697376681516404809015
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14711.902880 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14711.902880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.94831053056829483117491851828244096270044126900204619274729899586764453138873
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15516.256672 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15516.256672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.86829122405804383357104239825221955991653933222109689865573438491587000223985
    Line 872, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23310.576704 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23310.576704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.16616537638913684436573943873493455388692561681117641149200208393034008073065
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 23083.753574 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
  UVM_INFO @ 23083.753574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.40290635638816798913173504314350224892881624367759745698257015470515153886737
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 4019.696747 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 4019.696747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.4853327695782251764039461096201127032962355962974654476833306788044202078852
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3883.153671 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3883.153671 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.55088868678785347035016738396265281199482799117777092687226023844524817057851
    Line 967, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_shutdown_exception_c.16207680796152402061187817521066065008878982499725990609681745740268186044900
    Line 1017, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.103736520975665061371373499228061203750126930639016392517119638361235825518990
    Line 1042, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.9578794143842854222777853665680297325129891966226606144154423034680193030037
    Line 1000, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.104118870562756371527784819652028125276720533514698131992382048996256500314023
    Line 984, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.79098027015908201833974076104745476351461846542437944465900513023864176227167
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2097.865500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2097.865500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.100100149521902106316523853833798840378161910169732477013195235144639019627216
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2747.235000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2747.235000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.60545427932366844609717139288732603907140914206131616471615020903883211564197
    Line 730, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2386.517000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2386.517000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.13039178714401094611598478691173197350456887782168121949213094605440097681844
    Line 916, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_static_critical.27504356857712666814953944897004748774607508855446449903848470338529479763432
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.27494776065467105868167874632902492836415413529403642469173547823825788511866
    Line 1015, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5480.499199 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5480.499199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.25352250233839876508898774343552834436973085220448545886743754389878285615133
    Line 1028, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5886.223012 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5886.223012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.111911420904834522288619315446089931781249785085515248550037730531878375186315
    Line 1027, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.38699590054095589186618865570150784255925297976282752731493305233967982097620
    Line 980, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.6657154926484996033948465609052047882107673174844799851929314308161514524974
    Line 1088, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.18130994237981208993400322798241937790338392840003919983583295564581073621632
    Line 988, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.98970373435098959682303681024231857183556202942912369992673356906521835559794
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50566.810263 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50566.810263 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.31317593937145932998476576322844247979905425252301487317164709651818973885505
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 50440.739578 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50440.739578 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 1 failures:
- Test chip_sw_keymgr_sideload_aes has 1 failures.
  - 0.chip_sw_keymgr_sideload_aes.71963735097343872380691704548687888212254836541945362084425351109849568898841
    Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_FATAL @ 10010.320001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
  UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.25230910502801675281992568949360177510097626149550387588376968820881092338335
    Line 1010, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.85368177980816457745340057186497949683115404175527180859604808163185634814825
    Line 952, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.9791415160355619186880053261646469508192002248795827961260338871959565738866
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_keymgr_sideload_otbn has 1 failures.
  - 1.chip_sw_keymgr_sideload_otbn.59133918249312402167203290168723111027347419061890320644760113871334773231924
    Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @ 20016.167450 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.167450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.13810869128936793668033370218842301223147527043389177660225649987074427452554
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6015.329190 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6015.329190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(seen_exception_pc_set || exception_pc_set)' has 1 failures:
- Test chip_sw_data_integrity_escalation has 1 failures.
  - 5.chip_sw_data_integrity_escalation.15478902125244801191680018835243064694074566792205444096007234022664553079197
    Line 907, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/5.chip_sw_data_integrity_escalation/latest/run.log
```
      Offending '(seen_exception_pc_set || exception_pc_set)'
  UVM_ERROR @ 3373.011140 us: (ibex_controller.sv:993) [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
  UVM_INFO @ 3373.011140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```