18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 5.040m | 2.987ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.045m | 2.312ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.986m | 2.811ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.809m | 2.480ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 8.196m | 7.709ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.728m | 5.915ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 2.167h | 74.057ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.917h | 69.655ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 1.968m | 2.809ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.917h | 69.655ms | 4 | 5 | 80.00 |
| chip_csr_rw | 11.728m | 5.915ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.900s | 266.503us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.872m | 4.132ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.872m | 4.132ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.872m | 4.132ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 11.364m | 4.657ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 11.364m | 4.657ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 12.139m | 5.123ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.300m | 4.163ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 14.530m | 4.252ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 38.258m | 13.054ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 48.662m | 13.123ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 24.866m | 13.252ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 199 | 220 | 90.45 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.625m | 5.733ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.625m | 5.733ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.141m | 3.172ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 6.433m | 4.339ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 4.839m | 3.317ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 28.114m | 14.163ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 14.420m | 9.196ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.558m | 8.253ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.759m | 10.299ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.305m | 2.896ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 20.372m | 8.210ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 11.597m | 5.850ms | 5 | 6 | 83.33 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 11.597m | 5.850ms | 5 | 6 | 83.33 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 14.776m | 6.888ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 26.041m | 15.930ms | 1 | 3 | 33.33 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.277m | 4.102ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.106m | 5.892ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.167h | 19.038ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.677m | 2.630ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.336m | 6.351ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.179m | 3.137ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 42.731m | 10.010ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.939m | 2.840ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.818m | 5.111ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.865m | 2.682ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.868m | 2.939ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 18.466m | 8.937ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.200m | 5.323ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 3.749m | 3.106ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.200m | 5.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.748m | 2.623ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.973m | 3.359ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.005m | 2.946ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.200m | 2.999ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.375m | 2.893ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 10.028m | 4.599ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.248m | 2.594ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.407m | 3.391ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.126m | 3.218ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 36.327m | 10.840ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 4.127m | 2.657ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.045m | 4.052ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.277m | 4.749ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.259m | 3.035ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 3.873m | 2.543ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.786m | 2.634ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.255m | 3.211ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.708m | 2.707ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.070m | 5.099ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.692h | 76.752ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.097h | 17.280ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 3 | 0.00 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.691m | 3.836ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 10.286m | 10.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.879h | 57.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.284h | 64.916ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 6.808m | 3.986ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 6.808m | 3.986ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.917h | 69.655ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.282h | 28.065ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.196m | 7.709ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.728m | 5.915ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.917h | 69.655ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.282h | 28.065ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.196m | 7.709ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.728m | 5.915ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.519m | 2.241ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 6.980s | 44.766us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.843m | 9.887ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.947m | 6.459ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 58.830s | 556.225us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.952m | 107.570ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 21.070m | 68.190ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.054m | 1.367ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.450s | 1.590ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.604m | 2.543ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.450s | 1.590ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.485m | 3.645ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 57.932m | 188.466ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.294m | 2.598ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 10.982m | 16.760ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 13.772m | 22.251ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 20.147m | 18.398ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 28.664m | 35.142ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.097h | 17.280ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 45.480s | 10.160us | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 1 | 0.00 | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 1 | 0.00 | ||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 38.870s | 10.280us | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 40.630s | 10.140us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 39.440s | 10.400us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 38.870s | 10.300us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 41.860s | 10.100us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 38.650s | 10.160us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 39.080s | 10.240us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 38.950s | 10.240us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 38.900s | 10.260us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 40.020s | 10.280us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 42.230s | 10.260us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 38.650s | 10.320us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 41.790s | 10.300us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 41.960s | 10.380us | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 42.030s | 10.380us | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_dev | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_prod_end | 0 | 3 | 0.00 | ||||
| rom_e2e_asm_init_rma | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 3 | 0.00 | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 43.080s | 10.100us | 0 | 3 | 0.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.722m | 3.265ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.677m | 2.630ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.852m | 2.659ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 6.974m | 2.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 32.009m | 10.010ms | 2 | 3 | 66.67 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.394m | 18.358ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.394m | 18.358ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.668m | 4.122ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.045m | 4.052ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.668m | 4.122ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.661m | 8.411ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.661m | 8.411ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.938m | 7.617ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.635m | 4.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.165m | 5.889ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 6.974m | 2.904ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.806m | 2.773ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.823m | 2.877ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.646m | 4.340ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 10.115m | 4.308ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.293m | 4.118ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 10.433m | 5.068ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 21.889m | 12.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.796m | 4.275ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.599m | 4.317ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.331m | 3.963ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.886m | 4.617ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.196m | 4.636ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.084m | 4.174ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 14.776m | 6.888ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 10.233m | 6.104ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.331m | 3.963ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.886m | 4.617ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.277m | 4.102ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.106m | 5.892ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.167h | 19.038ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.677m | 2.630ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.336m | 6.351ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.179m | 3.137ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 42.731m | 10.010ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.939m | 2.840ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.818m | 5.111ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.865m | 2.682ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.698m | 2.774ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 11.423m | 5.001ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 20.322m | 7.742ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.333h | 24.882ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.261m | 3.083ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.200m | 3.268ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 20.678m | 10.137ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.721m | 3.167ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.266m | 5.034ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 31.888m | 21.625ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 52.674m | 23.358ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 14.776m | 6.888ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 12.056m | 4.491ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.989m | 4.051ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 32.380m | 8.739ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 22.316m | 5.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.334m | 5.127ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 14.472m | 6.956ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.757m | 2.715ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.982m | 8.455ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.451m | 25.042ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.336m | 3.206ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 41.190s | 10.140us | 0 | 3 | 0.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 12.683m | 4.638ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.451m | 25.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.451m | 25.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.140m | 20.927ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.140m | 20.927ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.763m | 6.334ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 12.394m | 18.358ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.242h | 23.777ms | 3 | 3 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.446m | 2.404ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 25.886m | 7.361ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.446m | 2.404ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 22.316m | 5.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.350m | 2.458ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 39.818m | 25.006ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.230m | 6.222ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.106m | 5.892ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.246m | 4.175ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 11.277m | 4.102ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.490h | 43.619ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 39.818m | 25.006ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.451m | 3.431ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.490h | 43.619ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 9.065m | 14.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.541m | 5.564ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.704m | 4.794ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 13.704m | 4.794ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.974m | 3.159ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.179m | 3.137ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.806m | 2.773ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 16.014m | 5.457ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 15.818m | 4.882ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 15.724m | 4.911ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.948m | 3.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 42.731m | 10.010ms | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 28.560m | 8.065ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 32.009m | 10.010ms | 2 | 3 | 66.67 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.198h | 15.205ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.827m | 3.060ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.044m | 2.619ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 4.939m | 2.840ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.640m | 2.912ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.362m | 3.045ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.823m | 2.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 11.242m | 6.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 28.114m | 14.163ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 12.558m | 8.253ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.759m | 10.299ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.688m | 3.464ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 35.859m | 9.421ms | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 4.702m | 3.137ms | 0 | 3 | 0.00 |
| chip_sw_flash_rma_unlocked | 1.490h | 43.619ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.977m | 4.862ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 8.449m | 3.050ms | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 7.948m | 3.868ms | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 8.732m | 3.758ms | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 10.092m | 8.465ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.774m | 7.842ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 9.065m | 14.705ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 10.233m | 6.104ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.796m | 4.275ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.599m | 4.317ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.331m | 3.963ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 9.886m | 4.617ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.196m | 4.636ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.084m | 4.174ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 28.114m | 14.163ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 12.558m | 8.253ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.759m | 10.299ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 7.737m | 13.646ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.315m | 2.692ms | 0 | 1 | 0.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.143m | 2.885ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.604m | 2.619ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 2.913m | 3.030ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.403m | 33.532ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 7.737m | 13.646ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.592h | 50.207ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.553h | 47.653ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 14.953m | 10.712ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.591h | 48.407ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.403m | 33.532ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.863m | 2.338ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.204m | 2.840ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 0 | 3 | 0.00 | ||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 39.818m | 25.006ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.565m | 3.665ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.905m | 4.479ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.309m | 2.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 39.818m | 25.006ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.565m | 3.665ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 36.321m | 10.010ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.905m | 4.479ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.309m | 2.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 14.814m | 14.924ms | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.688m | 3.464ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.977m | 4.862ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 8.449m | 3.050ms | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 7.948m | 3.868ms | 0 | 3 | 0.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 8.732m | 3.758ms | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_transition | 19.072m | 11.246ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 9.065m | 14.705ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 9.065m | 14.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 12.580m | 8.511ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 30.085m | 17.782ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.963m | 6.768ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.128m | 10.104ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 10.138m | 6.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 29.504m | 22.933ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 30.582m | 16.607ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 15.661m | 8.411ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 24.340m | 9.331ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.627m | 4.276ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 12.580m | 8.511ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 6.689m | 5.328ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 56.283m | 38.927ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.734m | 6.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.902m | 5.162ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 36.640m | 24.554ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 17.982m | 8.455ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 25.968m | 9.107ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 42.034m | 23.917ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.872m | 2.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.092m | 8.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.092m | 8.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 25.968m | 9.107ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 36.640m | 24.554ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.627m | 4.276ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.045m | 4.052ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.622m | 4.218ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.630m | 6.672ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.554m | 4.792ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 24.239m | 10.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.422m | 2.653ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 33.716m | 8.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 22.804m | 5.969ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 9.914m | 4.113ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.324m | 4.414ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.436m | 3.190ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.729m | 2.953ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.097h | 17.280ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.842m | 7.009ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.835m | 4.979ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.258m | 3.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 3.968m | 2.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.905m | 4.479ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 9.818m | 5.111ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 12.699m | 6.895ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 15.185m | 7.608ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.774m | 7.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 11.597m | 5.850ms | 5 | 6 | 83.33 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.167m | 2.647ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.799m | 2.661ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.776m | 3.532ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.152m | 3.708ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 35.316m | 7.928ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.778h | 31.106ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 45.754m | 12.627ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.195m | 3.566ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 11.242m | 6.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.859m | 3.670ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 24.239m | 10.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.360m | 5.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.149m | 4.101ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 30.348m | 13.206ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 32.380m | 8.739ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 33.716m | 8.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.472h | 256.324ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 40.820m | 22.026ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 25.216m | 13.969ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.622m | 4.218ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.877m | 5.355ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.654m | 3.770ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 12.558m | 8.253ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 7.737m | 13.646ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2515 | 2627 | 95.74 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.265m | 2.730ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 17.513m | 5.653ms | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.695m | 2.247ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 1.695m | 1.898ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 2.065m | 2.322ms | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.260h | 50.924ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 1.067h | 45.803ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 1.424h | 50.751ms | 0 | 1 | 0.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.137m | 3.459ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 9.825m | 3.018ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 22.014m | 5.879ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 34.332m | 8.692ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.402m | 3.423ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.951m | 5.248ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.474m | 1.983ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.209m | 4.360ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.284m | 22.506ms | 0 | 3 | 0.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.477m | 4.288ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 25.968m | 9.107ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.530m | 5.198ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 1.839h | 37.855ms | 1 | 3 | 33.33 |
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 1.839h | 37.855ms | 1 | 3 | 33.33 |
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | chip_sw_spi_host_pass_through | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 11.364m | 4.657ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.151h | 18.853ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.695m | 2.247ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 1.695m | 1.898ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 2.065m | 2.322ms | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.370m | 5.932ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 30 | 45 | 66.67 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.917m | 2.924ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 10.607m | 5.072ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 57.275m | 17.652ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 17.723m | 5.040ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 16.531m | 4.388ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 7.529m | 4.859ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 4.648m | 3.122ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 5.646m | 2.692ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 0 | 3 | 0.00 | ||||
| TOTAL | 2771 | 2922 | 94.83 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 9 | 9 | 8 | 88.89 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 280 | 266 | 204 | 72.86 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 91 | 21 | 11 | 12.09 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.29 | 95.41 | 94.46 | 95.56 | -- | 95.36 | 97.38 | 99.57 |
Exit reason: Error: User command failed Job returned non-zero exit code has 51 failures:
Test chip_sw_flash_ctrl_write_clear has 3 failures.
0.chip_sw_flash_ctrl_write_clear.69490630417141407562774282638140181246503628079058217255843954298356899457391
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log
(16:19:28) Loading:
(16:19:28) Loading:
(16:19:28) Loading: 4 packages loaded
(16:19:29) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(16:19:29) WARNING: Target pattern parsing failed.
(16:19:29) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(16:19:29) INFO: Elapsed time: 39.776s
(16:19:29) INFO: 0 processes.
(16:19:29) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.chip_sw_flash_ctrl_write_clear.68359353472657762843438961131838746622702134034399724443933264452534560562230
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log
(16:29:13) Loading:
(16:29:14) Loading:
(16:29:14) Loading: 4 packages loaded
(16:29:14) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(16:29:14) WARNING: Target pattern parsing failed.
(16:29:14) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
(16:29:14) INFO: Elapsed time: 25.583s
(16:29:14) INFO: 0 processes.
(16:29:14) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Test rom_e2e_shutdown_output has 3 failures.
0.rom_e2e_shutdown_output.15465541298208612974109277001527791760648143243405896236009967409381045723503
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
(16:20:29) Loading:
(16:20:29) Loading:
(16:20:29) Loading: 4 packages loaded
(16:20:30) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:20:30) WARNING: Target pattern parsing failed.
(16:20:30) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:20:30) INFO: Elapsed time: 31.076s
(16:20:30) INFO: 0 processes.
(16:20:30) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_shutdown_output.98804217336587051080727386223145539463405793461785650805130118788216328280896
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
(16:30:12) Loading:
(16:30:13) Loading:
(16:30:13) Loading: 4 packages loaded
(16:30:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:30:13) WARNING: Target pattern parsing failed.
(16:30:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:30:13) INFO: Elapsed time: 20.074s
(16:30:13) INFO: 0 processes.
(16:30:13) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.40008806893408656918973992800123197442541127684564904190350064042952487703981
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log
(16:19:59) Loading:
(16:19:59) Loading:
(16:19:59) Loading: 4 packages loaded
(16:19:59) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:19:59) WARNING: Target pattern parsing failed.
(16:19:59) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:19:59) INFO: Elapsed time: 18.163s
(16:19:59) INFO: 0 processes.
(16:19:59) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1220369516279511911549051648956141502249205941878505411853465952566352484299
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log
(16:19:52) Loading:
(16:19:53) Loading:
(16:19:53) Loading: 4 packages loaded
(16:19:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:19:53) WARNING: Target pattern parsing failed.
(16:19:53) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:19:53) INFO: Elapsed time: 18.367s
(16:19:53) INFO: 0 processes.
(16:19:53) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_prod.11546520882059447384658347175027514017480098229985317430636442497045793865471
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log
(16:20:17) Loading:
(16:20:18) Loading:
(16:20:18) Loading: 4 packages loaded
(16:20:18) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:20:18) WARNING: Target pattern parsing failed.
(16:20:18) ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_sim_dv': target 'empty_test_slot_a_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e:*"` to see all the targets in that package)
(16:20:18) INFO: Elapsed time: 29.046s
(16:20:18) INFO: 0 processes.
(16:20:18) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 22 more tests.
UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.chip_csr_mem_rw_with_rand_reset.18288758543758527844135087707322586379723864104841203637365031175188585879483
Line 363, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1827.255785 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1827.255785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_mem_rw_with_rand_reset.15126602945440274058466022691958985566561772865001941747859562304293682394410
Line 361, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2179.652424 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2179.652424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: *, expected to be * has 9 failures:
0.chip_sw_otp_ctrl_lc_signals_dev.75564269284785699463928551476254230587218118218048102152185645907619484678284
Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log
UVM_ERROR @ 2849.844852 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 2849.844852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otp_ctrl_lc_signals_dev.85477798040090379481997795587101403644574114930044020272974192254384588978511
Line 913, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log
UVM_ERROR @ 3212.414968 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 3212.414968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_otp_ctrl_lc_signals_prod.18472577528038399095066538973656746177015659242436167367689349599212172963870
Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log
UVM_ERROR @ 3391.513234 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 3391.513234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otp_ctrl_lc_signals_prod.75303237562516535933280475489212436876892051852487662622715158089902688121270
Line 897, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log
UVM_ERROR @ 4333.240600 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 4333.240600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_otp_ctrl_lc_signals_rma.57016180663862954803414000938036418677687053335476628310311674388890703448344
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
UVM_ERROR @ 3757.894816 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 3757.894816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_otp_ctrl_lc_signals_rma.26970654419972573403311751912312192282018787808435473542709082017080680258984
Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
UVM_ERROR @ 3402.970000 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(w/device/lib/testing/keymgr_testutils.c:247)] CHECK-fail: Keymgr in unexpected state: 6, expected to be 1
UVM_INFO @ 3402.970000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '$stable(key_data_i)' has 7 failures:
Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 2 failures.
0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.7368452131889049161093966856247902120033802000279006168389667535938300809919
Line 834, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 6991.279927 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6991.279927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2296134425513457511519781310965761330504447533140362579136270962655299252662
Line 848, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 10137.362996 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 10137.362996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation has 2 failures.
1.chip_sw_keymgr_key_derivation.40308788041004063770979866288581841190925255625501560898968297463603184121705
Line 820, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 8284.676170 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 8284.676170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_keymgr_key_derivation.42448827808160677084412844302654928966284083279919948252469079006632597592450
Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 6655.533176 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6655.533176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation_prod has 2 failures.
1.chip_sw_keymgr_key_derivation_prod.107517277478304491389302034035527459182220764927091462071589699121154931767922
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 9420.605536 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 9420.605536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_keymgr_key_derivation_prod.97128176473807390739042521307887359033175784285768853859756743148608244164007
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 7714.428492 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 7714.428492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.
1.chip_sw_keymgr_key_derivation_jitter_en.105487066664738479849344335964035312763162302051926835295747743042728693820502
Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 9015.263009 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 9015.263009 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 6 failures:
Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_prod.86187278375549328820759584627161899766217003130548058010716980145104124008586
Line 1028, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.93393832860636954289141913266789099020858830604525988572344209818052508724746
Line 1043, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_rma.11183032083046692026781563663588604891415589604675106584903487833168699637216
Line 1085, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_nothing_prod has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.14138071428181232918229279283380002789722138848965484985944430275207611497742
Line 976, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_nothing_prod_end has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.78555643627282658317877165786977005685395523314049694028338062403508844801340
Line 999, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test chip_sw_rv_timer_systick_test has 2 failures.
0.chip_sw_rv_timer_systick_test.80714858390057175387727973787023554459406974688814055435697201043793442171644
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:8dc501de-93a0-45f2-88c4-3e70dc276d2b
2.chip_sw_rv_timer_systick_test.73702041388478977174623110035077866216672262161001893221751284655634031687715
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:0b9595d2-7e84-49b0-9ec2-ab94d435ff29
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.15989077627310701264683449008358056227328240469034728735404986637546366950298
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job ID: smart:c3ab4705-07a8-4df0-9047-fc0338974bfc
Test chip_sw_ast_clk_rst_inputs has 2 failures.
0.chip_sw_ast_clk_rst_inputs.25969661037266460885829691659823082115940283272321945944953189566947236941948
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:36c92efc-53a9-4bb8-9e5d-0fb9c6499e84
1.chip_sw_ast_clk_rst_inputs.107765124085248832689508600416001429712756649669001362255718877702710519468017
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:4aeaa5e4-0754-403f-adc8-425a98b919a0
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 5 failures:
Test chip_sw_keymgr_key_derivation has 1 failures.
0.chip_sw_keymgr_key_derivation.34880645359998021392093724259198716884826135745937695093897072660588334967591
Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
UVM_FATAL @ 10010.380001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation_prod has 1 failures.
0.chip_sw_keymgr_key_derivation_prod.11808867574408011329578645598048434030567001132949359337509318745747664880853
Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation_jitter_en has 2 failures.
0.chip_sw_keymgr_key_derivation_jitter_en.80648380422386283693529336995169680111876069474339165904773376170841772450430
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10010.280001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_keymgr_key_derivation_jitter_en.14406283954493117421733160229199725249025206513897013506308593515989175378211
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
UVM_FATAL @ 10010.140001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.
1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.29132842145004279717487708300482422892509860040175416713982180114506575791747
Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
0.chip_sw_flash_ctrl_lc_rw_en.19336612705311835341547349695148789881103437244070269850889632769713348871976
Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
UVM_ERROR @ 3035.414712 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
UVM_INFO @ 3035.414712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_flash_ctrl_lc_rw_en.42077321511307557080942674756921227462526749151380540235993920250279981762535
Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
UVM_ERROR @ 3204.873078 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
UVM_INFO @ 3204.873078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
0.chip_sw_sysrst_ctrl_outputs.41229893825206136481790640257058534817590075621231823350777441359339743164131
Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_sysrst_ctrl_outputs.91310398968955271795165923176644464926895701319801532597626554363114197401549
Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
0.chip_sw_lc_ctrl_program_error.109707881798867891283804544095096112061667119208744059356674664053621394544612
Line 908, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14598.088606 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14598.088606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_lc_ctrl_program_error.105150313284362007791942064104467711063995822078032001499045192113595733718473
Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14923.677580 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14923.677580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_if.sv:717) [chip_if] wait timeout occurred! has 3 failures:
0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.38692212896647108805619982219172685431361197669710236900752703377749469816215
Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
UVM_FATAL @ 23212.741050 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
UVM_INFO @ 23212.741050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.50837376917994156836693301749608698923789182925278559902189434012201624188651
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
UVM_FATAL @ 22803.771880 us: (chip_if.sv:717) [chip_if] wait timeout occurred!
UVM_INFO @ 22803.771880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.93231879469121828764062364870506230115476677542113807706386927461384220598977
Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 4174.915089 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 4174.915089 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.16281422910689239602128096092331416149796843353679275968200388285809052401374
Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3769.574196 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3769.574196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 3 failures:
0.chip_sw_power_virus.97919322815429394895726603171599856338434453098040151011371608903064018174233
Line 1060, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5653.332909 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5653.332909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_power_virus.78739384425159061314666138707116659570644473247542251581948784454580348345000
Line 1020, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5295.168741 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5295.168741 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
0.rom_e2e_shutdown_exception_c.92155830292512726778441184346443941911815422751871504272771343287735769853001
Line 1050, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_exception_c.26809846863125724603530678495190347096625125414218985271502189962305659912860
Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_shutdown_exception_c_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.111941574213464070628861386563790801208349696686689731528338228518471831805546
Line 1015, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.86487794654695049795277590364605463233535782921168089216799278762123187037439
Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.114980840358569957233235598993575226332452338118477967493418249863114866311594
Line 1050, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_debug_test_unlocked0.10106280174963208351536428183218129864062371051039806375174410981305004217503
Line 714, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
UVM_FATAL @ 2246.621000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2246.621000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_dev has 1 failures.
0.rom_e2e_jtag_debug_dev.98795926066061673759082185201546489213142932836740806957910121698661907266017
Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
UVM_FATAL @ 1898.115000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 1898.115000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_rma has 1 failures.
0.rom_e2e_jtag_debug_rma.58736583806387821691888246738799921669146840216241036629160668491038841892869
Line 744, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
UVM_FATAL @ 2322.116500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2322.116500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_inject_test_unlocked0.28902552412698012473414748577545909349678832528604618485677819312309708128908
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
UVM_FATAL @ 50924.120305 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 50924.120305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_dev has 1 failures.
0.rom_e2e_jtag_inject_dev.97296788417548902756337682156832955238814481181290728276290625580017946269532
Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
UVM_FATAL @ 45803.074291 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 45803.074291 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_rma has 1 failures.
0.rom_e2e_jtag_inject_rma.109306932089518436113848761206731528956503596604074463120612625610769752187057
Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
UVM_FATAL @ 50750.864363 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 50750.864363 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
0.rom_e2e_static_critical.77173192114709550836088898199440512612084866660741239105459041796847537409948
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_static_critical.98684833188332498791365915932951165177591963106839981402871235281453254331934
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file rom_e2e_static_critical_prog_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.99011509189439377072651874153773538863674632131981912072064681786586632384611
Line 1055, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.75615317557413530270677979288843177888142850972776600536360095645700930836474
Line 1012, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_dev.88137427232650410093200520913456050738199992013498745096430625781614129822128
Line 1041, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.22256122683025078033811671658023945786255551624825772742527383915704241866888
Line 984, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
14.chip_sw_all_escalation_resets.59064528439989352223774573604818850738054594527882460541052084922279440590502
Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/14.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3359.243210 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3359.243210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.chip_sw_all_escalation_resets.80447600482803362157943869379176371198786404164580391686933751186878885586465
Line 881, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3297.596556 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3297.596556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(seen_exception_pc_set || exception_pc_set)' has 1 failures:
0.chip_sw_data_integrity_escalation.108991011264160434660057876426317529143248619583907803399789105121766007993373
Line 938, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log
Offending '(seen_exception_pc_set || exception_pc_set)'
UVM_ERROR @ 3503.517380 us: (ibex_controller.sv:993) [ASSERT FAILED] IbexSetExceptionPCOnSpecialReqIfExpected
UVM_INFO @ 3503.517380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:770) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *cdf* has 1 failures:
0.chip_sw_lc_ctrl_rma_to_scrap.61936158369333158337687544852225393510395038958015065462615618313761018853877
Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log
UVM_ERROR @ 2692.005050 us: (chip_sw_base_vseq.sv:770) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (183792 [0x2cdf0] vs 0 [0x0]) Unexpected status error 2cdf0000
UVM_INFO @ 2692.005050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.69025740628437339617387280385056937345590086519746430481917024892471544886706
Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 6573.302520 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
UVM_INFO @ 6573.302520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.90152816842708814821715133723627482231793741564209570077596827719826470244591
Line 1024, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.17895690447386181831191563158645524637683368103190830227467384358969507006913
Line 973, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:487) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_rsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rst_sys_req[*] || rst_sys_src_n[*])' has 1 failures:
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.20212331895920141500450995047001800487676399461738155568539731573184773778657
Line 783, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
Offending '(rst_sys_req[1] || rst_sys_src_n[1])'
UVM_ERROR @ 6909.991667 us: (pwrmgr_rstmgr_sva_if.sv:44) [ASSERT FAILED] SysHandshakeOff_A
UVM_INFO @ 6909.991667 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 1 failures:
2.chip_sw_keymgr_sideload_aes.48718295881791518786553393662096727161227980565714709918789056694745120046381
Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest/run.log
UVM_FATAL @ 10010.360001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
3.chip_csr_aliasing.74315301028213988924952554615481425885900026810380394299303206690734203153519
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
Job ID: smart:f0821824-4dc9-4b04-8bd2-3e4cc31a97af
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
47.chip_sw_alert_handler_lpg_sleep_mode_alerts.95825453324986663196239041223169546071222230067594626199699901129106626973961
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3487.664994 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003718 MTVAL=40600800
UVM_INFO @ 3487.664994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---