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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.54 95.54 94.41 90.99 95.29 97.38 99.60


Total test records in report: 2779
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T45 /workspace/coverage/default/2.chip_jtag_mem_access.838703115 May 19 03:57:12 PM PDT 24 May 19 04:19:22 PM PDT 24 13191640175 ps
T197 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3877619237 May 19 03:45:10 PM PDT 24 May 19 04:18:37 PM PDT 24 7814362944 ps
T872 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1663125358 May 19 03:57:12 PM PDT 24 May 19 04:02:30 PM PDT 24 2808564028 ps
T873 /workspace/coverage/default/2.chip_sw_example_concurrency.3805653897 May 19 04:00:01 PM PDT 24 May 19 04:04:15 PM PDT 24 2916275856 ps
T95 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3529926688 May 19 03:57:30 PM PDT 24 May 19 04:36:12 PM PDT 24 25079492256 ps
T277 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1077432015 May 19 04:08:59 PM PDT 24 May 19 04:19:34 PM PDT 24 6397776804 ps
T874 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3403578486 May 19 04:10:13 PM PDT 24 May 19 05:04:21 PM PDT 24 14372210220 ps
T195 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3251099429 May 19 03:47:35 PM PDT 24 May 19 03:51:25 PM PDT 24 2915636800 ps
T875 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2676858975 May 19 04:04:10 PM PDT 24 May 19 05:15:12 PM PDT 24 15248535232 ps
T167 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.517598071 May 19 04:09:54 PM PDT 24 May 19 04:24:11 PM PDT 24 8140614200 ps
T876 /workspace/coverage/default/1.chip_sw_uart_smoketest.1250968501 May 19 03:58:23 PM PDT 24 May 19 04:03:55 PM PDT 24 3222994390 ps
T877 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3716469434 May 19 03:52:46 PM PDT 24 May 19 03:56:34 PM PDT 24 2961079590 ps
T217 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1334576567 May 19 03:44:52 PM PDT 24 May 19 04:51:09 PM PDT 24 11866296536 ps
T230 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1931347504 May 19 04:17:05 PM PDT 24 May 19 04:28:03 PM PDT 24 5707296200 ps
T878 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2716463977 May 19 03:51:08 PM PDT 24 May 19 04:35:36 PM PDT 24 34473753690 ps
T879 /workspace/coverage/default/1.chip_sw_otbn_randomness.2086772597 May 19 03:53:01 PM PDT 24 May 19 04:08:30 PM PDT 24 5633794136 ps
T46 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3600824506 May 19 04:07:13 PM PDT 24 May 19 04:17:06 PM PDT 24 5337772810 ps
T136 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3964001441 May 19 04:12:34 PM PDT 24 May 19 04:19:11 PM PDT 24 3242395640 ps
T648 /workspace/coverage/default/0.chip_sw_power_idle_load.2841839410 May 19 03:50:09 PM PDT 24 May 19 04:01:58 PM PDT 24 4448737670 ps
T96 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3780747682 May 19 03:48:13 PM PDT 24 May 19 04:24:16 PM PDT 24 25929952367 ps
T164 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1450529339 May 19 03:48:37 PM PDT 24 May 19 03:57:19 PM PDT 24 5576454512 ps
T679 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3726456441 May 19 04:11:09 PM PDT 24 May 19 04:21:16 PM PDT 24 5575177280 ps
T880 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2105842222 May 19 03:47:50 PM PDT 24 May 19 04:25:22 PM PDT 24 9000546456 ps
T881 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.562279802 May 19 04:00:58 PM PDT 24 May 19 04:23:46 PM PDT 24 10733071293 ps
T882 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.819310634 May 19 04:07:31 PM PDT 24 May 19 04:12:30 PM PDT 24 2884191696 ps
T51 /workspace/coverage/default/2.chip_jtag_csr_rw.476706831 May 19 03:57:17 PM PDT 24 May 19 04:30:03 PM PDT 24 20165721820 ps
T168 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2865886889 May 19 04:08:33 PM PDT 24 May 19 04:22:05 PM PDT 24 8000266700 ps
T387 /workspace/coverage/default/1.chip_sw_power_idle_load.4039511839 May 19 03:57:04 PM PDT 24 May 19 04:10:34 PM PDT 24 5097251212 ps
T388 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2651274237 May 19 03:47:24 PM PDT 24 May 19 04:43:31 PM PDT 24 25122868192 ps
T389 /workspace/coverage/default/2.chip_sw_example_flash.1224813563 May 19 03:58:27 PM PDT 24 May 19 04:02:03 PM PDT 24 2904149824 ps
T137 /workspace/coverage/default/57.chip_sw_all_escalation_resets.2941456364 May 19 04:14:19 PM PDT 24 May 19 04:28:01 PM PDT 24 5104730570 ps
T129 /workspace/coverage/default/1.chip_tap_straps_dev.1622515347 May 19 03:56:11 PM PDT 24 May 19 04:23:25 PM PDT 24 13894169440 ps
T77 /workspace/coverage/default/3.chip_tap_straps_dev.172458210 May 19 04:12:19 PM PDT 24 May 19 04:14:48 PM PDT 24 2844838910 ps
T390 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2719715219 May 19 04:00:43 PM PDT 24 May 19 04:04:06 PM PDT 24 3155679900 ps
T339 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1694396157 May 19 03:45:02 PM PDT 24 May 19 03:49:53 PM PDT 24 2956274027 ps
T719 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.598595283 May 19 04:16:34 PM PDT 24 May 19 04:23:17 PM PDT 24 3400525944 ps
T350 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3215489097 May 19 03:56:54 PM PDT 24 May 19 04:06:16 PM PDT 24 5143039624 ps
T53 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2967984877 May 19 03:57:02 PM PDT 24 May 19 04:22:27 PM PDT 24 22140927034 ps
T883 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2876649652 May 19 04:08:03 PM PDT 24 May 19 04:17:55 PM PDT 24 4523641830 ps
T83 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2861034792 May 19 04:03:24 PM PDT 24 May 19 04:25:04 PM PDT 24 9336037468 ps
T78 /workspace/coverage/default/3.chip_tap_straps_rma.2834632100 May 19 04:07:58 PM PDT 24 May 19 04:15:03 PM PDT 24 4743234877 ps
T884 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.673156742 May 19 03:56:11 PM PDT 24 May 19 04:08:51 PM PDT 24 4880137320 ps
T885 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.416175825 May 19 04:10:04 PM PDT 24 May 19 04:25:18 PM PDT 24 8004015398 ps
T886 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1232947016 May 19 04:07:27 PM PDT 24 May 19 04:12:40 PM PDT 24 3370802183 ps
T237 /workspace/coverage/default/0.chip_sw_power_sleep_load.2039419837 May 19 03:46:44 PM PDT 24 May 19 03:54:38 PM PDT 24 4692813022 ps
T887 /workspace/coverage/default/2.chip_sw_aes_idle.900449528 May 19 04:04:53 PM PDT 24 May 19 04:09:07 PM PDT 24 2461272894 ps
T138 /workspace/coverage/default/54.chip_sw_all_escalation_resets.639871546 May 19 04:19:58 PM PDT 24 May 19 04:27:33 PM PDT 24 4868677096 ps
T79 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.515239037 May 19 04:03:19 PM PDT 24 May 19 04:12:21 PM PDT 24 5021408420 ps
T625 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2251407199 May 19 04:16:25 PM PDT 24 May 19 04:23:24 PM PDT 24 3975455332 ps
T628 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2093186721 May 19 03:46:14 PM PDT 24 May 19 03:56:53 PM PDT 24 5379332675 ps
T623 /workspace/coverage/default/0.chip_sw_edn_boot_mode.4184514787 May 19 03:45:51 PM PDT 24 May 19 03:54:22 PM PDT 24 2967451060 ps
T627 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1628699738 May 19 03:52:44 PM PDT 24 May 19 05:01:51 PM PDT 24 17978199432 ps
T888 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2844865295 May 19 03:48:45 PM PDT 24 May 19 03:57:44 PM PDT 24 5358453984 ps
T889 /workspace/coverage/default/2.rom_e2e_smoke.455265628 May 19 04:11:35 PM PDT 24 May 19 04:59:36 PM PDT 24 14870488600 ps
T177 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3346334899 May 19 03:49:11 PM PDT 24 May 19 07:39:33 PM PDT 24 76995045033 ps
T264 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2449375176 May 19 03:53:49 PM PDT 24 May 19 04:01:55 PM PDT 24 9442945618 ps
T178 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1544223931 May 19 04:00:53 PM PDT 24 May 19 07:36:02 PM PDT 24 76666088421 ps
T890 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1247485971 May 19 03:45:47 PM PDT 24 May 19 03:54:09 PM PDT 24 5759171810 ps
T891 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1403637015 May 19 04:14:38 PM PDT 24 May 19 04:23:14 PM PDT 24 5303062568 ps
T316 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1739395435 May 19 04:00:22 PM PDT 24 May 19 04:12:09 PM PDT 24 4696946072 ps
T101 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1482631412 May 19 03:54:14 PM PDT 24 May 19 04:11:35 PM PDT 24 7776826278 ps
T892 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3253446555 May 19 03:53:35 PM PDT 24 May 19 03:57:50 PM PDT 24 2616271008 ps
T331 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.102326584 May 19 04:08:50 PM PDT 24 May 19 04:19:45 PM PDT 24 3961116456 ps
T893 /workspace/coverage/default/2.chip_sw_kmac_app_rom.792517223 May 19 04:03:12 PM PDT 24 May 19 04:07:18 PM PDT 24 3270905674 ps
T310 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2734751558 May 19 03:49:48 PM PDT 24 May 19 04:01:27 PM PDT 24 5237299146 ps
T267 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4124455171 May 19 03:51:57 PM PDT 24 May 19 04:07:22 PM PDT 24 5910161240 ps
T894 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2324022617 May 19 03:50:23 PM PDT 24 May 19 04:10:25 PM PDT 24 8884172648 ps
T147 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3354276905 May 19 03:56:42 PM PDT 24 May 19 04:23:51 PM PDT 24 19223027790 ps
T895 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1763437972 May 19 03:45:52 PM PDT 24 May 19 03:56:42 PM PDT 24 6035590920 ps
T682 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.384380717 May 19 04:14:40 PM PDT 24 May 19 04:22:51 PM PDT 24 4357997768 ps
T896 /workspace/coverage/default/1.chip_sw_rv_timer_irq.862656535 May 19 03:51:45 PM PDT 24 May 19 03:57:21 PM PDT 24 2950469760 ps
T897 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1692150149 May 19 04:08:04 PM PDT 24 May 19 04:19:11 PM PDT 24 4654831272 ps
T176 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3997228386 May 19 03:44:11 PM PDT 24 May 19 03:50:13 PM PDT 24 5964806395 ps
T317 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4145638006 May 19 03:46:40 PM PDT 24 May 19 04:01:56 PM PDT 24 5824203686 ps
T349 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.2687315903 May 19 03:50:29 PM PDT 24 May 19 06:57:47 PM PDT 24 63985127610 ps
T898 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2295155999 May 19 03:55:18 PM PDT 24 May 19 04:35:03 PM PDT 24 22385796735 ps
T84 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2782063032 May 19 04:03:17 PM PDT 24 May 19 04:08:34 PM PDT 24 3009351424 ps
T773 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2113560087 May 19 04:13:45 PM PDT 24 May 19 04:20:12 PM PDT 24 3412149368 ps
T220 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1173078765 May 19 03:46:25 PM PDT 24 May 19 04:04:18 PM PDT 24 7659529715 ps
T714 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3633678497 May 19 04:14:15 PM PDT 24 May 19 04:20:47 PM PDT 24 3983382764 ps
T126 /workspace/coverage/default/1.chip_tap_straps_rma.1104668533 May 19 03:55:45 PM PDT 24 May 19 04:10:49 PM PDT 24 7680991365 ps
T899 /workspace/coverage/default/1.chip_sw_aes_masking_off.3563520886 May 19 03:52:04 PM PDT 24 May 19 03:57:25 PM PDT 24 3051612911 ps
T900 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.617140205 May 19 04:07:49 PM PDT 24 May 19 04:12:12 PM PDT 24 2602944192 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2989581425 May 19 03:55:44 PM PDT 24 May 19 04:10:16 PM PDT 24 6831385002 ps
T311 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4066517052 May 19 03:50:51 PM PDT 24 May 19 04:01:44 PM PDT 24 4056342420 ps
T739 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1056272626 May 19 04:11:12 PM PDT 24 May 19 04:21:21 PM PDT 24 5078048128 ps
T901 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1834254184 May 19 04:10:57 PM PDT 24 May 19 05:01:57 PM PDT 24 15011025910 ps
T732 /workspace/coverage/default/13.chip_sw_all_escalation_resets.4138682241 May 19 04:13:16 PM PDT 24 May 19 04:23:18 PM PDT 24 6354804992 ps
T757 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.652243883 May 19 04:13:00 PM PDT 24 May 19 04:18:31 PM PDT 24 3983421728 ps
T242 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.517359976 May 19 03:45:03 PM PDT 24 May 19 03:50:42 PM PDT 24 3033253986 ps
T346 /workspace/coverage/default/2.chip_sival_flash_info_access.184578261 May 19 03:59:38 PM PDT 24 May 19 04:05:23 PM PDT 24 2464076816 ps
T34 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1059718263 May 19 03:50:34 PM PDT 24 May 19 03:57:07 PM PDT 24 5273416200 ps
T902 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2241493388 May 19 03:54:35 PM PDT 24 May 19 04:04:45 PM PDT 24 6642627864 ps
T903 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1795063790 May 19 03:52:33 PM PDT 24 May 19 03:59:58 PM PDT 24 4386656384 ps
T904 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3333452011 May 19 03:53:49 PM PDT 24 May 19 03:57:55 PM PDT 24 2919567666 ps
T684 /workspace/coverage/default/73.chip_sw_all_escalation_resets.50105830 May 19 04:17:39 PM PDT 24 May 19 04:27:30 PM PDT 24 4927636006 ps
T328 /workspace/coverage/default/2.chip_sw_pattgen_ios.1446043086 May 19 04:00:05 PM PDT 24 May 19 04:04:39 PM PDT 24 3411713038 ps
T704 /workspace/coverage/default/81.chip_sw_all_escalation_resets.1126239016 May 19 04:17:03 PM PDT 24 May 19 04:25:45 PM PDT 24 3955410952 ps
T905 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3207546804 May 19 04:11:09 PM PDT 24 May 19 05:02:33 PM PDT 24 14612835860 ps
T40 /workspace/coverage/default/0.rom_e2e_shutdown_output.114218241 May 19 03:53:09 PM PDT 24 May 19 04:42:38 PM PDT 24 30354204928 ps
T906 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1594213491 May 19 03:54:47 PM PDT 24 May 19 04:54:31 PM PDT 24 13946221942 ps
T907 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.289127115 May 19 03:55:09 PM PDT 24 May 19 04:17:50 PM PDT 24 11705449240 ps
T742 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1383251032 May 19 04:13:46 PM PDT 24 May 19 04:21:19 PM PDT 24 5209980468 ps
T908 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3927650116 May 19 03:42:53 PM PDT 24 May 19 03:50:37 PM PDT 24 4627548509 ps
T909 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1903478622 May 19 04:02:03 PM PDT 24 May 19 04:06:55 PM PDT 24 2727442084 ps
T910 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2621193152 May 19 03:45:44 PM PDT 24 May 19 03:52:10 PM PDT 24 3485245600 ps
T911 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3933978450 May 19 03:44:09 PM PDT 24 May 19 04:07:56 PM PDT 24 14030550113 ps
T758 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1669631327 May 19 04:16:30 PM PDT 24 May 19 04:26:17 PM PDT 24 4189707726 ps
T912 /workspace/coverage/default/1.chip_sw_kmac_entropy.152214960 May 19 03:49:40 PM PDT 24 May 19 03:55:07 PM PDT 24 2824545546 ps
T913 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2386187309 May 19 03:45:21 PM PDT 24 May 19 04:05:41 PM PDT 24 6019322394 ps
T729 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3577119036 May 19 04:12:17 PM PDT 24 May 19 04:19:32 PM PDT 24 4618732692 ps
T743 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1174662357 May 19 04:15:22 PM PDT 24 May 19 04:23:52 PM PDT 24 6338258622 ps
T763 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425706784 May 19 04:16:03 PM PDT 24 May 19 04:22:30 PM PDT 24 3953349240 ps
T336 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1294037788 May 19 03:45:15 PM PDT 24 May 19 03:48:33 PM PDT 24 3333877872 ps
T914 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1952669209 May 19 04:07:25 PM PDT 24 May 19 04:11:40 PM PDT 24 2624923604 ps
T915 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1692731385 May 19 04:11:16 PM PDT 24 May 19 04:36:26 PM PDT 24 8307843840 ps
T916 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2963777827 May 19 03:45:13 PM PDT 24 May 19 03:49:07 PM PDT 24 2569630008 ps
T917 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3308823401 May 19 03:56:06 PM PDT 24 May 19 04:10:22 PM PDT 24 9032585920 ps
T918 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1398968615 May 19 03:53:07 PM PDT 24 May 19 04:02:33 PM PDT 24 7918598372 ps
T744 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.778549111 May 19 04:13:52 PM PDT 24 May 19 04:18:45 PM PDT 24 3030373100 ps
T221 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3973514465 May 19 03:44:44 PM PDT 24 May 19 04:02:48 PM PDT 24 6165163760 ps
T365 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.913683194 May 19 03:53:39 PM PDT 24 May 19 05:23:33 PM PDT 24 22982184360 ps
T919 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2460130488 May 19 03:52:13 PM PDT 24 May 19 03:58:42 PM PDT 24 4629514740 ps
T8 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4124015573 May 19 03:43:24 PM PDT 24 May 19 03:48:46 PM PDT 24 2591120595 ps
T108 /workspace/coverage/default/2.chip_plic_all_irqs_10.3434762086 May 19 04:03:31 PM PDT 24 May 19 04:13:03 PM PDT 24 4199071798 ps
T194 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.196904433 May 19 03:52:01 PM PDT 24 May 19 04:04:27 PM PDT 24 6388727857 ps
T920 /workspace/coverage/default/2.chip_sw_aes_smoketest.975303930 May 19 04:05:48 PM PDT 24 May 19 04:09:26 PM PDT 24 3143106800 ps
T921 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3148681839 May 19 03:51:42 PM PDT 24 May 19 04:13:28 PM PDT 24 6850931432 ps
T710 /workspace/coverage/default/37.chip_sw_all_escalation_resets.277189148 May 19 04:12:52 PM PDT 24 May 19 04:21:03 PM PDT 24 5012129640 ps
T922 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3936393556 May 19 04:02:46 PM PDT 24 May 19 05:02:04 PM PDT 24 14737854990 ps
T923 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2574138680 May 19 04:09:26 PM PDT 24 May 19 04:21:03 PM PDT 24 4529880240 ps
T265 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1870199530 May 19 03:43:54 PM PDT 24 May 19 03:50:38 PM PDT 24 9689388036 ps
T924 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.623437472 May 19 03:45:39 PM PDT 24 May 19 03:50:05 PM PDT 24 2779689378 ps
T925 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3000624607 May 19 04:03:16 PM PDT 24 May 19 07:31:17 PM PDT 24 254918314360 ps
T766 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2336194121 May 19 04:13:17 PM PDT 24 May 19 04:23:40 PM PDT 24 4142872840 ps
T926 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2060246820 May 19 04:03:55 PM PDT 24 May 19 04:27:32 PM PDT 24 8764430680 ps
T927 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2358621412 May 19 03:50:22 PM PDT 24 May 19 04:09:42 PM PDT 24 6894249472 ps
T716 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1004522315 May 19 04:11:17 PM PDT 24 May 19 04:17:33 PM PDT 24 3509187672 ps
T928 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2211232456 May 19 04:06:35 PM PDT 24 May 19 04:11:26 PM PDT 24 2942090101 ps
T929 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2005822783 May 19 04:01:25 PM PDT 24 May 19 04:05:49 PM PDT 24 2661495227 ps
T57 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1104513830 May 19 03:43:48 PM PDT 24 May 19 03:49:20 PM PDT 24 3574231752 ps
T323 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3610444320 May 19 03:59:56 PM PDT 24 May 19 04:14:14 PM PDT 24 4279670904 ps
T930 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1197970944 May 19 04:00:47 PM PDT 24 May 19 04:55:41 PM PDT 24 14738488555 ps
T931 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1158030238 May 19 04:16:27 PM PDT 24 May 19 04:23:51 PM PDT 24 4145382528 ps
T244 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3157232041 May 19 03:50:37 PM PDT 24 May 19 04:04:06 PM PDT 24 7384333644 ps
T932 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2639840354 May 19 03:53:39 PM PDT 24 May 19 04:05:13 PM PDT 24 4796558592 ps
T120 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4144723351 May 19 04:04:10 PM PDT 24 May 19 04:17:23 PM PDT 24 4732042244 ps
T12 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2106772576 May 19 03:44:30 PM PDT 24 May 19 03:47:55 PM PDT 24 2901731408 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.421851604 May 19 03:45:00 PM PDT 24 May 19 03:49:59 PM PDT 24 2992796644 ps
T933 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3587703634 May 19 04:09:18 PM PDT 24 May 19 04:50:52 PM PDT 24 12765651221 ps
T934 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2183528988 May 19 03:59:22 PM PDT 24 May 19 04:02:44 PM PDT 24 1903463242 ps
T730 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.916686069 May 19 04:13:57 PM PDT 24 May 19 04:20:55 PM PDT 24 4567009112 ps
T935 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2866966991 May 19 03:45:22 PM PDT 24 May 19 03:48:52 PM PDT 24 2173698052 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1882513969 May 19 04:05:10 PM PDT 24 May 19 04:54:10 PM PDT 24 10408624500 ps
T224 /workspace/coverage/default/0.chip_sw_flash_init.1856973963 May 19 03:44:01 PM PDT 24 May 19 04:28:01 PM PDT 24 24629705050 ps
T936 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.297254105 May 19 03:57:01 PM PDT 24 May 19 04:22:08 PM PDT 24 8704328903 ps
T937 /workspace/coverage/default/0.chip_sw_example_rom.1921930623 May 19 03:41:45 PM PDT 24 May 19 03:43:29 PM PDT 24 2536605940 ps
T938 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3789965135 May 19 04:00:17 PM PDT 24 May 19 04:26:46 PM PDT 24 7976674700 ps
T483 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3128591940 May 19 03:52:21 PM PDT 24 May 19 04:06:22 PM PDT 24 4898032472 ps
T259 /workspace/coverage/default/1.chip_jtag_mem_access.1634552475 May 19 03:48:07 PM PDT 24 May 19 04:13:38 PM PDT 24 13973913222 ps
T939 /workspace/coverage/default/0.rom_e2e_smoke.3621016705 May 19 03:51:13 PM PDT 24 May 19 04:51:25 PM PDT 24 14401252506 ps
T68 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1926746525 May 19 03:45:52 PM PDT 24 May 19 03:55:55 PM PDT 24 5221459506 ps
T707 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3680159592 May 19 04:10:01 PM PDT 24 May 19 04:19:19 PM PDT 24 4950834664 ps
T148 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2554820630 May 19 03:46:05 PM PDT 24 May 19 03:52:06 PM PDT 24 7546685820 ps
T343 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3595165851 May 19 04:02:10 PM PDT 24 May 19 04:13:23 PM PDT 24 19389506008 ps
T940 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1622894687 May 19 04:05:12 PM PDT 24 May 19 04:08:36 PM PDT 24 3404527064 ps
T941 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3565765374 May 19 03:56:52 PM PDT 24 May 19 04:01:09 PM PDT 24 3334256144 ps
T73 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4019355577 May 19 03:56:14 PM PDT 24 May 19 04:03:21 PM PDT 24 5115531304 ps
T735 /workspace/coverage/default/95.chip_sw_all_escalation_resets.1496791933 May 19 04:17:29 PM PDT 24 May 19 04:28:26 PM PDT 24 4474686392 ps
T942 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3830450677 May 19 03:44:34 PM PDT 24 May 19 03:53:46 PM PDT 24 5187699996 ps
T943 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4192180396 May 19 03:46:58 PM PDT 24 May 19 03:58:57 PM PDT 24 4148390664 ps
T733 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3958439829 May 19 04:13:32 PM PDT 24 May 19 04:20:13 PM PDT 24 3872763980 ps
T944 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3542161229 May 19 03:50:28 PM PDT 24 May 19 03:54:45 PM PDT 24 3389975260 ps
T945 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2823677193 May 19 04:00:19 PM PDT 24 May 19 04:10:47 PM PDT 24 4370158047 ps
T35 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3537422394 May 19 03:46:23 PM PDT 24 May 19 03:53:24 PM PDT 24 5267664598 ps
T946 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1505649696 May 19 04:11:53 PM PDT 24 May 19 05:02:55 PM PDT 24 14275699714 ps
T681 /workspace/coverage/default/1.chip_sw_all_escalation_resets.2224076540 May 19 03:47:30 PM PDT 24 May 19 03:59:15 PM PDT 24 5364548240 ps
T947 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2915959108 May 19 04:02:18 PM PDT 24 May 19 04:26:23 PM PDT 24 6807357010 ps
T127 /workspace/coverage/default/4.chip_tap_straps_rma.1164343496 May 19 04:08:58 PM PDT 24 May 19 04:21:16 PM PDT 24 7175408880 ps
T685 /workspace/coverage/default/94.chip_sw_all_escalation_resets.961285586 May 19 04:17:15 PM PDT 24 May 19 04:26:36 PM PDT 24 5803867148 ps
T948 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2052486154 May 19 04:07:09 PM PDT 24 May 19 04:10:50 PM PDT 24 2721539838 ps
T949 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.195526263 May 19 04:09:53 PM PDT 24 May 19 04:14:56 PM PDT 24 2690936608 ps
T950 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1742653635 May 19 04:11:22 PM PDT 24 May 19 04:50:50 PM PDT 24 12990176476 ps
T951 /workspace/coverage/default/2.chip_sw_otbn_randomness.2587889898 May 19 04:02:08 PM PDT 24 May 19 04:17:37 PM PDT 24 5392047380 ps
T952 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4137548813 May 19 03:52:43 PM PDT 24 May 19 04:40:08 PM PDT 24 19292975488 ps
T74 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2623548605 May 19 04:11:30 PM PDT 24 May 19 04:21:26 PM PDT 24 4458120698 ps
T953 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3517576642 May 19 03:46:33 PM PDT 24 May 19 03:58:15 PM PDT 24 4081689188 ps
T954 /workspace/coverage/default/41.chip_sw_all_escalation_resets.2030839021 May 19 04:13:13 PM PDT 24 May 19 04:27:51 PM PDT 24 6100844212 ps
T368 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3740401797 May 19 03:47:31 PM PDT 24 May 19 03:50:09 PM PDT 24 1698269940 ps
T693 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2997478375 May 19 04:20:23 PM PDT 24 May 19 04:26:16 PM PDT 24 4110103896 ps
T338 /workspace/coverage/default/0.chip_sival_flash_info_access.2912008711 May 19 03:43:38 PM PDT 24 May 19 03:48:09 PM PDT 24 3262265632 ps
T955 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1235559864 May 19 03:53:38 PM PDT 24 May 19 04:43:50 PM PDT 24 11252600459 ps
T956 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3081478159 May 19 03:43:46 PM PDT 24 May 19 03:50:09 PM PDT 24 3489780036 ps
T957 /workspace/coverage/default/2.chip_sw_csrng_kat_test.2280865994 May 19 04:04:23 PM PDT 24 May 19 04:07:46 PM PDT 24 2833601608 ps
T958 /workspace/coverage/default/2.chip_sw_example_rom.3625444224 May 19 03:57:48 PM PDT 24 May 19 03:59:36 PM PDT 24 1974490312 ps
T658 /workspace/coverage/default/2.chip_sw_plic_sw_irq.471067560 May 19 04:03:37 PM PDT 24 May 19 04:08:46 PM PDT 24 3009455860 ps
T959 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.605978496 May 19 03:44:16 PM PDT 24 May 19 04:28:34 PM PDT 24 12705202312 ps
T960 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1087092567 May 19 03:46:24 PM PDT 24 May 19 03:53:20 PM PDT 24 6544558424 ps
T711 /workspace/coverage/default/42.chip_sw_all_escalation_resets.1768687987 May 19 04:13:06 PM PDT 24 May 19 04:19:47 PM PDT 24 4479094080 ps
T961 /workspace/coverage/default/1.chip_sw_kmac_idle.552197220 May 19 03:57:25 PM PDT 24 May 19 04:01:47 PM PDT 24 3432395000 ps
T340 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3076222821 May 19 03:53:17 PM PDT 24 May 19 03:56:48 PM PDT 24 2882880324 ps
T962 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2061924462 May 19 03:43:59 PM PDT 24 May 19 03:48:18 PM PDT 24 2998856538 ps
T720 /workspace/coverage/default/99.chip_sw_all_escalation_resets.402094311 May 19 04:17:23 PM PDT 24 May 19 04:29:44 PM PDT 24 5355592160 ps
T963 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3469228515 May 19 03:48:28 PM PDT 24 May 19 03:59:08 PM PDT 24 7340985628 ps
T964 /workspace/coverage/default/0.chip_sw_example_manufacturer.2722312890 May 19 03:43:14 PM PDT 24 May 19 03:47:41 PM PDT 24 2740838356 ps
T965 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3450984224 May 19 03:56:19 PM PDT 24 May 19 04:03:57 PM PDT 24 5220061848 ps
T966 /workspace/coverage/default/14.chip_sw_all_escalation_resets.572326106 May 19 04:11:01 PM PDT 24 May 19 04:21:08 PM PDT 24 5003897242 ps
T324 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3730170527 May 19 03:50:56 PM PDT 24 May 19 04:03:57 PM PDT 24 4903070196 ps
T725 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543632575 May 19 04:16:47 PM PDT 24 May 19 04:24:07 PM PDT 24 3782090304 ps
T967 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3612581915 May 19 04:10:20 PM PDT 24 May 19 04:21:48 PM PDT 24 4473437116 ps
T41 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2332704019 May 19 04:02:54 PM PDT 24 May 19 04:50:00 PM PDT 24 14019206762 ps
T38 /workspace/coverage/default/2.chip_sw_spi_device_tpm.3147543514 May 19 04:00:50 PM PDT 24 May 19 04:07:18 PM PDT 24 3418526151 ps
T968 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.686707901 May 19 04:10:14 PM PDT 24 May 19 04:18:00 PM PDT 24 5739804524 ps
T969 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1072910591 May 19 04:01:46 PM PDT 24 May 19 04:12:14 PM PDT 24 5098009226 ps
T970 /workspace/coverage/default/2.chip_sw_edn_kat.1267280694 May 19 04:04:15 PM PDT 24 May 19 04:14:15 PM PDT 24 3052737656 ps
T971 /workspace/coverage/default/2.rom_e2e_asm_init_dev.15838502 May 19 04:11:58 PM PDT 24 May 19 05:05:48 PM PDT 24 14475118534 ps
T972 /workspace/coverage/default/2.chip_sw_csrng_smoketest.224678379 May 19 04:08:05 PM PDT 24 May 19 04:12:38 PM PDT 24 2492308176 ps
T973 /workspace/coverage/default/0.chip_sw_uart_smoketest.2597452645 May 19 03:53:53 PM PDT 24 May 19 03:59:03 PM PDT 24 3503414730 ps
T130 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1707834461 May 19 03:42:56 PM PDT 24 May 19 03:48:48 PM PDT 24 3128550268 ps
T326 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1821889144 May 19 03:57:23 PM PDT 24 May 19 04:08:40 PM PDT 24 4266028550 ps
T974 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3143047131 May 19 03:55:39 PM PDT 24 May 19 04:03:43 PM PDT 24 5549239480 ps
T975 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2065293060 May 19 04:09:34 PM PDT 24 May 19 04:18:26 PM PDT 24 5188178242 ps
T260 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.164535424 May 19 04:12:20 PM PDT 24 May 19 05:08:51 PM PDT 24 13975901612 ps
T976 /workspace/coverage/default/0.chip_tap_straps_dev.612041834 May 19 03:44:19 PM PDT 24 May 19 04:10:34 PM PDT 24 13892292693 ps
T325 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2680384712 May 19 03:43:27 PM PDT 24 May 19 03:55:01 PM PDT 24 4071610952 ps
T977 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2874846534 May 19 04:01:14 PM PDT 24 May 19 04:07:20 PM PDT 24 3118873530 ps
T754 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371440095 May 19 04:11:47 PM PDT 24 May 19 04:18:53 PM PDT 24 4230891288 ps
T702 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1152212626 May 19 04:13:03 PM PDT 24 May 19 04:19:24 PM PDT 24 4030964070 ps
T298 /workspace/coverage/default/12.chip_sw_all_escalation_resets.2631078627 May 19 04:10:58 PM PDT 24 May 19 04:20:43 PM PDT 24 5162406456 ps
T978 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2729605832 May 19 03:51:42 PM PDT 24 May 19 04:09:14 PM PDT 24 6936184676 ps
T979 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2288008778 May 19 03:46:03 PM PDT 24 May 19 03:55:10 PM PDT 24 4685180384 ps
T768 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.142504671 May 19 04:16:10 PM PDT 24 May 19 04:23:31 PM PDT 24 4067776728 ps
T980 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3278025141 May 19 03:45:27 PM PDT 24 May 19 03:56:08 PM PDT 24 4288201632 ps
T981 /workspace/coverage/default/2.chip_sw_aes_enc.1002213913 May 19 04:02:37 PM PDT 24 May 19 04:06:11 PM PDT 24 2723437610 ps
T982 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.33653590 May 19 03:58:20 PM PDT 24 May 19 04:05:05 PM PDT 24 3547124104 ps
T717 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2761730707 May 19 04:14:50 PM PDT 24 May 19 04:21:49 PM PDT 24 3330234940 ps
T983 /workspace/coverage/default/1.chip_sw_aes_entropy.3032336614 May 19 03:51:39 PM PDT 24 May 19 03:55:54 PM PDT 24 3074615336 ps
T984 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3373960950 May 19 03:58:11 PM PDT 24 May 19 04:02:13 PM PDT 24 3238726152 ps
T198 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.948068008 May 19 03:49:36 PM PDT 24 May 19 03:59:25 PM PDT 24 3975399670 ps
T985 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2998846733 May 19 03:51:06 PM PDT 24 May 19 04:21:02 PM PDT 24 13159141674 ps
T986 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3395359055 May 19 04:03:16 PM PDT 24 May 19 05:01:22 PM PDT 24 18700842075 ps
T700 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3139482115 May 19 04:16:36 PM PDT 24 May 19 04:24:21 PM PDT 24 3693119384 ps
T987 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.438201703 May 19 03:52:50 PM PDT 24 May 19 04:50:51 PM PDT 24 13974278758 ps
T988 /workspace/coverage/default/2.chip_tap_straps_prod.2732953231 May 19 04:04:57 PM PDT 24 May 19 04:07:32 PM PDT 24 2572222821 ps
T199 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.384989873 May 19 03:43:13 PM PDT 24 May 19 03:59:31 PM PDT 24 7878939130 ps
T989 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2444660878 May 19 03:45:52 PM PDT 24 May 19 04:06:12 PM PDT 24 5410354344 ps
T990 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3713283798 May 19 03:48:00 PM PDT 24 May 19 03:54:51 PM PDT 24 4794428500 ps
T991 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3000267034 May 19 04:16:53 PM PDT 24 May 19 04:27:14 PM PDT 24 4526788570 ps
T992 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.859826887 May 19 04:03:49 PM PDT 24 May 19 04:13:00 PM PDT 24 3591589280 ps
T644 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1018328345 May 19 04:12:13 PM PDT 24 May 19 04:20:51 PM PDT 24 4155379876 ps
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