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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.54 95.54 94.41 90.99 95.29 97.38 99.60


Total test records in report: 2779
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T993 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3360990535 May 19 03:53:11 PM PDT 24 May 19 04:17:53 PM PDT 24 7324835400 ps
T994 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.340335413 May 19 03:46:22 PM PDT 24 May 19 04:04:32 PM PDT 24 8795541198 ps
T995 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1543559551 May 19 04:10:50 PM PDT 24 May 19 04:32:26 PM PDT 24 8374979496 ps
T314 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3467367614 May 19 03:42:55 PM PDT 24 May 19 03:52:14 PM PDT 24 3710564736 ps
T996 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2461739392 May 19 03:54:51 PM PDT 24 May 19 04:02:49 PM PDT 24 5128347824 ps
T997 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3876054284 May 19 04:03:33 PM PDT 24 May 19 04:10:43 PM PDT 24 3426822980 ps
T998 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4060491029 May 19 04:07:33 PM PDT 24 May 19 04:33:55 PM PDT 24 8482165950 ps
T999 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4038078069 May 19 03:51:06 PM PDT 24 May 19 03:56:42 PM PDT 24 4131834622 ps
T1000 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1565978867 May 19 03:55:54 PM PDT 24 May 19 04:04:56 PM PDT 24 4143507852 ps
T341 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3500995216 May 19 03:57:26 PM PDT 24 May 19 04:01:51 PM PDT 24 2831637199 ps
T1001 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3119769595 May 19 03:51:09 PM PDT 24 May 19 04:03:59 PM PDT 24 6846207330 ps
T1002 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3661198052 May 19 04:08:22 PM PDT 24 May 19 04:16:47 PM PDT 24 6893662914 ps
T1003 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.503809511 May 19 03:51:38 PM PDT 24 May 19 03:59:16 PM PDT 24 5072515626 ps
T1004 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282783194 May 19 04:13:33 PM PDT 24 May 19 04:20:10 PM PDT 24 3731188624 ps
T709 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.85655764 May 19 03:44:50 PM PDT 24 May 19 03:53:04 PM PDT 24 3337178496 ps
T1005 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3614186729 May 19 03:49:04 PM PDT 24 May 19 03:54:14 PM PDT 24 4423609588 ps
T1006 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3374354344 May 19 03:46:12 PM PDT 24 May 19 04:01:55 PM PDT 24 5486270800 ps
T1007 /workspace/coverage/default/2.chip_sw_hmac_enc.576704025 May 19 04:03:24 PM PDT 24 May 19 04:07:38 PM PDT 24 2818914000 ps
T1008 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3347722981 May 19 03:49:18 PM PDT 24 May 19 04:10:58 PM PDT 24 6361960760 ps
T1009 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.345719762 May 19 04:01:55 PM PDT 24 May 19 04:32:50 PM PDT 24 22623851979 ps
T52 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.332279139 May 19 04:11:57 PM PDT 24 May 19 04:18:18 PM PDT 24 3472768890 ps
T288 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4084236191 May 19 04:04:23 PM PDT 24 May 19 04:09:02 PM PDT 24 3310707171 ps
T703 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3280580703 May 19 04:15:10 PM PDT 24 May 19 04:20:45 PM PDT 24 3582316880 ps
T1010 /workspace/coverage/default/0.chip_tap_straps_prod.3645098523 May 19 03:45:01 PM PDT 24 May 19 04:16:25 PM PDT 24 16170411126 ps
T278 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4275209495 May 19 04:04:16 PM PDT 24 May 19 04:12:26 PM PDT 24 3386957288 ps
T1011 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1022430694 May 19 04:09:31 PM PDT 24 May 19 04:20:20 PM PDT 24 4075879976 ps
T626 /workspace/coverage/default/2.chip_sw_edn_boot_mode.602513868 May 19 04:04:09 PM PDT 24 May 19 04:13:02 PM PDT 24 3101975352 ps
T747 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.4240646314 May 19 04:15:07 PM PDT 24 May 19 04:22:31 PM PDT 24 3152060012 ps
T1012 /workspace/coverage/default/0.chip_sw_aes_entropy.1956021224 May 19 03:45:59 PM PDT 24 May 19 03:49:20 PM PDT 24 2689164680 ps
T1013 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.993478980 May 19 03:45:15 PM PDT 24 May 19 04:18:52 PM PDT 24 25568806372 ps
T1014 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2200408953 May 19 03:50:10 PM PDT 24 May 19 03:55:00 PM PDT 24 2825640500 ps
T1015 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3789594547 May 19 03:53:02 PM PDT 24 May 19 04:46:23 PM PDT 24 14145356508 ps
T1016 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1075887415 May 19 03:47:57 PM PDT 24 May 19 03:52:20 PM PDT 24 2974520738 ps
T1017 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2518582177 May 19 03:53:26 PM PDT 24 May 19 04:21:07 PM PDT 24 6738822136 ps
T723 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3576840382 May 19 04:18:00 PM PDT 24 May 19 04:29:16 PM PDT 24 5956175636 ps
T759 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1849631986 May 19 04:13:03 PM PDT 24 May 19 04:23:53 PM PDT 24 5885832506 ps
T305 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1135406206 May 19 03:42:52 PM PDT 24 May 19 04:12:16 PM PDT 24 14648091734 ps
T734 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.918584147 May 19 04:13:43 PM PDT 24 May 19 04:21:32 PM PDT 24 3774276080 ps
T751 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1081619740 May 19 04:17:37 PM PDT 24 May 19 04:22:07 PM PDT 24 3800278492 ps
T1018 /workspace/coverage/default/0.chip_sw_csrng_kat_test.430981547 May 19 03:45:34 PM PDT 24 May 19 03:50:12 PM PDT 24 2741093844 ps
T1019 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1652936231 May 19 03:44:46 PM PDT 24 May 19 04:01:48 PM PDT 24 10999913991 ps
T1020 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2636308557 May 19 04:00:04 PM PDT 24 May 19 04:05:14 PM PDT 24 2966792728 ps
T279 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.476746726 May 19 03:48:46 PM PDT 24 May 19 03:57:33 PM PDT 24 3950444011 ps
T22 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1612557646 May 19 03:51:57 PM PDT 24 May 19 04:42:36 PM PDT 24 21026272173 ps
T280 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3822291147 May 19 04:04:21 PM PDT 24 May 19 04:17:10 PM PDT 24 5665528860 ps
T621 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2724173163 May 19 03:47:10 PM PDT 24 May 19 04:04:55 PM PDT 24 4840866800 ps
T1021 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3462219613 May 19 03:53:07 PM PDT 24 May 19 04:01:54 PM PDT 24 19476679368 ps
T1022 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1804069261 May 19 03:46:18 PM PDT 24 May 19 03:55:44 PM PDT 24 4058026551 ps
T245 /workspace/coverage/default/87.chip_sw_all_escalation_resets.447001692 May 19 04:18:39 PM PDT 24 May 19 04:28:32 PM PDT 24 4994675540 ps
T1023 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2679396485 May 19 03:57:10 PM PDT 24 May 19 04:55:15 PM PDT 24 14224002856 ps
T745 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1070543146 May 19 04:13:37 PM PDT 24 May 19 04:21:17 PM PDT 24 3622821176 ps
T1024 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4079374736 May 19 03:44:35 PM PDT 24 May 19 03:52:11 PM PDT 24 5262564192 ps
T1025 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3266859467 May 19 03:51:40 PM PDT 24 May 19 04:03:02 PM PDT 24 9431160808 ps
T318 /workspace/coverage/default/2.chip_plic_all_irqs_0.101672659 May 19 04:04:30 PM PDT 24 May 19 04:26:53 PM PDT 24 5812416534 ps
T1026 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2627110958 May 19 03:43:16 PM PDT 24 May 19 04:04:10 PM PDT 24 6549880776 ps
T1027 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1333003792 May 19 03:49:30 PM PDT 24 May 19 03:53:26 PM PDT 24 2862683300 ps
T1028 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4272029488 May 19 04:09:32 PM PDT 24 May 19 04:20:12 PM PDT 24 4450180590 ps
T629 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.171808568 May 19 03:59:21 PM PDT 24 May 19 04:11:23 PM PDT 24 5518937754 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2934789754 May 19 03:44:43 PM PDT 24 May 19 04:19:12 PM PDT 24 7914901296 ps
T1029 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3575862913 May 19 04:11:06 PM PDT 24 May 19 04:38:48 PM PDT 24 8865024916 ps
T1030 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.4155943039 May 19 03:52:04 PM PDT 24 May 19 04:03:32 PM PDT 24 4950083239 ps
T1031 /workspace/coverage/default/11.chip_sw_all_escalation_resets.2123585297 May 19 04:13:24 PM PDT 24 May 19 04:22:23 PM PDT 24 5468769510 ps
T1032 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3442619417 May 19 03:45:37 PM PDT 24 May 19 04:27:12 PM PDT 24 39249443052 ps
T1033 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.4158437553 May 19 04:00:44 PM PDT 24 May 19 04:06:54 PM PDT 24 2641150472 ps
T139 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2352172865 May 19 04:09:24 PM PDT 24 May 19 04:14:55 PM PDT 24 3708183982 ps
T774 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2221524245 May 19 04:13:59 PM PDT 24 May 19 04:20:27 PM PDT 24 4408093224 ps
T1034 /workspace/coverage/default/0.rom_e2e_asm_init_dev.639298251 May 19 03:51:09 PM PDT 24 May 19 04:48:20 PM PDT 24 14324113990 ps
T749 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2544265892 May 19 04:17:05 PM PDT 24 May 19 04:23:00 PM PDT 24 3967589680 ps
T1035 /workspace/coverage/default/2.chip_sw_aes_entropy.1620235099 May 19 04:03:15 PM PDT 24 May 19 04:07:12 PM PDT 24 3396606676 ps
T1036 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1901869221 May 19 04:03:33 PM PDT 24 May 19 04:09:22 PM PDT 24 3189874400 ps
T1037 /workspace/coverage/default/1.chip_sw_example_flash.3037698656 May 19 03:50:56 PM PDT 24 May 19 03:54:50 PM PDT 24 2688686048 ps
T1038 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.12780284 May 19 03:50:26 PM PDT 24 May 19 03:53:53 PM PDT 24 2186684638 ps
T1039 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3024699866 May 19 04:07:52 PM PDT 24 May 19 04:11:40 PM PDT 24 2875989140 ps
T1040 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.280678973 May 19 03:50:28 PM PDT 24 May 19 03:57:21 PM PDT 24 3474115708 ps
T1041 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4178306000 May 19 04:01:33 PM PDT 24 May 19 04:14:16 PM PDT 24 4895649476 ps
T1042 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1442165716 May 19 03:44:43 PM PDT 24 May 19 04:40:28 PM PDT 24 17012406664 ps
T770 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3910198129 May 19 04:15:34 PM PDT 24 May 19 04:22:20 PM PDT 24 4199773850 ps
T1043 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1274843063 May 19 03:56:07 PM PDT 24 May 19 04:04:31 PM PDT 24 3713651552 ps
T645 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2926467356 May 19 04:16:16 PM PDT 24 May 19 04:25:15 PM PDT 24 5126192992 ps
T1044 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3218551120 May 19 04:07:19 PM PDT 24 May 19 04:26:36 PM PDT 24 8164960035 ps
T656 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1909295531 May 19 03:51:39 PM PDT 24 May 19 03:57:33 PM PDT 24 2883326772 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3266047803 May 19 03:44:22 PM PDT 24 May 19 03:53:56 PM PDT 24 3426601640 ps
T1045 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.664438204 May 19 04:03:51 PM PDT 24 May 19 04:08:41 PM PDT 24 2752793528 ps
T351 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1636418378 May 19 04:04:54 PM PDT 24 May 19 04:15:16 PM PDT 24 5203503416 ps
T1046 /workspace/coverage/default/4.chip_tap_straps_dev.4028454202 May 19 04:08:13 PM PDT 24 May 19 04:10:14 PM PDT 24 2687249810 ps
T9 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1964359013 May 19 03:48:34 PM PDT 24 May 19 03:52:26 PM PDT 24 2560800947 ps
T281 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3162761036 May 19 04:06:28 PM PDT 24 May 19 04:17:16 PM PDT 24 5089110838 ps
T60 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2025787918 May 19 03:46:37 PM PDT 24 May 19 04:12:01 PM PDT 24 21156032700 ps
T1047 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.576098977 May 19 03:54:23 PM PDT 24 May 19 04:02:00 PM PDT 24 4237933430 ps
T1048 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1777130138 May 19 04:02:26 PM PDT 24 May 19 04:10:40 PM PDT 24 4110272048 ps
T1049 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.4286110456 May 19 03:57:04 PM PDT 24 May 19 04:53:06 PM PDT 24 14071660490 ps
T1050 /workspace/coverage/default/0.chip_sw_aes_masking_off.3003186129 May 19 03:44:38 PM PDT 24 May 19 03:50:43 PM PDT 24 2552214924 ps
T131 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.390916801 May 19 03:42:55 PM PDT 24 May 19 05:42:51 PM PDT 24 31730420424 ps
T713 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526330842 May 19 04:13:48 PM PDT 24 May 19 04:20:44 PM PDT 24 4200692428 ps
T327 /workspace/coverage/default/0.chip_plic_all_irqs_20.125756913 May 19 03:46:02 PM PDT 24 May 19 03:57:05 PM PDT 24 4526150408 ps
T1051 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1529680261 May 19 03:46:52 PM PDT 24 May 19 04:02:51 PM PDT 24 7512509658 ps
T1052 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2796045531 May 19 03:43:46 PM PDT 24 May 19 07:30:43 PM PDT 24 75876059520 ps
T1053 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.885761145 May 19 03:58:36 PM PDT 24 May 19 04:24:08 PM PDT 24 8232760868 ps
T261 /workspace/coverage/default/1.rom_e2e_shutdown_output.514302596 May 19 04:02:42 PM PDT 24 May 19 04:50:24 PM PDT 24 22906287075 ps
T1054 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1929368765 May 19 03:46:22 PM PDT 24 May 19 05:00:40 PM PDT 24 18339257244 ps
T738 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3617133888 May 19 04:13:32 PM PDT 24 May 19 04:19:38 PM PDT 24 3612014000 ps
T1055 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1413834215 May 19 04:05:52 PM PDT 24 May 19 04:16:14 PM PDT 24 4802532638 ps
T1056 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.652172374 May 19 03:58:24 PM PDT 24 May 19 04:10:31 PM PDT 24 4884052976 ps
T769 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1748583307 May 19 04:14:13 PM PDT 24 May 19 04:20:57 PM PDT 24 3606947846 ps
T337 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1905971999 May 19 03:54:17 PM PDT 24 May 19 03:58:57 PM PDT 24 2813629918 ps
T1057 /workspace/coverage/default/3.chip_tap_straps_prod.458563182 May 19 04:08:12 PM PDT 24 May 19 04:27:01 PM PDT 24 11590939240 ps
T746 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238698608 May 19 04:15:37 PM PDT 24 May 19 04:20:11 PM PDT 24 3423120896 ps
T697 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446742016 May 19 04:16:41 PM PDT 24 May 19 04:21:55 PM PDT 24 3538817332 ps
T1058 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3003194793 May 19 03:55:27 PM PDT 24 May 19 04:10:14 PM PDT 24 7348736572 ps
T1059 /workspace/coverage/default/4.chip_tap_straps_prod.3199134247 May 19 04:08:46 PM PDT 24 May 19 04:25:32 PM PDT 24 10792260595 ps
T1060 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3158356879 May 19 03:45:14 PM PDT 24 May 19 03:50:31 PM PDT 24 3757581885 ps
T205 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1817951026 May 19 04:00:14 PM PDT 24 May 19 04:11:02 PM PDT 24 5599548872 ps
T289 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2536450162 May 19 03:59:53 PM PDT 24 May 19 04:03:35 PM PDT 24 2449383512 ps
T366 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.833757435 May 19 03:53:41 PM PDT 24 May 19 05:21:05 PM PDT 24 22201572960 ps
T1061 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2175112855 May 19 03:50:22 PM PDT 24 May 19 03:57:38 PM PDT 24 7278373870 ps
T348 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.9345456 May 19 04:05:50 PM PDT 24 May 19 04:09:40 PM PDT 24 3235744851 ps
T715 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1141078760 May 19 04:15:46 PM PDT 24 May 19 04:21:43 PM PDT 24 3995307292 ps
T1062 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2789029223 May 19 04:09:31 PM PDT 24 May 19 04:34:53 PM PDT 24 8105788290 ps
T1063 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2021928237 May 19 04:09:32 PM PDT 24 May 19 04:20:49 PM PDT 24 4607559400 ps
T740 /workspace/coverage/default/90.chip_sw_all_escalation_resets.25169994 May 19 04:17:48 PM PDT 24 May 19 04:26:00 PM PDT 24 4557978808 ps
T200 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3628212064 May 19 03:46:27 PM PDT 24 May 19 03:56:20 PM PDT 24 4740357627 ps
T1064 /workspace/coverage/default/0.chip_sw_edn_sw_mode.3155270531 May 19 03:45:26 PM PDT 24 May 19 04:10:58 PM PDT 24 7247509160 ps
T1065 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1947413287 May 19 03:44:51 PM PDT 24 May 19 03:55:50 PM PDT 24 6993750136 ps
T1066 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3815783444 May 19 03:48:52 PM PDT 24 May 19 03:53:39 PM PDT 24 2024311490 ps
T1067 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2885330108 May 19 04:02:29 PM PDT 24 May 19 04:07:14 PM PDT 24 2667082400 ps
T1068 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1852978845 May 19 04:07:38 PM PDT 24 May 19 04:14:01 PM PDT 24 5327760976 ps
T123 /workspace/coverage/default/1.chip_sw_alert_test.2484091128 May 19 03:55:08 PM PDT 24 May 19 04:00:54 PM PDT 24 2916482500 ps
T121 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2877428695 May 19 03:54:09 PM PDT 24 May 19 04:03:21 PM PDT 24 3546281716 ps
T1069 /workspace/coverage/default/0.chip_sw_example_flash.1623724801 May 19 03:44:10 PM PDT 24 May 19 03:47:51 PM PDT 24 2976766120 ps
T1070 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2902224301 May 19 03:51:36 PM PDT 24 May 19 03:55:42 PM PDT 24 2563581752 ps
T1071 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2090869529 May 19 04:01:51 PM PDT 24 May 19 04:13:31 PM PDT 24 5822586044 ps
T1072 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4183125215 May 19 04:09:23 PM PDT 24 May 19 04:17:58 PM PDT 24 3769317676 ps
T140 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2117110556 May 19 04:14:20 PM PDT 24 May 19 04:26:33 PM PDT 24 6034082576 ps
T1073 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.451169203 May 19 03:42:06 PM PDT 24 May 19 04:03:32 PM PDT 24 8335740578 ps
T1074 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2369069894 May 19 03:46:46 PM PDT 24 May 19 03:50:49 PM PDT 24 2969420074 ps
T69 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.191734395 May 19 04:03:47 PM PDT 24 May 19 04:15:52 PM PDT 24 5390979456 ps
T1075 /workspace/coverage/default/1.chip_sw_aes_idle.3653468208 May 19 03:53:05 PM PDT 24 May 19 03:58:14 PM PDT 24 3223911966 ps
T1076 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2884606646 May 19 04:11:45 PM PDT 24 May 19 04:49:42 PM PDT 24 10588779261 ps
T1077 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1846320178 May 19 03:58:50 PM PDT 24 May 19 04:09:22 PM PDT 24 3519214200 ps
T1078 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1925838330 May 19 04:09:07 PM PDT 24 May 19 04:20:18 PM PDT 24 3822218250 ps
T1079 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.746387996 May 19 04:01:43 PM PDT 24 May 19 04:19:58 PM PDT 24 7471614980 ps
T312 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1055497876 May 19 03:59:40 PM PDT 24 May 19 04:09:46 PM PDT 24 3569239544 ps
T1080 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.158982567 May 19 03:47:32 PM PDT 24 May 19 04:06:11 PM PDT 24 10705731400 ps
T364 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3668756751 May 19 03:59:55 PM PDT 24 May 19 04:15:03 PM PDT 24 4714353400 ps
T622 /workspace/coverage/default/1.chip_sw_edn_auto_mode.975119479 May 19 03:53:03 PM PDT 24 May 19 04:11:33 PM PDT 24 4239270100 ps
T1081 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.392702971 May 19 04:10:24 PM PDT 24 May 19 04:13:31 PM PDT 24 2648164110 ps
T1082 /workspace/coverage/default/1.rom_keymgr_functest.399404138 May 19 03:58:03 PM PDT 24 May 19 04:03:54 PM PDT 24 3598293878 ps
T1083 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2637922683 May 19 04:06:31 PM PDT 24 May 19 04:13:33 PM PDT 24 6140696668 ps
T761 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1284891227 May 19 04:14:14 PM PDT 24 May 19 04:19:41 PM PDT 24 3805281910 ps
T675 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2869740904 May 19 04:02:36 PM PDT 24 May 19 04:32:39 PM PDT 24 24721396150 ps
T1084 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3390195620 May 19 03:51:55 PM PDT 24 May 19 04:45:00 PM PDT 24 18455188911 ps
T1085 /workspace/coverage/default/2.chip_tap_straps_dev.1037882614 May 19 04:04:19 PM PDT 24 May 19 04:06:52 PM PDT 24 2746354533 ps
T54 /workspace/coverage/default/0.chip_jtag_csr_rw.4109353312 May 19 03:37:45 PM PDT 24 May 19 04:10:28 PM PDT 24 20338944120 ps
T1086 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3655844635 May 19 03:48:36 PM PDT 24 May 19 03:52:05 PM PDT 24 2724616394 ps
T1087 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3873180806 May 19 04:01:39 PM PDT 24 May 19 04:55:11 PM PDT 24 20927188990 ps
T1088 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2538699561 May 19 04:05:55 PM PDT 24 May 19 04:44:08 PM PDT 24 10483947880 ps
T109 /workspace/coverage/default/0.chip_plic_all_irqs_10.3343121614 May 19 03:48:10 PM PDT 24 May 19 03:57:21 PM PDT 24 3894701526 ps
T1089 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4212734778 May 19 03:55:49 PM PDT 24 May 19 04:02:00 PM PDT 24 4484962200 ps
T1090 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2664408508 May 19 04:02:57 PM PDT 24 May 19 04:37:14 PM PDT 24 9700033524 ps
T771 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3115038756 May 19 04:10:11 PM PDT 24 May 19 04:16:36 PM PDT 24 4254362860 ps
T26 /workspace/coverage/default/1.chip_sw_gpio.1110065365 May 19 03:50:04 PM PDT 24 May 19 03:58:16 PM PDT 24 3291464286 ps
T752 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1815431269 May 19 04:17:28 PM PDT 24 May 19 04:26:39 PM PDT 24 5873101160 ps
T169 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2681757424 May 19 03:54:29 PM PDT 24 May 19 04:02:34 PM PDT 24 5048811990 ps
T1091 /workspace/coverage/default/0.chip_tap_straps_rma.588875110 May 19 03:48:45 PM PDT 24 May 19 03:53:06 PM PDT 24 3945595935 ps
T1092 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.108074206 May 19 03:59:56 PM PDT 24 May 19 04:04:20 PM PDT 24 2313170098 ps
T320 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3567579084 May 19 03:54:20 PM PDT 24 May 19 04:27:53 PM PDT 24 7761773176 ps
T698 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.178084525 May 19 04:14:58 PM PDT 24 May 19 04:21:08 PM PDT 24 3587871080 ps
T1093 /workspace/coverage/default/2.chip_sw_uart_tx_rx.406525695 May 19 03:59:52 PM PDT 24 May 19 04:11:11 PM PDT 24 4457533560 ps
T1094 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2268130695 May 19 03:54:27 PM PDT 24 May 19 04:45:10 PM PDT 24 14449040436 ps
T1095 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.527418859 May 19 04:01:55 PM PDT 24 May 19 04:06:26 PM PDT 24 3008777568 ps
T1096 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.654244580 May 19 03:46:31 PM PDT 24 May 19 03:54:35 PM PDT 24 2872099042 ps
T1097 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.318934628 May 19 04:02:54 PM PDT 24 May 19 04:19:01 PM PDT 24 5363365636 ps
T347 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1045506713 May 19 03:49:38 PM PDT 24 May 19 04:01:43 PM PDT 24 4327687274 ps
T1098 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3878779085 May 19 04:06:51 PM PDT 24 May 19 04:15:20 PM PDT 24 4730292920 ps
T1099 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2372902734 May 19 03:51:27 PM PDT 24 May 19 04:46:25 PM PDT 24 17141926570 ps
T124 /workspace/coverage/default/4.chip_tap_straps_testunlock0.4228581910 May 19 04:08:19 PM PDT 24 May 19 04:10:56 PM PDT 24 3100249550 ps
T750 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3331093016 May 19 04:10:33 PM PDT 24 May 19 04:21:56 PM PDT 24 6479519370 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2343386518 May 19 04:03:09 PM PDT 24 May 19 04:13:59 PM PDT 24 6151702150 ps
T226 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.328407150 May 19 04:04:46 PM PDT 24 May 19 04:31:27 PM PDT 24 19154367597 ps
T1100 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.942759970 May 19 04:04:48 PM PDT 24 May 19 04:07:32 PM PDT 24 2719079505 ps
T1101 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2943589617 May 19 04:00:04 PM PDT 24 May 19 04:05:10 PM PDT 24 2334918520 ps
T1102 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2539768412 May 19 03:49:37 PM PDT 24 May 19 04:00:51 PM PDT 24 3934165890 ps
T1103 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1496284216 May 19 04:11:00 PM PDT 24 May 19 04:29:12 PM PDT 24 7918428024 ps
T748 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1144377019 May 19 04:15:33 PM PDT 24 May 19 04:24:07 PM PDT 24 4439872568 ps
T1104 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.394789992 May 19 03:44:53 PM PDT 24 May 19 03:50:57 PM PDT 24 3235699729 ps
T1105 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2747480177 May 19 03:53:49 PM PDT 24 May 19 04:04:42 PM PDT 24 5170931900 ps
T55 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1041371001 May 19 04:03:36 PM PDT 24 May 19 04:07:29 PM PDT 24 2827074440 ps
T1106 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2832709291 May 19 04:09:29 PM PDT 24 May 19 04:18:54 PM PDT 24 4152296402 ps
T1107 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.912485096 May 19 03:44:40 PM PDT 24 May 19 03:54:50 PM PDT 24 4009942168 ps
T1108 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2116431646 May 19 04:03:11 PM PDT 24 May 19 04:07:40 PM PDT 24 2884452505 ps
T1109 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3818334826 May 19 03:59:36 PM PDT 24 May 19 04:22:36 PM PDT 24 7775914806 ps
T764 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032550485 May 19 04:12:53 PM PDT 24 May 19 04:19:59 PM PDT 24 3674520124 ps
T1110 /workspace/coverage/default/0.chip_sw_hmac_enc.1567705386 May 19 03:48:40 PM PDT 24 May 19 03:55:12 PM PDT 24 3684972012 ps
T262 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1418704874 May 19 03:51:17 PM PDT 24 May 19 04:44:36 PM PDT 24 14299035566 ps
T1111 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3300547465 May 19 03:53:14 PM PDT 24 May 19 03:57:59 PM PDT 24 4694957750 ps
T1112 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2436829236 May 19 03:45:45 PM PDT 24 May 19 04:08:22 PM PDT 24 7118914566 ps
T741 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1894336074 May 19 04:14:10 PM PDT 24 May 19 04:21:55 PM PDT 24 5435662896 ps
T1113 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2001168482 May 19 04:07:12 PM PDT 24 May 19 04:15:40 PM PDT 24 3778711496 ps
T775 /workspace/coverage/default/83.chip_sw_all_escalation_resets.4074965151 May 19 04:15:57 PM PDT 24 May 19 04:24:21 PM PDT 24 4522206788 ps
T1114 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1516787148 May 19 04:10:33 PM PDT 24 May 19 04:19:48 PM PDT 24 4130660252 ps
T141 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1344766049 May 19 04:16:43 PM PDT 24 May 19 04:26:09 PM PDT 24 5342805684 ps
T683 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2374828436 May 19 04:13:17 PM PDT 24 May 19 04:22:43 PM PDT 24 4601908680 ps
T1115 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2311781104 May 19 03:50:49 PM PDT 24 May 19 03:55:29 PM PDT 24 2892312240 ps
T1116 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.280931687 May 19 03:45:39 PM PDT 24 May 19 03:51:01 PM PDT 24 2742679181 ps
T1117 /workspace/coverage/default/0.chip_sw_aes_smoketest.3321912490 May 19 03:47:14 PM PDT 24 May 19 03:51:46 PM PDT 24 2645854240 ps
T1118 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3113386627 May 19 03:54:00 PM PDT 24 May 19 03:58:07 PM PDT 24 3178901032 ps
T1119 /workspace/coverage/default/1.chip_sw_example_rom.3030678251 May 19 03:52:54 PM PDT 24 May 19 03:55:10 PM PDT 24 2229158842 ps
T1120 /workspace/coverage/default/20.chip_sw_all_escalation_resets.4050901769 May 19 04:13:25 PM PDT 24 May 19 04:25:42 PM PDT 24 5570313364 ps
T290 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.677530555 May 19 03:46:32 PM PDT 24 May 19 03:50:15 PM PDT 24 3139264520 ps
T776 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2582467968 May 19 04:16:59 PM PDT 24 May 19 04:27:48 PM PDT 24 5027005640 ps
T1121 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414699719 May 19 04:12:01 PM PDT 24 May 19 04:17:36 PM PDT 24 3764536352 ps
T699 /workspace/coverage/default/50.chip_sw_all_escalation_resets.382439425 May 19 04:15:11 PM PDT 24 May 19 04:27:53 PM PDT 24 4494023240 ps
T352 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3088908563 May 19 03:47:13 PM PDT 24 May 19 03:56:21 PM PDT 24 6489482148 ps
T1122 /workspace/coverage/default/2.chip_sw_power_idle_load.2920674623 May 19 04:05:49 PM PDT 24 May 19 04:15:04 PM PDT 24 3770919290 ps
T1123 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3028228399 May 19 04:09:33 PM PDT 24 May 19 04:18:20 PM PDT 24 3562936680 ps
T225 /workspace/coverage/default/2.chip_sw_flash_init.1640223613 May 19 04:07:27 PM PDT 24 May 19 04:29:42 PM PDT 24 17308072531 ps
T332 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2299342237 May 19 03:51:20 PM PDT 24 May 19 04:04:18 PM PDT 24 3745034274 ps
T56 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2652740254 May 19 03:49:33 PM PDT 24 May 19 03:55:35 PM PDT 24 3236507000 ps
T1124 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.262432993 May 19 03:53:48 PM PDT 24 May 19 04:18:08 PM PDT 24 7585651404 ps
T1125 /workspace/coverage/default/0.chip_sw_kmac_idle.1727573364 May 19 03:45:18 PM PDT 24 May 19 03:50:08 PM PDT 24 3208632128 ps
T1126 /workspace/coverage/default/1.chip_sw_aes_enc.3699501782 May 19 03:53:10 PM PDT 24 May 19 04:00:04 PM PDT 24 2439987608 ps
T687 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3581343966 May 19 04:16:26 PM PDT 24 May 19 04:28:02 PM PDT 24 6217363604 ps
T1127 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.229691220 May 19 03:45:26 PM PDT 24 May 19 04:02:39 PM PDT 24 5960531546 ps
T367 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3343006524 May 19 03:56:37 PM PDT 24 May 19 05:16:30 PM PDT 24 22526349292 ps
T246 /workspace/coverage/default/19.chip_sw_all_escalation_resets.913369656 May 19 04:11:43 PM PDT 24 May 19 04:22:11 PM PDT 24 5464771072 ps
T689 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2838875376 May 19 04:13:02 PM PDT 24 May 19 04:23:43 PM PDT 24 5779015542 ps
T1128 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.692298432 May 19 04:01:34 PM PDT 24 May 19 04:13:22 PM PDT 24 3853600362 ps
T1129 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2114687221 May 19 04:01:21 PM PDT 24 May 19 04:24:38 PM PDT 24 8404108776 ps
T1130 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2554911143 May 19 04:00:12 PM PDT 24 May 19 04:12:42 PM PDT 24 4270224320 ps
T1131 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1571031245 May 19 04:05:08 PM PDT 24 May 19 04:15:01 PM PDT 24 4301688094 ps
T1132 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1941926398 May 19 04:03:13 PM PDT 24 May 19 04:12:09 PM PDT 24 4720931464 ps
T708 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4012202641 May 19 04:15:28 PM PDT 24 May 19 04:26:12 PM PDT 24 5824882636 ps
T1133 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2862874580 May 19 03:57:28 PM PDT 24 May 19 04:08:29 PM PDT 24 4974866254 ps
T1134 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.882496453 May 19 03:53:11 PM PDT 24 May 19 05:09:59 PM PDT 24 16961821306 ps
T1135 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3402768600 May 19 03:56:57 PM PDT 24 May 19 04:05:00 PM PDT 24 3397503032 ps
T158 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1109712389 May 19 04:06:11 PM PDT 24 May 19 04:27:52 PM PDT 24 8583127454 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2189620378 May 19 03:54:07 PM PDT 24 May 19 04:33:02 PM PDT 24 10031618500 ps
T306 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3672273375 May 19 04:01:17 PM PDT 24 May 19 04:25:49 PM PDT 24 11834883376 ps
T1136 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1354241103 May 19 03:51:26 PM PDT 24 May 19 04:22:10 PM PDT 24 20535632667 ps
T59 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3465415781 May 19 03:59:02 PM PDT 24 May 19 04:04:33 PM PDT 24 4097153456 ps
T90 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.571555779 May 19 03:45:53 PM PDT 24 May 19 03:53:46 PM PDT 24 4566586712 ps
T1137 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1988677278 May 19 03:42:53 PM PDT 24 May 19 03:55:09 PM PDT 24 5345464181 ps
T1138 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.764428127 May 19 03:57:12 PM PDT 24 May 19 04:15:43 PM PDT 24 5771074864 ps
T1139 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.529684242 May 19 04:05:07 PM PDT 24 May 19 04:13:53 PM PDT 24 4775555416 ps
T1140 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.118535889 May 19 04:05:21 PM PDT 24 May 19 04:11:19 PM PDT 24 3681522400 ps
T1141 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4053619374 May 19 03:50:06 PM PDT 24 May 19 03:59:50 PM PDT 24 5691906017 ps
T122 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.613440340 May 19 03:44:44 PM PDT 24 May 19 03:50:15 PM PDT 24 3852654156 ps
T296 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1962693351 May 19 03:47:06 PM PDT 24 May 19 03:56:59 PM PDT 24 7461622851 ps
T1142 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1591193174 May 19 04:06:27 PM PDT 24 May 19 04:10:11 PM PDT 24 3477792100 ps
T345 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1333528859 May 19 03:51:27 PM PDT 24 May 19 03:56:05 PM PDT 24 3586569514 ps
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