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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.54 95.54 94.41 90.99 95.29 97.38 99.60


Total test records in report: 2779
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T1143 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3510952779 May 19 04:03:39 PM PDT 24 May 19 04:19:49 PM PDT 24 5481791600 ps
T1144 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.892919829 May 19 03:45:43 PM PDT 24 May 19 07:17:04 PM PDT 24 254998894360 ps
T172 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1245886211 May 19 04:06:20 PM PDT 24 May 19 04:47:15 PM PDT 24 20160321932 ps
T1145 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3845121097 May 19 04:03:23 PM PDT 24 May 19 04:11:07 PM PDT 24 7510300998 ps
T1146 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.519268504 May 19 03:54:06 PM PDT 24 May 19 04:55:55 PM PDT 24 14534832084 ps
T1147 /workspace/coverage/default/2.chip_tap_straps_rma.2488560156 May 19 04:04:14 PM PDT 24 May 19 04:08:01 PM PDT 24 3202631256 ps
T1148 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.548294712 May 19 04:14:28 PM PDT 24 May 19 04:22:40 PM PDT 24 3806826446 ps
T75 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1598661207 May 19 03:46:11 PM PDT 24 May 19 03:56:22 PM PDT 24 5005009246 ps
T1149 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1086034325 May 19 03:47:47 PM PDT 24 May 19 03:59:19 PM PDT 24 4249062200 ps
T354 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2698736073 May 19 04:13:19 PM PDT 24 May 19 04:20:13 PM PDT 24 3969545640 ps
T1150 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1572818619 May 19 04:01:20 PM PDT 24 May 19 04:43:42 PM PDT 24 10668496458 ps
T1151 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2505184751 May 19 04:14:00 PM PDT 24 May 19 04:20:05 PM PDT 24 3538452050 ps
T1152 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2944502626 May 19 03:51:48 PM PDT 24 May 19 04:12:17 PM PDT 24 8219493514 ps
T1153 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2815937005 May 19 03:53:34 PM PDT 24 May 19 04:08:22 PM PDT 24 5682282740 ps
T1154 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1679981885 May 19 03:53:01 PM PDT 24 May 19 03:58:02 PM PDT 24 3140009574 ps
T1155 /workspace/coverage/default/0.chip_sw_hmac_smoketest.981100187 May 19 03:47:26 PM PDT 24 May 19 03:52:12 PM PDT 24 2636155672 ps
T391 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.691295431 May 19 04:04:22 PM PDT 24 May 19 04:33:23 PM PDT 24 19314120790 ps
T1156 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1424190617 May 19 03:45:48 PM PDT 24 May 19 03:54:49 PM PDT 24 3947782091 ps
T1157 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1864459084 May 19 04:12:37 PM PDT 24 May 19 05:00:44 PM PDT 24 14180013092 ps
T1158 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.85609934 May 19 03:47:51 PM PDT 24 May 19 03:52:13 PM PDT 24 2858556434 ps
T1159 /workspace/coverage/default/1.rom_e2e_smoke.1348209056 May 19 04:04:45 PM PDT 24 May 19 05:00:11 PM PDT 24 14614994180 ps
T39 /workspace/coverage/default/0.chip_sw_spi_device_tpm.3900488427 May 19 03:44:37 PM PDT 24 May 19 03:51:11 PM PDT 24 3543315062 ps
T1160 /workspace/coverage/default/2.chip_sw_aes_masking_off.93232979 May 19 04:03:36 PM PDT 24 May 19 04:09:20 PM PDT 24 2692856806 ps
T319 /workspace/coverage/default/0.chip_plic_all_irqs_0.2146779609 May 19 03:46:05 PM PDT 24 May 19 04:04:05 PM PDT 24 6189660188 ps
T620 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2380103560 May 19 03:56:19 PM PDT 24 May 19 04:51:22 PM PDT 24 24896863615 ps
T1161 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1992436171 May 19 03:59:57 PM PDT 24 May 19 04:06:29 PM PDT 24 3496053016 ps
T370 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3116065100 May 19 03:57:01 PM PDT 24 May 19 03:59:53 PM PDT 24 2501298748 ps
T1162 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3899430911 May 19 04:03:49 PM PDT 24 May 19 04:10:44 PM PDT 24 2973536270 ps
T731 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1879878309 May 19 04:12:54 PM PDT 24 May 19 04:19:24 PM PDT 24 3366888818 ps
T1163 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2107384096 May 19 03:50:38 PM PDT 24 May 19 03:57:27 PM PDT 24 3593817025 ps
T762 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930463521 May 19 04:11:07 PM PDT 24 May 19 04:18:10 PM PDT 24 3768195796 ps
T1164 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1206446975 May 19 04:14:02 PM PDT 24 May 19 04:27:40 PM PDT 24 5928148650 ps
T680 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.897376692 May 19 04:13:41 PM PDT 24 May 19 04:18:32 PM PDT 24 4303509968 ps
T1165 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3650435270 May 19 03:51:50 PM PDT 24 May 19 03:58:29 PM PDT 24 3580210400 ps
T657 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.180631240 May 19 03:53:47 PM PDT 24 May 19 03:58:17 PM PDT 24 3296673980 ps
T1166 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3094703674 May 19 03:46:25 PM PDT 24 May 19 03:56:10 PM PDT 24 4381830456 ps
T233 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2924900251 May 19 03:59:54 PM PDT 24 May 19 04:10:25 PM PDT 24 4855232896 ps
T1167 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1654695519 May 19 03:43:22 PM PDT 24 May 19 03:52:33 PM PDT 24 4820280400 ps
T1168 /workspace/coverage/default/2.chip_sw_uart_smoketest.52318613 May 19 04:08:08 PM PDT 24 May 19 04:12:02 PM PDT 24 2534347296 ps
T1169 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3505069928 May 19 03:43:34 PM PDT 24 May 19 04:29:16 PM PDT 24 11869932040 ps
T1170 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3276233132 May 19 04:10:11 PM PDT 24 May 19 04:20:08 PM PDT 24 4783656440 ps
T201 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1615635303 May 19 04:02:33 PM PDT 24 May 19 04:10:28 PM PDT 24 4729054626 ps
T630 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1922914371 May 19 04:05:51 PM PDT 24 May 19 04:14:32 PM PDT 24 5660733095 ps
T247 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2944583490 May 19 04:16:18 PM PDT 24 May 19 04:24:21 PM PDT 24 4672641380 ps
T1171 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.486540684 May 19 04:09:55 PM PDT 24 May 19 04:19:19 PM PDT 24 3100795700 ps
T248 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.521266461 May 19 04:02:01 PM PDT 24 May 19 04:15:13 PM PDT 24 4939397400 ps
T1172 /workspace/coverage/default/2.chip_sw_example_manufacturer.885301486 May 19 03:59:25 PM PDT 24 May 19 04:03:22 PM PDT 24 2314775616 ps
T718 /workspace/coverage/default/30.chip_sw_all_escalation_resets.120397132 May 19 04:13:04 PM PDT 24 May 19 04:24:38 PM PDT 24 5227834176 ps
T1173 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.118665151 May 19 04:02:07 PM PDT 24 May 19 04:11:50 PM PDT 24 5199301524 ps
T1174 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3814882753 May 19 03:56:41 PM PDT 24 May 19 04:09:26 PM PDT 24 4130261743 ps
T1175 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1362881312 May 19 04:06:38 PM PDT 24 May 19 04:25:51 PM PDT 24 16760409016 ps
T1176 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1064074457 May 19 04:15:38 PM PDT 24 May 19 04:26:24 PM PDT 24 6144565360 ps
T721 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540564553 May 19 04:16:02 PM PDT 24 May 19 04:23:21 PM PDT 24 4129905912 ps
T772 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174610956 May 19 04:13:00 PM PDT 24 May 19 04:20:10 PM PDT 24 4002116542 ps
T676 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4135360633 May 19 03:51:16 PM PDT 24 May 19 04:18:18 PM PDT 24 23035608232 ps
T659 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3237550048 May 19 03:56:29 PM PDT 24 May 19 04:03:09 PM PDT 24 3246378392 ps
T1177 /workspace/coverage/default/1.chip_sival_flash_info_access.3193936587 May 19 03:49:05 PM PDT 24 May 19 03:53:40 PM PDT 24 3403389320 ps
T1178 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1855352109 May 19 03:47:37 PM PDT 24 May 19 03:52:55 PM PDT 24 3274558976 ps
T1179 /workspace/coverage/default/74.chip_sw_all_escalation_resets.988643694 May 19 04:15:50 PM PDT 24 May 19 04:26:15 PM PDT 24 5588812704 ps
T1180 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1280346600 May 19 04:03:47 PM PDT 24 May 19 04:59:15 PM PDT 24 17291664264 ps
T299 /workspace/coverage/default/18.chip_sw_all_escalation_resets.98211898 May 19 04:12:21 PM PDT 24 May 19 04:23:20 PM PDT 24 5435109040 ps
T1181 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3604604312 May 19 03:52:15 PM PDT 24 May 19 07:10:10 PM PDT 24 256141037358 ps
T321 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.377519416 May 19 03:45:19 PM PDT 24 May 19 04:10:36 PM PDT 24 6285583500 ps
T1182 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.418809842 May 19 04:02:42 PM PDT 24 May 19 04:12:00 PM PDT 24 7620848100 ps
T1183 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3751417126 May 19 03:59:03 PM PDT 24 May 19 07:21:23 PM PDT 24 64217640898 ps
T755 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2023956430 May 19 04:13:04 PM PDT 24 May 19 04:22:54 PM PDT 24 4627854528 ps
T1184 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.660262018 May 19 03:43:14 PM PDT 24 May 19 03:53:03 PM PDT 24 4215924336 ps
T1185 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.659966042 May 19 03:50:43 PM PDT 24 May 19 04:07:35 PM PDT 24 4843158313 ps
T688 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2088067858 May 19 04:12:33 PM PDT 24 May 19 04:20:56 PM PDT 24 5550830128 ps
T1186 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.975876702 May 19 04:10:12 PM PDT 24 May 19 04:18:05 PM PDT 24 4258438280 ps
T705 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1238656328 May 19 04:15:35 PM PDT 24 May 19 04:24:14 PM PDT 24 5825574458 ps
T1187 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3647268869 May 19 03:58:42 PM PDT 24 May 19 04:09:40 PM PDT 24 5586164932 ps
T1188 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.715245830 May 19 04:02:59 PM PDT 24 May 19 04:46:02 PM PDT 24 25393049020 ps
T249 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3944255065 May 19 04:13:50 PM PDT 24 May 19 04:24:26 PM PDT 24 6247175850 ps
T646 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3151729537 May 19 04:15:41 PM PDT 24 May 19 04:24:23 PM PDT 24 5040629736 ps
T753 /workspace/coverage/default/97.chip_sw_all_escalation_resets.3851353896 May 19 04:18:47 PM PDT 24 May 19 04:26:43 PM PDT 24 4614326580 ps
T1189 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4114400990 May 19 03:44:33 PM PDT 24 May 19 03:51:39 PM PDT 24 3672225052 ps
T1190 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1102028654 May 19 03:42:59 PM PDT 24 May 19 03:52:23 PM PDT 24 4478782488 ps
T1191 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.691057984 May 19 03:43:28 PM PDT 24 May 19 03:55:40 PM PDT 24 4365405400 ps
T756 /workspace/coverage/default/76.chip_sw_all_escalation_resets.1409645599 May 19 04:15:46 PM PDT 24 May 19 04:25:02 PM PDT 24 5269551688 ps
T1192 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4023740483 May 19 04:00:14 PM PDT 24 May 19 04:11:23 PM PDT 24 4454862840 ps
T223 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.393508643 May 19 03:54:08 PM PDT 24 May 19 04:53:00 PM PDT 24 14416087456 ps
T1193 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.444546371 May 19 03:48:01 PM PDT 24 May 19 03:55:12 PM PDT 24 3087880456 ps
T1194 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3002841569 May 19 04:05:45 PM PDT 24 May 19 05:08:12 PM PDT 24 14301056649 ps
T165 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1489775437 May 19 04:04:04 PM PDT 24 May 19 04:13:24 PM PDT 24 5386269790 ps
T1195 /workspace/coverage/default/36.chip_sw_all_escalation_resets.792788490 May 19 04:13:30 PM PDT 24 May 19 04:25:40 PM PDT 24 4900882720 ps
T1196 /workspace/coverage/default/1.chip_sw_example_manufacturer.1533163729 May 19 03:50:22 PM PDT 24 May 19 03:53:20 PM PDT 24 2718870126 ps
T1197 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2033724165 May 19 04:03:33 PM PDT 24 May 19 04:08:08 PM PDT 24 2200516200 ps
T1198 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2617988259 May 19 03:54:34 PM PDT 24 May 19 04:44:19 PM PDT 24 14329669876 ps
T1199 /workspace/coverage/default/1.chip_sw_hmac_enc.3201712726 May 19 03:53:45 PM PDT 24 May 19 03:59:44 PM PDT 24 3355087592 ps
T1200 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1646674218 May 19 04:05:49 PM PDT 24 May 19 04:22:39 PM PDT 24 6031651008 ps
T1201 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2359282257 May 19 04:04:30 PM PDT 24 May 19 04:23:28 PM PDT 24 7793867124 ps
T1202 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.214692092 May 19 03:53:23 PM PDT 24 May 19 05:30:04 PM PDT 24 22997594788 ps
T1203 /workspace/coverage/default/0.chip_sw_kmac_app_rom.2233105865 May 19 03:53:01 PM PDT 24 May 19 03:56:49 PM PDT 24 2660938364 ps
T171 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3899784351 May 19 03:55:07 PM PDT 24 May 19 04:04:02 PM PDT 24 3893666940 ps
T1204 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3243056915 May 19 03:44:34 PM PDT 24 May 19 07:01:10 PM PDT 24 64046086221 ps
T1205 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1229135695 May 19 03:56:20 PM PDT 24 May 19 04:00:48 PM PDT 24 2623604706 ps
T1206 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1880299612 May 19 04:02:42 PM PDT 24 May 19 04:08:30 PM PDT 24 6113929980 ps
T1207 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.331902628 May 19 04:01:04 PM PDT 24 May 19 04:21:51 PM PDT 24 8822326295 ps
T1208 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.290158160 May 19 04:15:15 PM PDT 24 May 19 04:21:10 PM PDT 24 3568890156 ps
T674 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3370507469 May 19 04:02:32 PM PDT 24 May 19 04:16:29 PM PDT 24 5006245684 ps
T1209 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1001877978 May 19 03:46:14 PM PDT 24 May 19 03:52:03 PM PDT 24 4877127507 ps
T91 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2921523707 May 19 04:19:11 PM PDT 24 May 19 04:27:54 PM PDT 24 5882893520 ps
T1210 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.489249924 May 19 04:08:51 PM PDT 24 May 19 04:19:19 PM PDT 24 5955589880 ps
T1211 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3119429592 May 19 03:50:06 PM PDT 24 May 19 04:07:38 PM PDT 24 6256886317 ps
T1212 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2733815519 May 19 04:12:23 PM PDT 24 May 19 04:18:26 PM PDT 24 3833049024 ps
T250 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2798946661 May 19 04:07:44 PM PDT 24 May 19 04:17:47 PM PDT 24 5643474546 ps
T701 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1793930454 May 19 04:17:15 PM PDT 24 May 19 04:28:24 PM PDT 24 5570093076 ps
T1213 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1834805995 May 19 04:03:28 PM PDT 24 May 19 04:56:51 PM PDT 24 14582555840 ps
T1214 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3679471862 May 19 04:03:32 PM PDT 24 May 19 04:07:40 PM PDT 24 2245573555 ps
T243 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.533826956 May 19 03:56:08 PM PDT 24 May 19 04:15:56 PM PDT 24 9256380900 ps
T190 /workspace/coverage/default/1.chip_jtag_csr_rw.950058641 May 19 03:48:00 PM PDT 24 May 19 04:25:52 PM PDT 24 20068596181 ps
T765 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.523141214 May 19 04:11:50 PM PDT 24 May 19 04:18:20 PM PDT 24 3381524068 ps
T1215 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1181586132 May 19 04:04:32 PM PDT 24 May 19 04:12:55 PM PDT 24 3082577634 ps
T1216 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3702554319 May 19 03:58:07 PM PDT 24 May 19 04:25:11 PM PDT 24 9990043565 ps
T1217 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1180267416 May 19 03:51:31 PM PDT 24 May 19 04:01:40 PM PDT 24 4189782350 ps
T1218 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.332032721 May 19 04:16:35 PM PDT 24 May 19 04:21:40 PM PDT 24 3187163440 ps
T1219 /workspace/coverage/default/1.rom_e2e_asm_init_prod.620317950 May 19 04:00:19 PM PDT 24 May 19 05:06:43 PM PDT 24 14473080859 ps
T1220 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2824141836 May 19 03:51:39 PM PDT 24 May 19 04:03:14 PM PDT 24 4396111114 ps
T1221 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3118817274 May 19 04:16:05 PM PDT 24 May 19 04:28:31 PM PDT 24 5307917524 ps
T1222 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1513217674 May 19 04:14:54 PM PDT 24 May 19 04:20:25 PM PDT 24 3314715322 ps
T1223 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.883152293 May 19 03:55:38 PM PDT 24 May 19 04:01:22 PM PDT 24 2741272354 ps
T1224 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1730205231 May 19 04:08:26 PM PDT 24 May 19 04:20:00 PM PDT 24 4663309832 ps
T1225 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1256329395 May 19 04:02:12 PM PDT 24 May 19 04:25:10 PM PDT 24 6472075310 ps
T1226 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1014863739 May 19 04:02:43 PM PDT 24 May 19 04:07:36 PM PDT 24 3196602104 ps
T727 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4290972593 May 19 04:14:29 PM PDT 24 May 19 04:22:40 PM PDT 24 3571161520 ps
T1227 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1876923986 May 19 03:56:02 PM PDT 24 May 19 03:59:04 PM PDT 24 2035449840 ps
T1228 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3172246745 May 19 04:18:28 PM PDT 24 May 19 04:26:53 PM PDT 24 5646666456 ps
T1229 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1768501694 May 19 04:06:16 PM PDT 24 May 19 04:25:05 PM PDT 24 7211774804 ps
T1230 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1736018171 May 19 04:13:20 PM PDT 24 May 19 04:23:35 PM PDT 24 4686412848 ps
T62 /workspace/coverage/cover_reg_top/4.xbar_random.2154771998 May 19 03:19:42 PM PDT 24 May 19 03:21:11 PM PDT 24 2299586790 ps
T63 /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1974051797 May 19 03:32:01 PM PDT 24 May 19 03:33:32 PM PDT 24 8841092290 ps
T64 /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3262937404 May 19 03:28:13 PM PDT 24 May 19 03:30:11 PM PDT 24 2553124093 ps
T65 /workspace/coverage/cover_reg_top/15.chip_tl_errors.3535125168 May 19 03:21:49 PM PDT 24 May 19 03:26:31 PM PDT 24 4214150708 ps
T105 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2862682094 May 19 03:24:53 PM PDT 24 May 19 03:25:16 PM PDT 24 113504992 ps
T72 /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4236576682 May 19 03:21:29 PM PDT 24 May 19 03:21:36 PM PDT 24 39310749 ps
T66 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3830405590 May 19 03:35:07 PM PDT 24 May 19 03:37:58 PM PDT 24 4975868186 ps
T397 /workspace/coverage/cover_reg_top/60.xbar_smoke.4182975827 May 19 03:29:34 PM PDT 24 May 19 03:29:43 PM PDT 24 178587541 ps
T234 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3067779725 May 19 03:32:50 PM PDT 24 May 19 03:46:17 PM PDT 24 8084149009 ps
T395 /workspace/coverage/cover_reg_top/28.xbar_stress_all.3387254038 May 19 03:24:32 PM PDT 24 May 19 03:34:11 PM PDT 24 16119817397 ps
T409 /workspace/coverage/cover_reg_top/45.xbar_same_source.455001430 May 19 03:27:21 PM PDT 24 May 19 03:27:32 PM PDT 24 109005869 ps
T638 /workspace/coverage/cover_reg_top/14.xbar_error_random.2040216134 May 19 03:21:50 PM PDT 24 May 19 03:22:15 PM PDT 24 272102567 ps
T696 /workspace/coverage/cover_reg_top/28.xbar_error_random.2548881523 May 19 03:24:33 PM PDT 24 May 19 03:25:10 PM PDT 24 1028998096 ps
T410 /workspace/coverage/cover_reg_top/60.xbar_same_source.236033849 May 19 03:29:32 PM PDT 24 May 19 03:30:11 PM PDT 24 570358517 ps
T484 /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1069414107 May 19 03:29:14 PM PDT 24 May 19 03:43:57 PM PDT 24 50508270837 ps
T448 /workspace/coverage/cover_reg_top/22.xbar_same_source.3957409718 May 19 03:23:17 PM PDT 24 May 19 03:23:51 PM PDT 24 1047153057 ps
T546 /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1983808308 May 19 03:26:10 PM PDT 24 May 19 03:26:18 PM PDT 24 53667955 ps
T785 /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.4266214879 May 19 03:24:19 PM PDT 24 May 19 03:41:38 PM PDT 24 61379357787 ps
T481 /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2035240654 May 19 03:19:32 PM PDT 24 May 19 03:20:07 PM PDT 24 269991621 ps
T482 /workspace/coverage/cover_reg_top/3.xbar_same_source.3806573109 May 19 03:19:33 PM PDT 24 May 19 03:19:57 PM PDT 24 616225666 ps
T179 /workspace/coverage/cover_reg_top/13.chip_csr_rw.1041051153 May 19 03:21:44 PM PDT 24 May 19 03:26:43 PM PDT 24 4566751824 ps
T1231 /workspace/coverage/cover_reg_top/66.xbar_random.2529952401 May 19 03:30:24 PM PDT 24 May 19 03:30:39 PM PDT 24 148754116 ps
T647 /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.620600743 May 19 03:29:14 PM PDT 24 May 19 03:34:09 PM PDT 24 27817465051 ps
T494 /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.738133900 May 19 03:31:36 PM PDT 24 May 19 03:32:08 PM PDT 24 341423018 ps
T574 /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2267594773 May 19 03:25:19 PM PDT 24 May 19 03:25:26 PM PDT 24 37680405 ps
T796 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1717798153 May 19 03:22:49 PM PDT 24 May 19 03:23:50 PM PDT 24 350759765 ps
T1232 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.276297451 May 19 03:25:43 PM PDT 24 May 19 03:26:35 PM PDT 24 1381622602 ps
T1233 /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.777400980 May 19 03:19:03 PM PDT 24 May 19 03:24:37 PM PDT 24 11145111145 ps
T573 /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.262580836 May 19 03:32:24 PM PDT 24 May 19 03:33:28 PM PDT 24 6423634439 ps
T358 /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.2449053470 May 19 03:19:18 PM PDT 24 May 19 04:50:23 PM PDT 24 57227002245 ps
T1234 /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.516580788 May 19 03:26:35 PM PDT 24 May 19 03:26:57 PM PDT 24 453368802 ps
T404 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3133941922 May 19 03:24:19 PM PDT 24 May 19 03:32:28 PM PDT 24 7555556273 ps
T1235 /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1424331181 May 19 03:28:08 PM PDT 24 May 19 03:28:15 PM PDT 24 45666132 ps
T507 /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3399989171 May 19 03:33:05 PM PDT 24 May 19 03:34:57 PM PDT 24 6655698071 ps
T632 /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3186986402 May 19 03:19:45 PM PDT 24 May 19 03:20:20 PM PDT 24 853941024 ps
T455 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2634898708 May 19 03:35:39 PM PDT 24 May 19 03:39:48 PM PDT 24 4166024853 ps
T514 /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.3705223886 May 19 03:34:33 PM PDT 24 May 19 03:34:39 PM PDT 24 34351525 ps
T598 /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2486239557 May 19 03:29:54 PM PDT 24 May 19 03:31:16 PM PDT 24 8273633737 ps
T503 /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.63960812 May 19 03:34:56 PM PDT 24 May 19 03:36:38 PM PDT 24 10304074440 ps
T558 /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3337206308 May 19 03:30:58 PM PDT 24 May 19 03:31:30 PM PDT 24 766141238 ps
T575 /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.749261166 May 19 03:30:17 PM PDT 24 May 19 03:31:43 PM PDT 24 5313398658 ps
T830 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1622426654 May 19 03:25:05 PM PDT 24 May 19 03:25:46 PM PDT 24 69401974 ps
T500 /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1141546458 May 19 03:20:33 PM PDT 24 May 19 03:20:59 PM PDT 24 582890013 ps
T406 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.880969924 May 19 03:20:10 PM PDT 24 May 19 03:21:40 PM PDT 24 434966476 ps
T560 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.379846903 May 19 03:29:35 PM PDT 24 May 19 03:31:45 PM PDT 24 338962149 ps
T1236 /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3432607190 May 19 03:18:59 PM PDT 24 May 19 03:19:05 PM PDT 24 69498674 ps
T453 /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1091718024 May 19 03:23:38 PM PDT 24 May 19 03:32:19 PM PDT 24 29599621819 ps
T524 /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.800154867 May 19 03:26:42 PM PDT 24 May 19 03:27:22 PM PDT 24 924186242 ps
T1237 /workspace/coverage/cover_reg_top/50.xbar_error_random.91945516 May 19 03:28:03 PM PDT 24 May 19 03:28:21 PM PDT 24 422982179 ps
T677 /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2816091430 May 19 03:35:38 PM PDT 24 May 19 03:36:07 PM PDT 24 290585535 ps
T545 /workspace/coverage/cover_reg_top/65.xbar_smoke.4179037512 May 19 03:30:19 PM PDT 24 May 19 03:30:30 PM PDT 24 225708030 ps
T521 /workspace/coverage/cover_reg_top/98.xbar_same_source.1177378674 May 19 03:35:21 PM PDT 24 May 19 03:35:37 PM PDT 24 427871891 ps
T512 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2852896072 May 19 03:31:48 PM PDT 24 May 19 03:35:15 PM PDT 24 372083785 ps
T413 /workspace/coverage/cover_reg_top/41.xbar_stress_all.1404604664 May 19 03:26:47 PM PDT 24 May 19 03:32:55 PM PDT 24 9702668220 ps
T492 /workspace/coverage/cover_reg_top/56.xbar_random.3567410898 May 19 03:28:49 PM PDT 24 May 19 03:29:36 PM PDT 24 594592097 ps
T1238 /workspace/coverage/cover_reg_top/99.xbar_smoke.2106269655 May 19 03:35:25 PM PDT 24 May 19 03:35:35 PM PDT 24 207258347 ps
T792 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.392903924 May 19 03:27:42 PM PDT 24 May 19 03:27:52 PM PDT 24 74278879 ps
T412 /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.907924395 May 19 03:29:48 PM PDT 24 May 19 03:58:10 PM PDT 24 97192256473 ps
T779 /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.344276601 May 19 03:29:56 PM PDT 24 May 19 03:42:55 PM PDT 24 40868139337 ps
T537 /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3817993695 May 19 03:24:28 PM PDT 24 May 19 03:32:26 PM PDT 24 44805362331 ps
T570 /workspace/coverage/cover_reg_top/29.xbar_stress_all.671398718 May 19 03:24:42 PM PDT 24 May 19 03:28:17 PM PDT 24 5595959996 ps
T182 /workspace/coverage/cover_reg_top/15.chip_csr_rw.2531845845 May 19 03:22:02 PM PDT 24 May 19 03:28:14 PM PDT 24 4265735380 ps
T678 /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1619728771 May 19 03:30:50 PM PDT 24 May 19 03:32:34 PM PDT 24 3284220174 ps
T535 /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3007601903 May 19 03:32:18 PM PDT 24 May 19 03:32:25 PM PDT 24 77147328 ps
T1239 /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2847344314 May 19 03:25:39 PM PDT 24 May 19 03:27:37 PM PDT 24 7404979794 ps
T581 /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.575890208 May 19 03:26:09 PM PDT 24 May 19 03:26:30 PM PDT 24 214061148 ps
T637 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2682301048 May 19 03:33:44 PM PDT 24 May 19 03:36:52 PM PDT 24 4591165584 ps
T446 /workspace/coverage/cover_reg_top/28.xbar_random.4136468963 May 19 03:24:24 PM PDT 24 May 19 03:25:14 PM PDT 24 1397399707 ps
T1240 /workspace/coverage/cover_reg_top/81.xbar_smoke.3214680878 May 19 03:32:47 PM PDT 24 May 19 03:32:57 PM PDT 24 213127844 ps
T1241 /workspace/coverage/cover_reg_top/65.xbar_error_random.3816670648 May 19 03:30:18 PM PDT 24 May 19 03:30:50 PM PDT 24 380208575 ps
T1242 /workspace/coverage/cover_reg_top/29.xbar_error_random.3845029613 May 19 03:24:44 PM PDT 24 May 19 03:24:53 PM PDT 24 66317773 ps
T496 /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3510819476 May 19 03:31:26 PM PDT 24 May 19 03:32:05 PM PDT 24 492804352 ps
T1243 /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1357326603 May 19 03:25:20 PM PDT 24 May 19 03:25:27 PM PDT 24 70091978 ps
T636 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1851304081 May 19 03:25:29 PM PDT 24 May 19 03:31:35 PM PDT 24 7400575579 ps
T1244 /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.963731699 May 19 03:31:25 PM PDT 24 May 19 03:31:48 PM PDT 24 533476423 ps
T672 /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3406356656 May 19 03:34:24 PM PDT 24 May 19 03:35:56 PM PDT 24 8241611710 ps
T405 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.4179674790 May 19 03:23:42 PM PDT 24 May 19 03:37:32 PM PDT 24 7625082627 ps
T1245 /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.43930135 May 19 03:33:07 PM PDT 24 May 19 03:33:16 PM PDT 24 132722099 ps
T592 /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1623002309 May 19 03:19:47 PM PDT 24 May 19 03:21:28 PM PDT 24 260807547 ps
T786 /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1981403993 May 19 03:24:40 PM PDT 24 May 19 03:46:21 PM PDT 24 72024981004 ps
T791 /workspace/coverage/cover_reg_top/85.xbar_access_same_device.4050956267 May 19 03:33:25 PM PDT 24 May 19 03:34:05 PM PDT 24 1035509780 ps
T407 /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1477663651 May 19 03:35:20 PM PDT 24 May 19 03:46:20 PM PDT 24 62045665220 ps
T1246 /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1009387097 May 19 03:19:17 PM PDT 24 May 19 03:26:09 PM PDT 24 8114183931 ps
T599 /workspace/coverage/cover_reg_top/19.xbar_smoke.347193012 May 19 03:22:39 PM PDT 24 May 19 03:22:47 PM PDT 24 50418016 ps
T411 /workspace/coverage/cover_reg_top/55.xbar_same_source.394378127 May 19 03:28:48 PM PDT 24 May 19 03:29:26 PM PDT 24 1293369094 ps
T402 /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3738123286 May 19 03:23:51 PM PDT 24 May 19 03:25:32 PM PDT 24 2225634317 ps
T577 /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1421690668 May 19 03:32:52 PM PDT 24 May 19 03:35:54 PM PDT 24 1442417664 ps
T474 /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3515546376 May 19 03:24:43 PM PDT 24 May 19 03:25:45 PM PDT 24 3397401875 ps
T445 /workspace/coverage/cover_reg_top/81.xbar_random.3679504697 May 19 03:32:46 PM PDT 24 May 19 03:33:13 PM PDT 24 308394176 ps
T1247 /workspace/coverage/cover_reg_top/96.xbar_smoke.3918198793 May 19 03:35:08 PM PDT 24 May 19 03:35:17 PM PDT 24 164523665 ps
T631 /workspace/coverage/cover_reg_top/18.chip_tl_errors.814768655 May 19 03:22:24 PM PDT 24 May 19 03:23:44 PM PDT 24 3125366314 ps
T811 /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3688793251 May 19 03:29:38 PM PDT 24 May 19 03:32:36 PM PDT 24 169449699 ps
T414 /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.646707293 May 19 03:23:36 PM PDT 24 May 19 03:40:52 PM PDT 24 99062424447 ps
T1248 /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1959155369 May 19 03:18:49 PM PDT 24 May 19 03:22:19 PM PDT 24 7416282025 ps
T1249 /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1608511487 May 19 03:19:35 PM PDT 24 May 19 03:20:52 PM PDT 24 6948964878 ps
T460 /workspace/coverage/cover_reg_top/29.xbar_same_source.3846444335 May 19 03:24:40 PM PDT 24 May 19 03:25:47 PM PDT 24 2082246837 ps
T787 /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1468398473 May 19 03:33:36 PM PDT 24 May 19 03:35:47 PM PDT 24 3008698710 ps
T1250 /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3872533901 May 19 03:31:20 PM PDT 24 May 19 03:32:22 PM PDT 24 3706682669 ps
T1251 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.4220540986 May 19 03:28:55 PM PDT 24 May 19 03:30:11 PM PDT 24 6757741004 ps
T456 /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3624786118 May 19 03:21:58 PM PDT 24 May 19 03:22:12 PM PDT 24 141179693 ps
T435 /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1504068380 May 19 03:25:08 PM PDT 24 May 19 04:04:29 PM PDT 24 133298481136 ps
T1252 /workspace/coverage/cover_reg_top/2.xbar_smoke.3485459351 May 19 03:19:19 PM PDT 24 May 19 03:19:27 PM PDT 24 168911402 ps
T1253 /workspace/coverage/cover_reg_top/7.xbar_error_random.3514932423 May 19 03:20:33 PM PDT 24 May 19 03:20:51 PM PDT 24 417364003 ps
T464 /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.679210498 May 19 03:19:09 PM PDT 24 May 19 03:19:44 PM PDT 24 429592298 ps
T1254 /workspace/coverage/cover_reg_top/15.xbar_error_random.2819511315 May 19 03:21:58 PM PDT 24 May 19 03:22:32 PM PDT 24 426851113 ps
T1255 /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2945741301 May 19 03:20:44 PM PDT 24 May 19 03:20:51 PM PDT 24 39789798 ps
T444 /workspace/coverage/cover_reg_top/76.xbar_same_source.3225301450 May 19 03:32:01 PM PDT 24 May 19 03:32:59 PM PDT 24 1995258089 ps
T1256 /workspace/coverage/cover_reg_top/25.xbar_same_source.3847750301 May 19 03:23:56 PM PDT 24 May 19 03:24:05 PM PDT 24 157545674 ps
T641 /workspace/coverage/cover_reg_top/31.xbar_error_random.2393528883 May 19 03:25:04 PM PDT 24 May 19 03:26:08 PM PDT 24 1767157996 ps
T1257 /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3830131890 May 19 03:28:34 PM PDT 24 May 19 03:28:52 PM PDT 24 249039228 ps
T642 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2595617113 May 19 03:23:12 PM PDT 24 May 19 03:25:00 PM PDT 24 2594997681 ps
T1258 /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.3151571216 May 19 03:28:40 PM PDT 24 May 19 03:28:48 PM PDT 24 118033544 ps
T569 /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2877247295 May 19 03:32:48 PM PDT 24 May 19 03:41:09 PM PDT 24 44807879702 ps
T840 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1792964119 May 19 03:21:10 PM PDT 24 May 19 03:21:24 PM PDT 24 56012156 ps
T1259 /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.782234993 May 19 03:19:59 PM PDT 24 May 19 03:20:16 PM PDT 24 117706255 ps
T591 /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.488226064 May 19 03:25:21 PM PDT 24 May 19 03:26:38 PM PDT 24 7576441155 ps
T1260 /workspace/coverage/cover_reg_top/6.xbar_smoke.441890679 May 19 03:20:05 PM PDT 24 May 19 03:20:12 PM PDT 24 51306514 ps
T671 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1930311917 May 19 03:31:54 PM PDT 24 May 19 03:33:45 PM PDT 24 10678239418 ps
T596 /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3434125548 May 19 03:28:00 PM PDT 24 May 19 03:33:24 PM PDT 24 17510368357 ps
T551 /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2750255731 May 19 03:32:32 PM PDT 24 May 19 03:32:45 PM PDT 24 256261810 ps
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