CHIP Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.891m	2.689ms	3	3	100.00
		chip_sw_example_rom	2.230m	2.229ms	3	3	100.00
		chip_sw_example_manufacturer	4.436m	2.741ms	3	3	100.00
		chip_sw_example_concurrency	4.231m	2.916ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.032m	7.424ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.695m	5.763ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.823h	59.114ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.865h	63.298ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.081m	2.249ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.865h	63.298ms	4	5	80.00
		chip_csr_rw	11.695m	5.763ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.650s	271.203us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.816m	4.211ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.816m	4.211ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.816m	4.211ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.555m	4.334ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.555m	4.334ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.435m	4.265ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.718m	4.456ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	12.490m	4.270ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	44.289m	12.705ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	41.553m	12.766ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	19.889m	7.953ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.304m	6.064ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.304m	6.064ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.425m	2.666ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.033m	3.237ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.814m	4.982ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	27.228m	13.894ms	5	5	100.00
		chip_tap_straps_testunlock0	9.873m	5.338ms	4	5	80.00
		chip_tap_straps_rma	15.068m	7.681ms	5	5	100.00
		chip_tap_straps_prod	31.379m	16.170ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.876m	2.340ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.520m	8.233ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.756m	6.594ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.756m	6.594ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	18.243m	8.194ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	42.851m	16.156ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.792m	3.854ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.616m	5.771ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.077m	18.701ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.637m	2.909ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.954m	6.472ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.811m	2.956ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.726m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.534m	3.714ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.806m	5.666ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.372m	2.975ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.349m	2.743ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	14.262m	8.141ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.082m	5.415ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.671m	2.814ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.082m	5.415ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.787m	3.160ms	3	3	100.00
		chip_sw_aes_smoketest	5.539m	2.444ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.542m	3.496ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.393m	2.313ms	3	3	100.00
		chip_sw_csrng_smoketest	4.782m	2.024ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.537m	3.519ms	3	3	100.00
		chip_sw_gpio_smoketest	5.203m	3.371ms	3	3	100.00
		chip_sw_hmac_smoketest	6.858m	3.539ms	3	3	100.00
		chip_sw_kmac_smoketest	5.623m	2.609ms	3	3	100.00
		chip_sw_otbn_smoketest	48.991m	10.593ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.475m	3.433ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.957m	5.586ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.796m	5.536ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.361m	2.859ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.986m	2.884ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.096m	3.179ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.367m	2.603ms	3	3	100.00
		chip_sw_uart_smoketest	5.524m	3.223ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.340m	4.938ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.839h	76.995ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.003h	14.401ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.022m	4.857ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.486m	5.097ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.881m	10.008ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	6.726m	4.239ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.372h	64.218ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.734m	5.035ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.734m	5.035ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.865h	63.298ms	4	5	80.00
		chip_same_csr_outstanding	1.391h	32.437ms	19	20	95.00
		chip_csr_hw_reset	7.032m	7.424ms	5	5	100.00
		chip_csr_rw	11.695m	5.763ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.865h	63.298ms	4	5	80.00
		chip_same_csr_outstanding	1.391h	32.437ms	19	20	95.00
		chip_csr_hw_reset	7.032m	7.424ms	5	5	100.00
		chip_csr_rw	11.695m	5.763ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.921m	2.658ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.360s	51.234us	100	100	100.00
		xbar_smoke_large_delays	1.935m	10.402ms	100	100	100.00
		xbar_smoke_slow_rsp	2.167m	7.258ms	100	100	100.00
		xbar_random_zero_delays	1.051m	649.570us	100	100	100.00
		xbar_random_large_delays	23.005m	111.668ms	100	100	100.00
		xbar_random_slow_rsp	21.074m	66.622ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.029m	1.364ms	100	100	100.00
		xbar_error_and_unmapped_addr	51.830s	1.233ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.676m	2.464ms	100	100	100.00
		xbar_error_and_unmapped_addr	51.830s	1.233ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.038m	4.313ms	100	100	100.00
		xbar_access_same_device_slow_rsp	50.210m	159.097ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.418m	2.709ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.443m	15.837ms	100	100	100.00
		xbar_stress_all_with_error	15.585m	22.646ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	15.008m	8.423ms	100	100	100.00
		xbar_stress_all_with_reset_error	20.623m	13.872ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.003h	14.401ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	49.466m	30.354ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	56.506m	13.976ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	46.489m	10.948ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	58.077m	14.224ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	57.995m	13.974ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	59.713m	13.946ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	49.737m	14.330ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	52.372m	10.885ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	56.024m	14.072ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	57.174m	14.404ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.008h	14.382ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.030h	14.535ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.280h	16.962ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.331h	22.526ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.611h	22.998ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.498h	22.982ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.456h	22.202ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.357h	16.508ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.409h	21.928ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.396h	21.965ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.451h	21.508ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.584h	21.740ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	47.701m	10.660ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	52.072m	12.818ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	54.267m	13.017ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	1.076h	14.072ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	59.041m	12.981ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	41.246m	9.925ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	48.544m	12.963ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	50.370m	13.415ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	47.588m	13.361ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	54.521m	13.834ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	50.192m	11.253ms	3	3	100.00
		rom_e2e_asm_init_dev	57.168m	14.324ms	3	3	100.00
		rom_e2e_asm_init_prod	1.106h	14.473ms	3	3	100.00
		rom_e2e_asm_init_prod_end	57.290m	13.903ms	3	3	100.00
		rom_e2e_asm_init_rma	1.041h	14.301ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.183h	15.249ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	53.364m	14.583ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.118h	13.885ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.202h	20.016ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.880m	2.440ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.637m	2.909ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.232m	3.075ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.133m	3.224ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	38.897m	10.032ms	2	3	66.67
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	19.390ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	19.390ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.224m	4.110ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	10.957m	5.586ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.224m	4.110ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.248m	9.033ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.248m	9.033ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.435m	7.919ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.553m	4.797ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.736m	5.948ms	3	3	100.00
		chip_sw_aes_idle	5.133m	3.224ms	3	3	100.00
		chip_sw_hmac_enc_idle	7.167m	3.427ms	3	3	100.00
		chip_sw_kmac_idle	4.814m	3.209ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.250m	4.280ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	6.177m	4.485ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	7.612m	4.238ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	11.070m	4.937ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	22.673m	11.705ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.298m	4.108ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.677m	4.082ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.966m	4.148ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.109m	4.884ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.510m	4.249ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	9.730m	4.382ms	3	3	100.00
		chip_sw_ast_clk_outputs	18.243m	8.194ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.515m	4.304ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.966m	4.148ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.109m	4.884ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.792m	3.854ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.616m	5.771ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.077m	18.701ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.637m	2.909ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.954m	6.472ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.811m	2.956ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	25.726m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.534m	3.714ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.806m	5.666ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.372m	2.975ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.255m	3.334ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.634m	5.237ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.820m	7.212ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	56.142m	24.853ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.460m	3.537ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.405m	2.832ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	30.970m	10.010ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	4.836m	2.942ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.792m	5.089ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.680m	25.079ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	59.669m	17.841ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	18.243m	8.194ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.663m	4.880ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.375m	3.083ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	26.353m	7.477ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	33.537m	7.762ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.197m	4.732ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.086m	5.391ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.613m	2.741ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.466m	8.219ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	30.583m	24.956ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.281m	2.990ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.670s	10.280us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.439m	4.950ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	30.583m	24.956ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	30.583m	24.956ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	53.501m	20.927ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	53.501m	20.927ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.819m	6.152ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	19.390ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.238h	18.339ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.829m	2.753ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.001m	6.282ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.829m	2.753ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	33.537m	7.762ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.743m	2.667ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	43.968m	24.630ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.665m	6.362ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.616m	5.771ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.071m	4.328ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.792m	3.854ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	8.707m	4.785ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	43.968m	24.630ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.966m	3.209ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	8.707m	4.785ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.476m	7.416ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.321m	6.019ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.917m	4.983ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.917m	4.983ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.534m	3.685ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.811m	2.956ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	7.167m	3.427ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.292m	4.280ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	15.260m	5.824ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.517m	4.746ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.948m	3.745ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	25.726m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	31.354m	10.010ms	1	3	33.33
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	38.897m	10.032ms	2	3	66.67
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.105h	11.866ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.561m	2.201ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.907m	2.974ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.534m	3.714ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.090m	3.271ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.425m	2.825ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.814m	3.209ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.108m	4.685ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	27.228m	13.894ms	5	5	100.00
		chip_tap_straps_rma	15.068m	7.681ms	5	5	100.00
		chip_tap_straps_prod	31.379m	16.170ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.802m	3.190ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	41.742m	10.010ms	1	3	33.33
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.792m	3.104ms	0	3	0.00
		chip_sw_flash_rma_unlocked	8.707m	4.785ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.184m	4.365ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.746m	7.939ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.197m	6.506ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.283m	8.404ms	3	3	100.00
		chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
		chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
		chip_sw_rom_ctrl_integrity_check	8.088m	9.443ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	17.341m	7.777ms	3	3	100.00
		chip_prim_tl_access	3.476m	7.416ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.515m	4.304ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.298m	4.108ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.677m	4.082ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.966m	4.148ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.109m	4.884ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.510m	4.249ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	9.730m	4.382ms	3	3	100.00
		chip_tap_straps_dev	27.228m	13.894ms	5	5	100.00
		chip_tap_straps_rma	15.068m	7.681ms	5	5	100.00
		chip_tap_straps_prod	31.379m	16.170ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.846m	8.114ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	8.461m	3.913ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	3.509m	4.332ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.945m	4.351ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	3.065m	4.318ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	3.272m	4.512ms	0	3	0.00
		chip_rv_dm_lc_disabled	6.846m	8.114ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3.337m	4.500ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	4.411m	4.261ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	2.754m	3.603ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.583m	2.586ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	3.272m	4.512ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.650m	4.663ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	3.306m	4.658ms	0	3	0.00
		rom_volatile_raw_unlock	4.132m	3.936ms	0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	43.968m	24.630ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.869m	4.302ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	10.858m	5.171ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.645m	3.311ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	43.968m	24.630ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.869m	4.302ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.177m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	10.858m	5.171ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.645m	3.311ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.892m	14.804ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.802m	3.190ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.184m	4.365ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.746m	7.939ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.197m	6.506ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.283m	8.404ms	3	3	100.00
		chip_sw_lc_ctrl_transition	4.283m	3.919ms	0	15	0.00
		chip_prim_tl_access	3.476m	7.416ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.476m	7.416ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.706m	8.278ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	29.018m	19.314ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.659m	7.018ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	15.338m	9.701ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.837m	6.846ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	33.269m	20.902ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.488m	14.878ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	14.248m	9.033ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	29.933m	13.159ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.718m	4.896ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.706m	8.278ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.458m	5.098ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	52.755m	41.471ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.915m	5.231ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	6.482m	4.630ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	33.612m	25.569ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.466m	8.219ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	27.342m	9.668ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	43.034m	25.393ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.888m	2.883ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.088m	9.443ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.088m	9.443ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	27.342m	9.668ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	33.612m	25.569ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	12.718m	4.896ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.957m	5.586ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.223m	3.485ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.482m	7.384ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.183m	4.820ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	29.380m	14.648ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.502m	3.009ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	33.430m	7.814ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.372m	5.812ms	3	3	100.00
		chip_plic_all_irqs_10	10.765m	4.431ms	3	3	100.00
		chip_plic_all_irqs_20	13.020m	4.420ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.624m	3.246ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.594m	2.950ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.003h	14.401ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.286m	7.879ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.879m	4.740ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.547m	3.543ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.990m	3.052ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.858m	5.171ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.806m	5.666ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	10.158m	6.643ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.944m	7.177ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.341m	7.777ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
		chip_sw_data_integrity_escalation	15.756m	6.594ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.869m	2.615ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.832m	3.129ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.685m	4.155ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.553m	3.427ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	34.477m	7.915ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.999h	31.730ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	45.686m	11.870ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.830m	3.387ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.108m	4.685ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.713m	2.741ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	29.380m	14.648ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.921m	4.721ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.363m	4.143ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	31.574m	12.170ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	26.353m	7.477ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	33.430m	7.814ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.522h	254.999ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	37.836m	20.069ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.495m	13.974ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.223m	3.485ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.160m	5.005ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	8.939m	3.755ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	15.068m	7.681ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.846m	8.114ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2521	2627	95.96
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.061m	2.552ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.993m	5.039ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.928m	1.987ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.738m	2.319ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.924m	2.128ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.422h	57.048ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.045h	57.538ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.147h	51.496ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.378m	3.101ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	8.861m	3.102ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	27.743m	7.326ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	34.273m	9.700ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.556m	3.765ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	18.500m	5.771ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.526m	2.728ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.874m	4.567ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	10.360m	5.204ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.765m	5.349ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	27.342m	9.668ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.623m	6.101ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.555m	4.334ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.112h	19.021ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.928m	1.987ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.738m	2.319ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.924m	2.128ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.013m	5.519ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	5.743m	2.464ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	9.394m	4.479ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	55.718m	17.012ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.315m	5.410ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.322m	4.976ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.800m	5.883ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.737m	3.392ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.138m	2.132ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	7.158m	3.088ms	3	3	100.00
		TOTAL			2779	2922	95.11

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	9	100.00
V1	18	18	16	88.89
V2	281	266	218	77.58
V2S	1	1	1	100.00
V3	90	21	11	12.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.54	95.54	94.41	90.99	--	95.29	97.38	99.60

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.110973773142190658860196431746627320601688750904015208213551316728674589481839
    Line 369, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2006.106894 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2006.106894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.88569131964323351054018765097092767692014134534711391309185279149965320427012
    Line 399, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2082.858049 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2082.858049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

Test chip_sw_lc_ctrl_transition has 15 failures.

0.chip_sw_lc_ctrl_transition.60727215912437664836573878284667027589831925904490445714616419721652617349650
Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 3795.818987 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3795.818987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_transition.50044100619521496627002733269842059114626004751076134694267242902387457211011
Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4140.439678 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4140.439678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

0.chip_sw_clkmgr_external_clk_src_for_lc.36728912029634711566921737711900986101574872586215111390465887735524454005062
Line 856, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 2673.875864 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2673.875864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_external_clk_src_for_lc.30913676440890145630129633410804297307038911417675814213593099774663917671987
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 4303.502130 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4303.502130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4932778537153443173740978103232404149428166901617126679386942948967712715798
    Line 1055, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 16507.953933 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:07535603
  LCV:02108421
  " == "BFV:01535603
  LCV:02108421
  "
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2641148664270507024413002506093034254672976825120121120856677366175112084042
    Line 1041, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 21927.840509 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:07535603
  LCV:21084210
  " == "BFV:01535603
  LCV:21084210
  "
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.52502701912670325265919376994988957187710005987800761139364068523455045295904
    Line 1041, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 21964.824537 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:07535603
  LCV:2318c631
  " == "BFV:01535603
  LCV:2318c631
  "
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.51878224343414233714935113372124994350802506635928923797965042861268022285395
    Line 1172, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 21508.119329 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:07535603
  LCV:25294a52
  " == "BFV:01535603
  LCV:25294a52
  "
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.62521610197727771026466605863852640111305243779497029560843401354736180628585
    Line 1042, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 21739.972203 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "BFV:07535603
  LCV:2739ce73
  " == "BFV:01535603
  LCV:2739ce73
  "
```
- ... and 10 more tests.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.107836826609085049461634134982995685871058274893609502871525695513263073866798
Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 3660.917403 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3660.917403 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.19487795474159891864084786768436454049975772429967724692803712742981779181519
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 4500.415501 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4500.415501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.8735542843315660809633332242538710575560464308875901116664763304654357009003
Line 810, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 4260.589304 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4260.589304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.91373576410873340216866155591293116918441127801504261275952230998000771415833
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 3796.015075 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3796.015075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prodend has 3 failures.

0.chip_sw_lc_walkthrough_prodend.7893551288529328196238362820319996267761439800476911352176579770748881960601
Line 853, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3603.031665 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3603.031665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prodend.11921443885717704508057375619525042446475365938336238938530943225389149186041
Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 4679.510933 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4679.510933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.109584378493623710622710265140066154376199539680479636844927358140211200353051
Line 877, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 2837.059912 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2837.059912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.59773286495752045517301871749085552489881865608801050102263679569503599085630
Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 4379.617395 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4379.617395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 9 failures:

Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock.87872086451780661760821652784447791779028659433731254882349519610486645396632
Line 819, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3141.093593 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3141.093593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock.98500058813346490662911208308513368837869837651295333848619471352402319478960
Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 4490.595734 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4490.595734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.53278764400967568802418018506125258907702192043080749113986398057674282077714
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 2830.833383 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2830.833383 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.53765042178360400360829110974741485425762319236640314835002511098465177171287
Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 4657.620109 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4657.620109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_volatile_raw_unlock has 3 failures.

0.rom_volatile_raw_unlock.51439803098263881652138617257551857337571733309063968949164064203284589505492
Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3146.956953 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3146.956953 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_volatile_raw_unlock.53407457658574389798628756830676586252933847373708871813262240012242556610272
Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3936.389367 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3936.389367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 7 failures:
- Test chip_sw_keymgr_key_derivation_prod has 2 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.20452847154024948391033780021212263757372985125474268365082801545055330622251
    Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_keymgr_key_derivation_prod.98485767746954698289941331856255212114381097993495982214676296352142995338833
    Line 786, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.200001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.78993792475220364040624817755653971595167320960732949898954124645321752419501
    Line 894, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.200001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.107698950016067368061804275392916615593043288473012945927130652336753299350640
    Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @ 10010.220001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 1.chip_sw_keymgr_key_derivation.20534959965762808480366168025630928833903488286139867923383286223099811004669
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
```
  UVM_FATAL @ 10010.260001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.
  - 2.chip_sw_keymgr_key_derivation_jitter_en.77767317266067657342561621751296001254624881836123386264876229651715852389742
    Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_rma_to_scrap.53834204606706045150773680660730426860921339400404817714324960322241312364619
Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

  UVM_FATAL @ 3912.553136 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3912.553136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_raw_to_scrap.60953683865881269964083117458537894673336049766052031206063937226021590834665
Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

  UVM_FATAL @ 4332.421254 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4332.421254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_test_locked0_to_scrap.39187859468289060697048657020472999758896838604424889519400087796434803018733
Line 819, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

  UVM_FATAL @ 4350.596696 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4350.596696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

0.chip_sw_lc_ctrl_rand_to_scrap.13617410143803057563344308626567928661572854374875839654237913341926560558883
Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3995.835644 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3995.835644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_rand_to_scrap.34808363636004474723233746711280033547028524245867811745894862029321017521047
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 4586.697557 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4586.697557 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.64359035524262506049455332900628299605780761494044797017866169435271257392301
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:f473a815-0c93-4751-b0ef-979d1536f497
```
  - 1.chip_sw_rv_timer_systick_test.92766940667045113368636840690090152881924806846804656132577617830856941362421
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:abd41c5c-4385-416f-85fc-9314b7eb47db
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.20672327897636160622618892710333679715481943682820383376078039885862301006377
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:7ed3b437-4860-4bff-b512-1cf958b4a794
```
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.53052957974160812099474922604133207983382121450160274809730585767100491302812
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:03b34d77-7aee-450b-85fe-a4fe560b7175
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 1.chip_sw_ast_clk_rst_inputs.64578291093005462044338451347649061593949086437838351645463190044708683727751
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:0fdadc5a-555f-466e-b7fa-e313ba05b7f9
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 27.chip_sw_all_escalation_resets.38451964040680063874273851852702244924461561414330759455510366284662695704579
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3519.628712 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3519.628712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.chip_sw_all_escalation_resets.108468724951611839947036032160639067302104383217369385070009947265372212526101
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2685.324988 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2685.324988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.111026188408328104140774105823627521190101552069086359774483713575786291453787
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 4272.627850 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4272.627850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.86064648533074328325256582049182608740045601312551128287049012415135204354471
    Line 812, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3899.522332 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3899.522332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.79520162650503709478116633283058629365031787035504345693471144556180770376200
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3103.626040 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 3103.626040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.70009995142388024068969099765554961436741929470300868154910363918751149667722
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3182.349872 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 3182.349872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.42268398188683739036491646136692867492409389773036655832548627540039110193208
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 3537.084402 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3537.084402 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.53008972162657501383449400896986403013399322984307298932236573798354371549919
    Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4785.301162 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4785.301162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.
  - 0.chip_sw_otp_ctrl_vendor_test_csr_access.103565861325003635450823675963963132524687897616065519385378100371233553650696
    Line 852, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 2727.798622 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2727.798622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_vendor_test_csr_access.99903138783668411916178530651047156360213156280723250953941918817752856957861
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 3263.037684 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3263.037684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 3 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.10549820496413265453312130802563212238183595727051265071704698522154079022255
    Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 3420.916619 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3420.916619 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_walkthrough_testunlocks.54507342608465904742257598510459124252099610168946367983955300332854007764082
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 4512.499720 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4512.499720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.43139839514709384400303116645811383518113053641087771546341046044585001038552
    Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.34511712439706844695495496647629612263864688273096590646376298137464871313610
    Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.85979717199414893189562848631604831549942238153973819155614082921133372217595
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14396.800184 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14396.800184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.50940327848111949121745344045650027772977416346744516810735109144185836707079
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14097.761250 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14097.761250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.58401477923768279506147629682413404241830250101906561758106820942390625590853
    Line 874, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3524.143513 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3524.143513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.104599681245211977551028644768963858799146178557919866658898975457405874481960
    Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3754.827802 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3754.827802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.27586070209773942802016564783948227194464468045434790254364745491811054717279
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1986.722500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1986.722500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.42418723926864522953095104664692153049257099782414666813608987851042610165139
    Line 730, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2318.802500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2318.802500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.52981771434002730565381013844588204883828265931318229702740030776352774975266
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2127.870000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2127.870000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.20494823769798457336133054480819169569087589748996833440702057594558407283408
    Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 57047.579685 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 57047.579685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.47949713251025879378069682360762147053365254750428852473511425273371117333456
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 57537.661925 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 57537.661925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.40653120906822576428157430707329952296529144812942195721362003858761611902059
    Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51495.992047 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51495.992047 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:
- Test rom_e2e_static_critical has 3 failures.
  - 0.rom_e2e_static_critical.73413517902084440649677253469298476445983659580539545111293631373039679996513
    Line 828, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20016.112077 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.112077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_e2e_static_critical.29207855767292631207381409540352398994690305756107593075215660548718420606765
    Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20016.372873 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.372873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.69560841070775458644615802646145586081275351556993233701218356681795685691136
Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 4856.511753 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4856.511753 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.110109505713407279742089318451300619748036148738566407361302907186291323185081
Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 3412.857254 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3412.857254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 2 failures:
- Test chip_sw_keymgr_sideload_kmac has 2 failures.
  - 0.chip_sw_keymgr_sideload_kmac.40672799530307119521662908562595117890018659830234193099552906310881991033242
    Line 951, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_keymgr_sideload_kmac.27425606922402279515323977883448984410333848943608791805819615815077963960174
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.38995360137984291943219891202771678262795981073088732201085070819540509962712
    Line 1017, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5038.977760 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5038.977760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.106011177612568271505938625899582801436365556973153749771158127986120409518405
    Line 1019, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5282.506594 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5282.506594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 1 failures:
- Test chip_sw_keymgr_sideload_aes has 1 failures.
  - 2.chip_sw_keymgr_sideload_aes.111409201874521568954205660116162317920366418618253701064650101074799834536647
    Line 748, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_FATAL @ 10010.200001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
  UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test chip_tap_straps_testunlock0 has 1 failures.
  - 2.chip_tap_straps_testunlock0.93606242151712135825721883017096520371961511742626298775004237760682997723439
    Line 5948, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_ERROR @ 4993.309532 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 4993.309532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 4.chip_csr_aliasing.74810235934495205264219180368668037219737573121920164395198594576839521856189
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:c1371e2c-8149-4717-abb3-d5e12bacf2f7
```
UVM_ERROR @ * us: (cip_base_vseq.sv:250) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 8.chip_same_csr_outstanding.74898468044660000751174499920900015059192811595011478583147668794825377248151
    Line 5463, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/8.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 25813.491861 us: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x40090078 read out mismatch
  UVM_INFO @ 25813.491861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 60.chip_sw_alert_handler_lpg_sleep_mode_alerts.94995713197299922251949207926191996167074720399812724057663614943111745259193
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4014.069544 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 4014.069544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```