Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.32	94.12	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.32	94.12	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.86	98.96	80.15	98.84		74.36	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.26	99.64	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.32	94.12	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.32	94.12	89.29	100.00		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T48,T185,T139	Yes	T48,T185,T139	INPUT
alert_req_i	Yes	Yes	T187,T303,T125	Yes	T187,T303,T114	INPUT
alert_ack_o	Yes	Yes	T187,T303,T114	Yes	T187,T303,T114	OUTPUT
alert_state_o	Yes	Yes	T187,T303,T125	Yes	T187,T303,T114	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T303,T83	Yes	T75,T303,T83	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T303,T83	Yes	T75,T303,T83	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T48,T185,T139	Yes	T48,T185,T139	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T78,T243	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T78,T243	Yes	T75,T77,T78	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	INPUT
alert_req_i	Yes	Yes	T116,T120,T121	Yes	T114,T116,T117	INPUT
alert_ack_o	Yes	Yes	T114,T116,T117	Yes	T114,T116,T117	OUTPUT
alert_state_o	Yes	Yes	T116,T120,T121	Yes	T114,T116,T117	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T83,T114	Yes	T75,T83,T114	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T83,T114	Yes	T75,T83,T114	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	INPUT
alert_req_i	Yes	Yes	T303,T125,T307	Yes	T303,T125,T304	INPUT
alert_ack_o	Yes	Yes	T303,T125,T304	Yes	T303,T125,T304	OUTPUT
alert_state_o	Yes	Yes	T303,T125,T307	Yes	T303,T125,T304	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T303,T125	Yes	T75,T303,T125	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T128,T77	Yes	T75,T128,T77	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T128,T77	Yes	T75,T128,T77	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T303,T125	Yes	T75,T303,T125	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	INPUT
alert_req_i	Yes	Yes	T402	Yes	T402	INPUT
alert_ack_o	Yes	Yes	T402	Yes	T402	OUTPUT
alert_state_o	Yes	Yes	T402	Yes	T402	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
alert_test_i	Yes	Yes	T76,T100,T101	Yes	T76,T100,T101	INPUT
alert_req_i	Yes	Yes	T187,T221,T222	Yes	T187,T221,T222	INPUT
alert_ack_o	Yes	Yes	T187,T221,T222	Yes	T187,T221,T222	OUTPUT
alert_state_o	Yes	Yes	T187,T221,T222	Yes	T187,T221,T222	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i.ack_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	INPUT
alert_rx_i.ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_rx_i.ping_p	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_tx_o.alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	OUTPUT