Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07	94.12	89.29	98.77		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	90.32	94.12	89.29	100.00		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.32	94.12	89.29	100.00		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.51	97.42	95.97	98.37		98.66	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	90.68		88.59			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	75.00			75.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.38			96.38
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.28	98.69	98.84			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T221,T222,T142
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T223,T224
1	0	Covered	T31,T4,T225

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T4,T187

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T76,T100,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T185,T139

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T4,T187
0	1	0	Covered	T221,T222,T142
1	0	0	Covered	T226,T227,T228

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T44
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T61,T229,T230	Yes	T61,T229,T230	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T46,T65,T66	Yes	T46,T65,T66	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T1,T32,T187	Yes	T1,T32,T187	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T184,T233,T234	Yes	T184,T233,T234	INPUT
irq_timer_i	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	OUTPUT
nmi_wdog_i	Yes	Yes	T238,T239,T46	Yes	T238,T239,T46	INPUT
debug_req_i	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T62,T63	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T44,T31,T32	Yes	T2,T115,T44	INPUT
edn_i.edn_fips	Yes	Yes	T157,T240,T241	Yes	T91,T157,T152	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T145,T146,T147	Yes	T145,T146,T147	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T3,T44,T95	Yes	T3,T115,T44	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T92,T115	Yes	T1,T92,T31	INPUT
icache_otp_key_i.ack	Yes	Yes	T145,T147,T148	Yes	T145,T147,T148	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T78,T243	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T75,T78,T243	Yes	T75,T77,T78	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T4,T187
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T187,T223,T224
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T44
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	381640490	8	0	0
FpvSecCmIbexFetchEnable1_A	381640490	19294921	0	60
FpvSecCmIbexFetchEnable2_A	381640490	55361199	0	70
FpvSecCmIbexFetchEnable3Rev_A	381640490	322129084	0	1794
FpvSecCmIbexFetchEnable3_A	381640490	322130754	0	1723
FpvSecCmIbexInstrIntgErrCheck_A	381640490	228	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	381640490	596	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	381640490	0	0	0
FpvSecCmIbexPcMismatchCheck_A	381640490	0	0	0
FpvSecCmIbexRfEccErrCheck_A	381640490	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	381640490	0	0	0
FpvSecCmRegWeOnehotCheck_A	381640490	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	381640490	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	381640490	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	381640490	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	905	905	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	905	905	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	381640490	123	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	381640490	192	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	8	0	0
T13	590423	0	0	0
T88	122646	0	0	0
T145	71102	0	0	0
T175	78137	0	0	0
T187	301412	1	0	0
T188	81985	0	0	0
T223	0	1	0	0
T224	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	341115	0	0	0
T250	122180	0	0	0
T251	57514	0	0	0
T252	105880	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	19294921	0	60
T1	245019	41103	0	0
T2	76918	9927	0	0
T3	241846	9931	0	0
T4	115290	10089	0	2
T31	520954	49615	0	0
T32	289301	40623	0	0
T42	0	0	0	2
T44	124916	9931	0	0
T46	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T92	148219	9931	0	0
T95	143581	9919	0	0
T97	0	0	0	2
T115	80803	9923	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T256	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	55361199	0	70
T1	245019	69554	0	0
T2	76918	34775	0	0
T3	241846	34775	0	0
T4	115290	34937	0	2
T31	520954	173891	0	0
T32	289301	69554	0	0
T42	0	0	0	2
T44	124916	34775	0	0
T46	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T92	148219	34775	0	0
T95	143581	34775	0	0
T97	0	0	0	2
T115	80803	34775	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T257	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	322129084	0	1794
T1	245019	154097	0	2
T2	76918	42078	0	2
T3	241846	207006	0	2
T4	115290	111784	0	2
T31	520954	346776	0	2
T32	289301	198860	0	2
T44	124916	121432	0	2
T92	148219	113379	0	2
T95	143581	140098	0	2
T115	80803	45974	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	322130754	0	1723
T1	245019	154099	0	2
T2	76918	42079	0	2
T3	241846	207007	0	2
T4	115290	111784	0	0
T31	520954	346780	0	2
T32	289301	198862	0	2
T44	124916	121432	0	2
T92	148219	113380	0	2
T95	143581	140098	0	2
T103	0	0	0	2
T115	80803	45975	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	228	0	0
T11	377607	0	0	0
T221	275064	76	0	0
T258	0	76	0	0
T259	0	76	0	0
T260	148548	0	0	0
T261	124711	0	0	0
T262	121185	0	0	0
T263	595292	0	0	0
T264	198975	0	0	0
T265	221875	0	0	0
T266	256747	0	0	0
T267	167412	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	596	0	0
T79	289646	0	0	0
T135	143646	0	0	0
T142	0	32	0	0
T143	0	32	0	0
T144	0	32	0	0
T182	223368	0	0	0
T222	246600	1	0	0
T223	259403	0	0	0
T268	0	31	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	0	32	0	0
T272	0	1	0	0
T273	0	100	0	0
T274	159103	0	0	0
T275	126185	0	0	0
T276	107936	0	0	0
T277	87072	0	0	0
T278	229019	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	5	0	0
T51	500784	0	0	0
T116	248878	0	0	0
T160	203912	0	0	0
T177	612068	0	0	0
T207	208776	0	0	0
T226	131646	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	345585	0	0	0
T282	675885	0	0	0
T283	387785	0	0	0
T284	224210	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	123	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	16	0	0
T147	0	36	0	0
T148	0	13	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	16	0	0
T286	0	26	0	0
T287	0	16	0	0
T288	77555	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	192	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	42	0	0
T146	0	16	0	0
T147	0	9	0	0
T148	0	3	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	42	0	0
T286	0	6	0	0
T287	0	42	0	0
T288	77555	0	0	0
T289	0	16	0	0
T290	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	80	94.12
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	0	0.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	0	1
753	1	1
754	1	1
757	1	1
760	0	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T221,T222,T142
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T223,T224
1	0	Covered	T31,T4,T225

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T4,T187

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T76,T100,T101
1	0	Covered	T1,T2,T3
1	1	Covered	T48,T185,T139

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T185,T139
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T100,T101

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T4,T187
0	1	0	Covered	T221,T222,T142
1	0	0	Covered	T226,T227,T228

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T44
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T61,T229,T230	Yes	T61,T229,T230	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T210,T211	Yes	T1,T210,T211	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T46,T65,T66	Yes	T46,T65,T66	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T231,T232,T61	Yes	T231,T232,T61	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T1,T32,T187	Yes	T1,T32,T187	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T184,T233,T234	Yes	T184,T233,T234	INPUT
irq_timer_i	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	INPUT
esc_tx_i.esc_p	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	INPUT
esc_rx_o.resp_n	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T1,T32,T103	Yes	T1,T32,T103	OUTPUT
nmi_wdog_i	Yes	Yes	T238,T239,T46	Yes	T238,T239,T46	INPUT
debug_req_i	Yes	Yes	T64,T71,T72	Yes	T64,T71,T72	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T44	Yes	T1,T2,T44	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T61,T63,T67	Yes	T61,T63,T67	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T61,*T63,*T67	Yes	T61,T62,T63	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T61,T63,T67	Yes	T61,T62,T63	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T44,T31,T32	Yes	T2,T115,T44	INPUT
edn_i.edn_fips	Yes	Yes	T157,T240,T241	Yes	T91,T157,T152	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T145,T146,T147	Yes	T145,T146,T147	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T1,T31,T32	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T3,T44,T95	Yes	T3,T115,T44	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T1,T92,T115	Yes	T1,T92,T31	INPUT
icache_otp_key_i.ack	Yes	Yes	T145,T147,T148	Yes	T145,T147,T148	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T75,T83,T77	Yes	T75,T83,T77	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T75,T77,T78	Yes	T75,T77,T78	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T75,T77,T78	Yes	T75,T78,T243	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T75,T78,T243	Yes	T75,T77,T78	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T83,T242	Yes	T75,T83,T242	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T75,T83,T48	Yes	T75,T83,T48	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T75,T187,T221	Yes	T75,T187,T221	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T4,T187
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T187,T223,T224
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T44
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	381640490	8	0	0
FpvSecCmIbexFetchEnable1_A	381640490	19294921	0	60
FpvSecCmIbexFetchEnable2_A	381640490	55361199	0	70
FpvSecCmIbexFetchEnable3Rev_A	381640490	322129084	0	1794
FpvSecCmIbexFetchEnable3_A	381640490	322130754	0	1723
FpvSecCmIbexInstrIntgErrCheck_A	381640490	228	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	381640490	596	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	381640490	0	0	0
FpvSecCmIbexPcMismatchCheck_A	381640490	0	0	0
FpvSecCmIbexRfEccErrCheck_A	381640490	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	381640490	0	0	0
FpvSecCmRegWeOnehotCheck_A	381640490	5	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	381640490	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	381640490	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	381640490	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	905	905	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	905	905	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	905	905	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	381640490	123	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	381640490	192	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	8	0	0
T13	590423	0	0	0
T88	122646	0	0	0
T145	71102	0	0	0
T175	78137	0	0	0
T187	301412	1	0	0
T188	81985	0	0	0
T223	0	1	0	0
T224	0	1	0	0
T244	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	341115	0	0	0
T250	122180	0	0	0
T251	57514	0	0	0
T252	105880	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	19294921	0	60
T1	245019	41103	0	0
T2	76918	9927	0	0
T3	241846	9931	0	0
T4	115290	10089	0	2
T31	520954	49615	0	0
T32	289301	40623	0	0
T42	0	0	0	2
T44	124916	9931	0	0
T46	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T92	148219	9931	0	0
T95	143581	9919	0	0
T97	0	0	0	2
T115	80803	9923	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T256	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	55361199	0	70
T1	245019	69554	0	0
T2	76918	34775	0	0
T3	241846	34775	0	0
T4	115290	34937	0	2
T31	520954	173891	0	0
T32	289301	69554	0	0
T42	0	0	0	2
T44	124916	34775	0	0
T46	0	0	0	2
T65	0	0	0	2
T66	0	0	0	2
T92	148219	34775	0	0
T95	143581	34775	0	0
T97	0	0	0	2
T115	80803	34775	0	0
T253	0	0	0	2
T254	0	0	0	2
T255	0	0	0	2
T257	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	322129084	0	1794
T1	245019	154097	0	2
T2	76918	42078	0	2
T3	241846	207006	0	2
T4	115290	111784	0	2
T31	520954	346776	0	2
T32	289301	198860	0	2
T44	124916	121432	0	2
T92	148219	113379	0	2
T95	143581	140098	0	2
T115	80803	45974	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	322130754	0	1723
T1	245019	154099	0	2
T2	76918	42079	0	2
T3	241846	207007	0	2
T4	115290	111784	0	0
T31	520954	346780	0	2
T32	289301	198862	0	2
T44	124916	121432	0	2
T92	148219	113380	0	2
T95	143581	140098	0	2
T103	0	0	0	2
T115	80803	45975	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	228	0	0
T11	377607	0	0	0
T221	275064	76	0	0
T258	0	76	0	0
T259	0	76	0	0
T260	148548	0	0	0
T261	124711	0	0	0
T262	121185	0	0	0
T263	595292	0	0	0
T264	198975	0	0	0
T265	221875	0	0	0
T266	256747	0	0	0
T267	167412	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	596	0	0
T79	289646	0	0	0
T135	143646	0	0	0
T142	0	32	0	0
T143	0	32	0	0
T144	0	32	0	0
T182	223368	0	0	0
T222	246600	1	0	0
T223	259403	0	0	0
T268	0	31	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	0	32	0	0
T272	0	1	0	0
T273	0	100	0	0
T274	159103	0	0	0
T275	126185	0	0	0
T276	107936	0	0	0
T277	87072	0	0	0
T278	229019	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	5	0	0
T51	500784	0	0	0
T116	248878	0	0	0
T160	203912	0	0	0
T177	612068	0	0	0
T207	208776	0	0	0
T226	131646	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T279	0	1	0	0
T280	0	1	0	0
T281	345585	0	0	0
T282	675885	0	0	0
T283	387785	0	0	0
T284	224210	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	905	905	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T44	1	1	0	0
T92	1	1	0	0
T95	1	1	0	0
T115	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	123	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	16	0	0
T147	0	36	0	0
T148	0	13	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	16	0	0
T286	0	26	0	0
T287	0	16	0	0
T288	77555	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381640490	192	0	0
T46	167250	0	0	0
T68	251068	0	0	0
T96	291514	0	0	0
T110	667584	0	0	0
T145	71102	42	0	0
T146	0	16	0	0
T147	0	9	0	0
T148	0	3	0	0
T188	81985	0	0	0
T225	221566	0	0	0
T239	145279	0	0	0
T252	105880	0	0	0
T285	0	42	0	0
T286	0	6	0	0
T287	0	42	0	0
T288	77555	0	0	0
T289	0	16	0	0
T290	0	16	0	0