Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.32 94.12 89.29 100.00 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 763280980 3976 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 763280980 3976 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 763280980 3976 0 0
T1 245019 4 0 0
T2 76918 2 0 0
T3 241846 1 0 0
T4 115290 14 0 0
T31 520954 5 0 0
T32 289301 4 0 0
T44 124916 15 0 0
T46 167250 0 0 0
T68 251068 0 0 0
T92 148219 1 0 0
T95 143581 1 0 0
T96 291514 0 0 0
T110 667584 0 0 0
T115 80803 1 0 0
T145 71102 4 0 0
T147 0 9 0 0
T148 0 3 0 0
T188 81985 0 0 0
T225 221566 0 0 0
T239 145279 0 0 0
T252 105880 0 0 0
T285 0 4 0 0
T286 0 6 0 0
T287 0 4 0 0
T288 77555 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 763280980 3976 0 0
T1 245019 4 0 0
T2 76918 2 0 0
T3 241846 1 0 0
T4 115290 14 0 0
T31 520954 5 0 0
T32 289301 4 0 0
T44 124916 15 0 0
T46 167250 0 0 0
T68 251068 0 0 0
T92 148219 1 0 0
T95 143581 1 0 0
T96 291514 0 0 0
T110 667584 0 0 0
T115 80803 1 0 0
T145 71102 4 0 0
T147 0 9 0 0
T148 0 3 0 0
T188 81985 0 0 0
T225 221566 0 0 0
T239 145279 0 0 0
T252 105880 0 0 0
T285 0 4 0 0
T286 0 6 0 0
T287 0 4 0 0
T288 77555 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 381640490 30 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 381640490 30 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 381640490 30 0 0
T46 167250 0 0 0
T68 251068 0 0 0
T96 291514 0 0 0
T110 667584 0 0 0
T145 71102 4 0 0
T147 0 9 0 0
T148 0 3 0 0
T188 81985 0 0 0
T225 221566 0 0 0
T239 145279 0 0 0
T252 105880 0 0 0
T285 0 4 0 0
T286 0 6 0 0
T287 0 4 0 0
T288 77555 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 381640490 30 0 0
T46 167250 0 0 0
T68 251068 0 0 0
T96 291514 0 0 0
T110 667584 0 0 0
T145 71102 4 0 0
T147 0 9 0 0
T148 0 3 0 0
T188 81985 0 0 0
T225 221566 0 0 0
T239 145279 0 0 0
T252 105880 0 0 0
T285 0 4 0 0
T286 0 6 0 0
T287 0 4 0 0
T288 77555 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 381640490 3946 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 381640490 3946 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 381640490 3946 0 0
T1 245019 4 0 0
T2 76918 2 0 0
T3 241846 1 0 0
T4 115290 14 0 0
T31 520954 5 0 0
T32 289301 4 0 0
T44 124916 15 0 0
T92 148219 1 0 0
T95 143581 1 0 0
T115 80803 1 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 381640490 3946 0 0
T1 245019 4 0 0
T2 76918 2 0 0
T3 241846 1 0 0
T4 115290 14 0 0
T31 520954 5 0 0
T32 289301 4 0 0
T44 124916 15 0 0
T92 148219 1 0 0
T95 143581 1 0 0
T115 80803 1 0 0

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