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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 95.29 93.66 91.79 94.46 97.38 99.57


Total test records in report: 2795
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T391 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.256857886 May 21 04:18:14 PM PDT 24 May 21 04:23:02 PM PDT 24 2807668294 ps
T204 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3217486996 May 21 04:05:56 PM PDT 24 May 21 04:31:37 PM PDT 24 8677161742 ps
T54 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.788955707 May 21 04:02:51 PM PDT 24 May 21 04:07:28 PM PDT 24 4032453150 ps
T392 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.201636179 May 21 03:54:50 PM PDT 24 May 21 04:04:03 PM PDT 24 6861140372 ps
T684 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3587397762 May 21 04:11:20 PM PDT 24 May 21 04:23:09 PM PDT 24 7186508650 ps
T685 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1501491534 May 21 04:13:33 PM PDT 24 May 21 04:24:21 PM PDT 24 4354589320 ps
T686 /workspace/coverage/default/1.rom_e2e_asm_init_prod.734936273 May 21 04:10:06 PM PDT 24 May 21 05:11:18 PM PDT 24 14134090145 ps
T687 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1428699801 May 21 04:01:14 PM PDT 24 May 21 04:42:12 PM PDT 24 27672376128 ps
T688 /workspace/coverage/default/51.chip_sw_all_escalation_resets.795145606 May 21 04:21:36 PM PDT 24 May 21 04:30:05 PM PDT 24 4311686750 ps
T689 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3650875251 May 21 04:23:30 PM PDT 24 May 21 04:29:24 PM PDT 24 3756889080 ps
T690 /workspace/coverage/default/1.chip_sw_example_concurrency.1913413704 May 21 03:58:22 PM PDT 24 May 21 04:01:58 PM PDT 24 2652186760 ps
T184 /workspace/coverage/default/0.chip_sw_power_sleep_load.1676664886 May 21 03:54:48 PM PDT 24 May 21 04:01:22 PM PDT 24 4393096600 ps
T912 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1592569629 May 21 04:10:03 PM PDT 24 May 21 05:07:25 PM PDT 24 10404170410 ps
T186 /workspace/coverage/default/4.chip_tap_straps_prod.455951548 May 21 04:15:50 PM PDT 24 May 21 04:29:08 PM PDT 24 10392056496 ps
T739 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993863237 May 21 04:21:05 PM PDT 24 May 21 04:25:28 PM PDT 24 3815407246 ps
T724 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1775877045 May 21 04:16:52 PM PDT 24 May 21 04:32:05 PM PDT 24 4909209970 ps
T913 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.511013283 May 21 03:53:32 PM PDT 24 May 21 04:05:37 PM PDT 24 7092498824 ps
T914 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.713990381 May 21 04:03:49 PM PDT 24 May 21 05:04:19 PM PDT 24 15569560370 ps
T305 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2561145544 May 21 04:03:17 PM PDT 24 May 21 04:11:22 PM PDT 24 3223607838 ps
T312 /workspace/coverage/default/1.chip_plic_all_irqs_0.453391292 May 21 04:02:58 PM PDT 24 May 21 04:23:14 PM PDT 24 6087812186 ps
T754 /workspace/coverage/default/63.chip_sw_all_escalation_resets.626096625 May 21 04:27:33 PM PDT 24 May 21 04:36:57 PM PDT 24 5520893128 ps
T130 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.927278635 May 21 04:03:05 PM PDT 24 May 21 04:10:43 PM PDT 24 7065705280 ps
T269 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1569730654 May 21 04:13:45 PM PDT 24 May 21 04:22:53 PM PDT 24 4937964294 ps
T915 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1783114246 May 21 03:57:57 PM PDT 24 May 21 04:02:15 PM PDT 24 2611495161 ps
T220 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630867366 May 21 04:20:46 PM PDT 24 May 21 04:27:17 PM PDT 24 3365004760 ps
T105 /workspace/coverage/default/2.chip_tap_straps_testunlock0.2083079870 May 21 04:12:17 PM PDT 24 May 21 04:26:39 PM PDT 24 8575156816 ps
T348 /workspace/coverage/default/0.rom_e2e_shutdown_output.3255866391 May 21 04:01:23 PM PDT 24 May 21 04:50:37 PM PDT 24 25786770362 ps
T683 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.171455370 May 21 04:11:06 PM PDT 24 May 21 04:14:55 PM PDT 24 3134540002 ps
T916 /workspace/coverage/default/0.rom_e2e_asm_init_rma.391684700 May 21 04:00:48 PM PDT 24 May 21 04:54:41 PM PDT 24 14876106435 ps
T917 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.610698447 May 21 04:07:55 PM PDT 24 May 21 04:31:03 PM PDT 24 8714734905 ps
T370 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.721525313 May 21 03:52:10 PM PDT 24 May 21 03:55:28 PM PDT 24 3426114186 ps
T227 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3338736551 May 21 04:22:56 PM PDT 24 May 21 04:30:59 PM PDT 24 5703240336 ps
T328 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.914483416 May 21 03:58:21 PM PDT 24 May 21 04:05:35 PM PDT 24 3148340730 ps
T341 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1791007258 May 21 03:55:16 PM PDT 24 May 21 04:03:44 PM PDT 24 4640774440 ps
T202 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1952992852 May 21 04:07:18 PM PDT 24 May 21 04:19:47 PM PDT 24 5012179640 ps
T241 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3044102316 May 21 03:56:51 PM PDT 24 May 21 04:30:05 PM PDT 24 10698866338 ps
T918 /workspace/coverage/default/0.rom_keymgr_functest.231011312 May 21 03:55:46 PM PDT 24 May 21 04:04:41 PM PDT 24 5041750032 ps
T919 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1052888186 May 21 04:13:47 PM PDT 24 May 21 04:25:16 PM PDT 24 5066173496 ps
T176 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3556862906 May 21 04:08:06 PM PDT 24 May 21 04:17:32 PM PDT 24 9005264257 ps
T920 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1373316555 May 21 04:09:03 PM PDT 24 May 21 04:14:41 PM PDT 24 3786793036 ps
T237 /workspace/coverage/default/1.chip_sw_rv_timer_irq.465930950 May 21 04:00:12 PM PDT 24 May 21 04:03:45 PM PDT 24 2295528130 ps
T921 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2403645357 May 21 04:13:45 PM PDT 24 May 21 04:17:49 PM PDT 24 2551479226 ps
T922 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1406790434 May 21 04:10:40 PM PDT 24 May 21 05:23:00 PM PDT 24 14335259268 ps
T770 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3659728834 May 21 04:21:34 PM PDT 24 May 21 04:32:07 PM PDT 24 6074682002 ps
T317 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2166891593 May 21 04:06:25 PM PDT 24 May 21 04:17:47 PM PDT 24 4175195800 ps
T117 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3086250892 May 21 04:16:23 PM PDT 24 May 21 04:24:04 PM PDT 24 4184024650 ps
T923 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1446101404 May 21 04:05:49 PM PDT 24 May 21 05:06:12 PM PDT 24 18026577872 ps
T146 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4233232235 May 21 04:01:19 PM PDT 24 May 21 04:15:13 PM PDT 24 8579849647 ps
T310 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4210338299 May 21 03:59:02 PM PDT 24 May 21 04:32:08 PM PDT 24 12917512408 ps
T106 /workspace/coverage/default/3.chip_tap_straps_rma.1508963089 May 21 04:15:16 PM PDT 24 May 21 04:27:23 PM PDT 24 6854085565 ps
T713 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3032503145 May 21 04:23:44 PM PDT 24 May 21 04:32:47 PM PDT 24 6047590810 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1025730685 May 21 03:52:39 PM PDT 24 May 21 04:40:44 PM PDT 24 11677076620 ps
T924 /workspace/coverage/default/2.chip_sw_example_concurrency.2086205565 May 21 04:07:30 PM PDT 24 May 21 04:11:02 PM PDT 24 3132666424 ps
T925 /workspace/coverage/default/2.chip_tap_straps_dev.3057387337 May 21 04:15:31 PM PDT 24 May 21 04:18:41 PM PDT 24 3228787113 ps
T358 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1305474588 May 21 04:08:06 PM PDT 24 May 21 05:48:33 PM PDT 24 23190379390 ps
T729 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305642969 May 21 04:24:02 PM PDT 24 May 21 04:30:29 PM PDT 24 3832076470 ps
T12 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.496777229 May 21 03:55:41 PM PDT 24 May 21 04:02:56 PM PDT 24 3966422723 ps
T740 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3257885180 May 21 04:16:50 PM PDT 24 May 21 04:28:32 PM PDT 24 4652117000 ps
T162 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2763778075 May 21 03:54:03 PM PDT 24 May 21 04:05:18 PM PDT 24 6837124840 ps
T926 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2562059391 May 21 04:11:59 PM PDT 24 May 21 04:50:04 PM PDT 24 26903647712 ps
T708 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1866165095 May 21 04:20:07 PM PDT 24 May 21 04:26:13 PM PDT 24 3866838496 ps
T751 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3805943258 May 21 04:23:47 PM PDT 24 May 21 04:32:53 PM PDT 24 5152855000 ps
T927 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1950958804 May 21 03:59:22 PM PDT 24 May 21 04:20:12 PM PDT 24 7612291304 ps
T928 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3400582448 May 21 04:13:20 PM PDT 24 May 21 04:17:40 PM PDT 24 2452587462 ps
T929 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2900053138 May 21 04:08:12 PM PDT 24 May 21 04:15:57 PM PDT 24 4379483380 ps
T270 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1113676524 May 21 04:15:25 PM PDT 24 May 21 04:18:27 PM PDT 24 2288437632 ps
T295 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3164913726 May 21 04:20:34 PM PDT 24 May 21 04:26:54 PM PDT 24 3674011526 ps
T203 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.181557964 May 21 03:58:14 PM PDT 24 May 21 04:12:53 PM PDT 24 5025569624 ps
T930 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1429655082 May 21 03:55:58 PM PDT 24 May 21 04:12:33 PM PDT 24 4868874728 ps
T82 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1118703312 May 21 04:18:34 PM PDT 24 May 21 04:29:48 PM PDT 24 6097791040 ps
T931 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3582623412 May 21 03:55:59 PM PDT 24 May 21 04:03:08 PM PDT 24 3719508380 ps
T932 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.4067894928 May 21 04:07:39 PM PDT 24 May 21 04:18:05 PM PDT 24 4157148230 ps
T933 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1121397621 May 21 04:09:22 PM PDT 24 May 21 04:18:20 PM PDT 24 5810597720 ps
T934 /workspace/coverage/default/2.chip_sw_kmac_smoketest.258165750 May 21 04:13:54 PM PDT 24 May 21 04:19:00 PM PDT 24 3355873256 ps
T935 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1821395606 May 21 03:53:02 PM PDT 24 May 21 03:58:52 PM PDT 24 3118961182 ps
T936 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.892371571 May 21 04:02:44 PM PDT 24 May 21 04:14:27 PM PDT 24 3712662902 ps
T937 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3557180811 May 21 04:19:05 PM PDT 24 May 21 05:11:46 PM PDT 24 14063833249 ps
T25 /workspace/coverage/default/2.chip_sw_gpio.1844084320 May 21 04:05:51 PM PDT 24 May 21 04:11:07 PM PDT 24 3274031072 ps
T938 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.468396528 May 21 04:06:21 PM PDT 24 May 21 04:10:15 PM PDT 24 3299579240 ps
T939 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4153923900 May 21 04:01:51 PM PDT 24 May 21 04:12:52 PM PDT 24 7810831616 ps
T717 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1147667378 May 21 04:21:14 PM PDT 24 May 21 04:28:14 PM PDT 24 3581560506 ps
T147 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.654667690 May 21 04:05:14 PM PDT 24 May 21 04:11:43 PM PDT 24 2806268072 ps
T940 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.920445484 May 21 04:12:21 PM PDT 24 May 21 04:34:05 PM PDT 24 9358669766 ps
T941 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3007367207 May 21 03:59:00 PM PDT 24 May 21 04:07:09 PM PDT 24 3704361637 ps
T942 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.553677487 May 21 04:00:03 PM PDT 24 May 21 04:13:25 PM PDT 24 5202884088 ps
T943 /workspace/coverage/default/2.chip_sw_example_flash.552975548 May 21 04:06:39 PM PDT 24 May 21 04:10:35 PM PDT 24 2859348160 ps
T111 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1903429077 May 21 03:52:30 PM PDT 24 May 21 04:00:03 PM PDT 24 2887093548 ps
T944 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3574206190 May 21 04:13:30 PM PDT 24 May 21 04:17:02 PM PDT 24 3452680975 ps
T945 /workspace/coverage/default/0.chip_sw_aes_enc.396902909 May 21 03:54:07 PM PDT 24 May 21 03:58:23 PM PDT 24 2526185988 ps
T946 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3652344635 May 21 03:57:50 PM PDT 24 May 21 04:01:24 PM PDT 24 2570457680 ps
T947 /workspace/coverage/default/0.chip_sw_aes_smoketest.1926948113 May 21 03:57:36 PM PDT 24 May 21 04:03:20 PM PDT 24 3198651518 ps
T253 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3045034727 May 21 04:05:09 PM PDT 24 May 21 05:21:10 PM PDT 24 14253878854 ps
T118 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3252747405 May 21 04:18:55 PM PDT 24 May 21 04:27:21 PM PDT 24 4216316900 ps
T948 /workspace/coverage/default/1.chip_tap_straps_dev.2564532791 May 21 04:02:26 PM PDT 24 May 21 04:29:14 PM PDT 24 11673171225 ps
T949 /workspace/coverage/default/0.chip_sw_kmac_entropy.421011226 May 21 03:53:13 PM PDT 24 May 21 03:57:18 PM PDT 24 3106860416 ps
T714 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450309856 May 21 04:23:34 PM PDT 24 May 21 04:28:00 PM PDT 24 3437810240 ps
T950 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.260332031 May 21 03:59:32 PM PDT 24 May 21 04:38:13 PM PDT 24 12863592500 ps
T254 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.4239006129 May 21 04:04:41 PM PDT 24 May 21 05:26:25 PM PDT 24 21867639960 ps
T951 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3210254700 May 21 04:17:03 PM PDT 24 May 21 04:28:09 PM PDT 24 4784696376 ps
T952 /workspace/coverage/default/1.chip_sw_aes_entropy.1779900891 May 21 04:01:13 PM PDT 24 May 21 04:05:22 PM PDT 24 3016071000 ps
T953 /workspace/coverage/default/1.chip_sw_aes_smoketest.173943624 May 21 04:04:23 PM PDT 24 May 21 04:08:36 PM PDT 24 3244715176 ps
T954 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.407512701 May 21 04:13:38 PM PDT 24 May 21 04:20:52 PM PDT 24 3229584870 ps
T955 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1215972801 May 21 04:06:10 PM PDT 24 May 21 04:10:09 PM PDT 24 3429779878 ps
T956 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3611429814 May 21 03:54:36 PM PDT 24 May 21 03:59:21 PM PDT 24 2922035712 ps
T197 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1487110513 May 21 04:08:53 PM PDT 24 May 21 04:14:42 PM PDT 24 2714143290 ps
T957 /workspace/coverage/default/0.chip_sw_kmac_idle.425432638 May 21 03:55:20 PM PDT 24 May 21 03:59:28 PM PDT 24 2223872216 ps
T359 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1668853138 May 21 04:02:58 PM PDT 24 May 21 05:25:53 PM PDT 24 22852052964 ps
T958 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3299990179 May 21 03:59:46 PM PDT 24 May 21 04:24:44 PM PDT 24 7203874514 ps
T258 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3381536733 May 21 03:59:31 PM PDT 24 May 21 04:11:29 PM PDT 24 5876692944 ps
T959 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1859711749 May 21 03:53:34 PM PDT 24 May 21 04:06:21 PM PDT 24 3973895216 ps
T334 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.143864623 May 21 04:11:08 PM PDT 24 May 21 04:21:49 PM PDT 24 4870499816 ps
T960 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3512159235 May 21 03:59:45 PM PDT 24 May 21 04:15:14 PM PDT 24 7540171995 ps
T776 /workspace/coverage/default/71.chip_sw_all_escalation_resets.4041552822 May 21 04:21:36 PM PDT 24 May 21 04:30:54 PM PDT 24 5768891816 ps
T163 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.56803806 May 21 04:15:36 PM PDT 24 May 21 04:24:30 PM PDT 24 4803388706 ps
T961 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3359442545 May 21 03:59:09 PM PDT 24 May 21 04:06:19 PM PDT 24 3965533608 ps
T344 /workspace/coverage/default/2.chip_sival_flash_info_access.3948668228 May 21 04:07:33 PM PDT 24 May 21 04:12:25 PM PDT 24 3376378840 ps
T962 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3229292694 May 21 04:10:53 PM PDT 24 May 21 04:15:36 PM PDT 24 3406000596 ps
T963 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1245341684 May 21 04:17:02 PM PDT 24 May 21 05:00:20 PM PDT 24 13051817976 ps
T964 /workspace/coverage/default/2.chip_sw_hmac_smoketest.3824619060 May 21 04:14:44 PM PDT 24 May 21 04:21:16 PM PDT 24 2945005350 ps
T965 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.4102636285 May 21 04:09:36 PM PDT 24 May 21 04:32:28 PM PDT 24 7950113292 ps
T966 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1622988219 May 21 04:15:42 PM PDT 24 May 21 04:26:14 PM PDT 24 4812702924 ps
T712 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3546746851 May 21 04:24:38 PM PDT 24 May 21 04:31:32 PM PDT 24 5261385370 ps
T967 /workspace/coverage/default/2.chip_sw_example_rom.3967927902 May 21 04:05:26 PM PDT 24 May 21 04:07:39 PM PDT 24 2109166932 ps
T148 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4103463009 May 21 04:14:04 PM PDT 24 May 21 04:17:56 PM PDT 24 2895304265 ps
T968 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1260311825 May 21 04:10:42 PM PDT 24 May 21 04:14:41 PM PDT 24 2091249400 ps
T969 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1578905839 May 21 04:00:42 PM PDT 24 May 21 04:06:20 PM PDT 24 4146924990 ps
T20 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.829312639 May 21 04:01:54 PM PDT 24 May 21 04:58:17 PM PDT 24 20654827323 ps
T970 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3775486439 May 21 04:02:06 PM PDT 24 May 21 04:53:08 PM PDT 24 12952848705 ps
T719 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3035888752 May 21 04:23:27 PM PDT 24 May 21 04:33:24 PM PDT 24 5415505302 ps
T293 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.776066102 May 21 04:10:56 PM PDT 24 May 21 04:15:47 PM PDT 24 2347037193 ps
T335 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3490706592 May 21 03:59:18 PM PDT 24 May 21 04:09:11 PM PDT 24 19143777880 ps
T764 /workspace/coverage/default/84.chip_sw_all_escalation_resets.741707404 May 21 04:23:26 PM PDT 24 May 21 04:33:15 PM PDT 24 5194635800 ps
T971 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.617344834 May 21 04:07:57 PM PDT 24 May 21 04:53:09 PM PDT 24 21280240419 ps
T972 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2823430415 May 21 04:06:43 PM PDT 24 May 21 04:17:22 PM PDT 24 4878308329 ps
T973 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2549770067 May 21 04:01:01 PM PDT 24 May 21 04:56:07 PM PDT 24 14540150974 ps
T228 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3655147862 May 21 04:22:55 PM PDT 24 May 21 04:33:35 PM PDT 24 4750758894 ps
T329 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2699663477 May 21 04:07:20 PM PDT 24 May 21 04:16:55 PM PDT 24 4165104444 ps
T974 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2976065545 May 21 04:00:29 PM PDT 24 May 21 04:16:24 PM PDT 24 7052253280 ps
T149 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.758750264 May 21 04:03:29 PM PDT 24 May 21 04:31:50 PM PDT 24 14932480219 ps
T76 /workspace/coverage/default/1.chip_sw_alert_test.522658139 May 21 04:05:42 PM PDT 24 May 21 04:10:13 PM PDT 24 3195698700 ps
T975 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1372145792 May 21 04:10:39 PM PDT 24 May 21 04:15:05 PM PDT 24 3064241330 ps
T255 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2315052649 May 21 04:02:26 PM PDT 24 May 21 04:55:34 PM PDT 24 10810375517 ps
T698 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1812136538 May 21 04:02:19 PM PDT 24 May 21 04:19:13 PM PDT 24 4707103610 ps
T26 /workspace/coverage/default/1.chip_sw_gpio.2990839124 May 21 03:58:03 PM PDT 24 May 21 04:04:58 PM PDT 24 3776969792 ps
T330 /workspace/coverage/default/0.chip_sw_pattgen_ios.2278073843 May 21 03:52:26 PM PDT 24 May 21 03:57:27 PM PDT 24 3010164648 ps
T976 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2459075814 May 21 03:59:12 PM PDT 24 May 21 04:19:06 PM PDT 24 6843219144 ps
T977 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3745000305 May 21 04:03:45 PM PDT 24 May 21 05:31:20 PM PDT 24 21645368813 ps
T289 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2221000800 May 21 04:11:27 PM PDT 24 May 21 04:28:11 PM PDT 24 9837359329 ps
T107 /workspace/coverage/default/4.chip_tap_straps_testunlock0.4182134877 May 21 04:15:40 PM PDT 24 May 21 04:29:02 PM PDT 24 9055476595 ps
T192 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3452298756 May 21 04:21:53 PM PDT 24 May 21 04:30:46 PM PDT 24 5378844072 ps
T150 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.167472813 May 21 04:18:18 PM PDT 24 May 21 05:26:20 PM PDT 24 24037196333 ps
T978 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2994351923 May 21 04:03:50 PM PDT 24 May 21 05:04:36 PM PDT 24 14041165960 ps
T979 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3676177699 May 21 04:01:04 PM PDT 24 May 21 05:12:32 PM PDT 24 14188113228 ps
T980 /workspace/coverage/default/4.chip_tap_straps_dev.267111647 May 21 04:15:04 PM PDT 24 May 21 04:18:02 PM PDT 24 2745387950 ps
T224 /workspace/coverage/default/62.chip_sw_all_escalation_resets.588203679 May 21 04:21:16 PM PDT 24 May 21 04:32:14 PM PDT 24 5711808190 ps
T981 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1150065471 May 21 03:53:12 PM PDT 24 May 21 04:00:01 PM PDT 24 4901379272 ps
T743 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3797770326 May 21 04:20:31 PM PDT 24 May 21 04:28:42 PM PDT 24 4925987268 ps
T726 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3956028475 May 21 04:22:34 PM PDT 24 May 21 04:28:30 PM PDT 24 3103583400 ps
T343 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1155506103 May 21 03:57:01 PM PDT 24 May 21 04:03:16 PM PDT 24 4392175710 ps
T982 /workspace/coverage/default/2.rom_e2e_asm_init_dev.4189544954 May 21 04:18:55 PM PDT 24 May 21 05:14:20 PM PDT 24 14147578293 ps
T709 /workspace/coverage/default/26.chip_sw_all_escalation_resets.230201105 May 21 04:21:02 PM PDT 24 May 21 04:31:09 PM PDT 24 5134964172 ps
T77 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3660197905 May 21 03:54:57 PM PDT 24 May 21 04:01:01 PM PDT 24 3783685687 ps
T733 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1949710789 May 21 04:19:54 PM PDT 24 May 21 04:26:39 PM PDT 24 3894344940 ps
T983 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3467795317 May 21 04:16:01 PM PDT 24 May 21 04:25:32 PM PDT 24 7381611050 ps
T984 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4108791665 May 21 04:19:29 PM PDT 24 May 21 05:16:56 PM PDT 24 14023282610 ps
T791 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2929547480 May 21 04:18:46 PM PDT 24 May 21 04:24:05 PM PDT 24 3152245820 ps
T985 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.362311309 May 21 04:09:06 PM PDT 24 May 21 04:12:43 PM PDT 24 2835498440 ps
T986 /workspace/coverage/default/1.chip_sw_example_manufacturer.3466526620 May 21 03:58:23 PM PDT 24 May 21 04:02:16 PM PDT 24 3112818678 ps
T987 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1256552043 May 21 04:09:07 PM PDT 24 May 21 04:20:58 PM PDT 24 4785511800 ps
T988 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1936333436 May 21 04:12:31 PM PDT 24 May 21 04:25:14 PM PDT 24 7267947840 ps
T989 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2993128970 May 21 04:14:51 PM PDT 24 May 21 04:23:25 PM PDT 24 3159549642 ps
T990 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.16408144 May 21 04:14:46 PM PDT 24 May 21 04:24:13 PM PDT 24 3591946658 ps
T774 /workspace/coverage/default/64.chip_sw_all_escalation_resets.868165320 May 21 04:22:03 PM PDT 24 May 21 04:30:13 PM PDT 24 5239448754 ps
T991 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.214575075 May 21 03:56:27 PM PDT 24 May 21 04:01:11 PM PDT 24 2692504720 ps
T992 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1412214437 May 21 04:00:30 PM PDT 24 May 21 04:11:24 PM PDT 24 8306291776 ps
T321 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4217534310 May 21 03:55:02 PM PDT 24 May 21 04:27:24 PM PDT 24 7076682568 ps
T993 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2265204561 May 21 03:59:08 PM PDT 24 May 21 04:10:35 PM PDT 24 8755680756 ps
T994 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3167389001 May 21 03:52:44 PM PDT 24 May 21 04:04:59 PM PDT 24 10218215832 ps
T766 /workspace/coverage/default/12.chip_sw_all_escalation_resets.63983307 May 21 04:18:04 PM PDT 24 May 21 04:28:51 PM PDT 24 4768483546 ps
T371 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.244755462 May 21 04:01:32 PM PDT 24 May 21 04:05:43 PM PDT 24 2973934916 ps
T995 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2932009613 May 21 04:11:04 PM PDT 24 May 21 04:17:03 PM PDT 24 2637189920 ps
T645 /workspace/coverage/default/1.chip_sw_power_idle_load.1635990518 May 21 04:03:48 PM PDT 24 May 21 04:12:57 PM PDT 24 4404002238 ps
T716 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2347281336 May 21 04:19:34 PM PDT 24 May 21 04:29:09 PM PDT 24 4966843420 ps
T996 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4082811271 May 21 04:20:58 PM PDT 24 May 21 04:27:28 PM PDT 24 3868058298 ps
T997 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3005418901 May 21 04:02:26 PM PDT 24 May 21 05:18:32 PM PDT 24 14576679152 ps
T998 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3089087761 May 21 04:03:03 PM PDT 24 May 21 04:16:27 PM PDT 24 8555987800 ps
T999 /workspace/coverage/default/0.rom_e2e_smoke.1405615386 May 21 04:01:45 PM PDT 24 May 21 04:58:29 PM PDT 24 14402145544 ps
T361 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1835239124 May 21 04:21:39 PM PDT 24 May 21 04:29:13 PM PDT 24 3242910600 ps
T1000 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.93904437 May 21 03:53:38 PM PDT 24 May 21 04:04:39 PM PDT 24 3631225288 ps
T345 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2903345306 May 21 04:07:08 PM PDT 24 May 21 04:18:06 PM PDT 24 4339209932 ps
T1001 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3247903782 May 21 04:19:06 PM PDT 24 May 21 05:13:40 PM PDT 24 14550933973 ps
T66 /workspace/coverage/default/2.chip_jtag_mem_access.2208286086 May 21 04:04:25 PM PDT 24 May 21 04:25:23 PM PDT 24 14023106151 ps
T233 /workspace/coverage/default/2.chip_sw_plic_sw_irq.4167378780 May 21 04:11:06 PM PDT 24 May 21 04:15:45 PM PDT 24 2174039474 ps
T141 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1450122507 May 21 04:01:38 PM PDT 24 May 21 04:10:44 PM PDT 24 4228024120 ps
T1002 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1199653408 May 21 04:03:01 PM PDT 24 May 21 04:11:39 PM PDT 24 3331867960 ps
T7 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3138213521 May 21 03:52:45 PM PDT 24 May 21 03:57:38 PM PDT 24 2902313220 ps
T1003 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3379595576 May 21 04:00:10 PM PDT 24 May 21 04:21:41 PM PDT 24 10311621114 ps
T1004 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2415301594 May 21 04:21:34 PM PDT 24 May 21 04:29:28 PM PDT 24 4592148616 ps
T1005 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1106263460 May 21 04:03:33 PM PDT 24 May 21 04:08:12 PM PDT 24 2529742372 ps
T306 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.877819755 May 21 04:23:26 PM PDT 24 May 21 04:30:30 PM PDT 24 3999791504 ps
T193 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.849087432 May 21 04:11:45 PM PDT 24 May 21 04:40:38 PM PDT 24 8287101456 ps
T1006 /workspace/coverage/default/1.chip_sw_uart_smoketest.363898172 May 21 04:07:35 PM PDT 24 May 21 04:12:17 PM PDT 24 3509184176 ps
T244 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3682645689 May 21 03:58:57 PM PDT 24 May 21 04:08:05 PM PDT 24 5498455654 ps
T720 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3601206943 May 21 03:51:19 PM PDT 24 May 21 04:02:55 PM PDT 24 6376514120 ps
T112 /workspace/coverage/default/0.chip_sw_usbdev_pullup.842973333 May 21 03:54:24 PM PDT 24 May 21 03:58:33 PM PDT 24 3109013638 ps
T93 /workspace/coverage/default/2.chip_sw_flash_init.2311147741 May 21 04:08:04 PM PDT 24 May 21 04:41:01 PM PDT 24 23609109784 ps
T722 /workspace/coverage/default/24.chip_sw_all_escalation_resets.1242639867 May 21 04:19:17 PM PDT 24 May 21 04:29:07 PM PDT 24 5236923332 ps
T1007 /workspace/coverage/default/0.chip_sw_csrng_smoketest.2623896296 May 21 04:01:36 PM PDT 24 May 21 04:05:46 PM PDT 24 2246889800 ps
T1008 /workspace/coverage/default/1.chip_sw_example_rom.2834383693 May 21 03:57:25 PM PDT 24 May 21 03:59:17 PM PDT 24 2186331520 ps
T1009 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1566508248 May 21 03:54:58 PM PDT 24 May 21 04:04:29 PM PDT 24 5106597352 ps
T783 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.98667452 May 21 04:23:07 PM PDT 24 May 21 04:29:01 PM PDT 24 3799262600 ps
T367 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1111790687 May 21 03:56:37 PM PDT 24 May 21 04:05:52 PM PDT 24 3996794616 ps
T322 /workspace/coverage/default/1.chip_sw_uart_tx_rx.477406401 May 21 03:59:56 PM PDT 24 May 21 04:12:25 PM PDT 24 4716438016 ps
T285 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.647928298 May 21 04:04:41 PM PDT 24 May 21 04:09:18 PM PDT 24 2150882788 ps
T383 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.162877335 May 21 04:01:39 PM PDT 24 May 21 04:12:39 PM PDT 24 9044182439 ps
T1010 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3395420733 May 21 03:54:04 PM PDT 24 May 21 04:17:53 PM PDT 24 7741417054 ps
T700 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1503381422 May 21 03:54:01 PM PDT 24 May 21 04:05:29 PM PDT 24 4682079693 ps
T1011 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3079810987 May 21 04:14:33 PM PDT 24 May 21 04:22:45 PM PDT 24 4183814240 ps
T1012 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3162237227 May 21 04:17:02 PM PDT 24 May 21 05:14:10 PM PDT 24 11052970778 ps
T1013 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1537106127 May 21 04:15:09 PM PDT 24 May 21 04:26:14 PM PDT 24 5483081780 ps
T728 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2731237060 May 21 04:28:44 PM PDT 24 May 21 04:38:12 PM PDT 24 4567439752 ps
T256 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3740491479 May 21 04:02:58 PM PDT 24 May 21 05:28:20 PM PDT 24 21456712655 ps
T1014 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.720031212 May 21 03:53:32 PM PDT 24 May 21 04:09:49 PM PDT 24 8380447940 ps
T215 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3880956394 May 21 04:10:29 PM PDT 24 May 21 05:11:48 PM PDT 24 17028688856 ps
T1015 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3380706295 May 21 03:56:48 PM PDT 24 May 21 04:02:57 PM PDT 24 4579036360 ps
T785 /workspace/coverage/default/65.chip_sw_all_escalation_resets.2102699373 May 21 04:21:49 PM PDT 24 May 21 04:30:44 PM PDT 24 4733996120 ps
T58 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3877922231 May 21 04:02:47 PM PDT 24 May 21 04:34:05 PM PDT 24 20331168536 ps
T1016 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.440062918 May 21 03:57:52 PM PDT 24 May 21 04:21:35 PM PDT 24 13990156547 ps
T1017 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.163713902 May 21 04:04:36 PM PDT 24 May 21 04:24:13 PM PDT 24 5644676186 ps
T1018 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3995157687 May 21 04:10:25 PM PDT 24 May 21 04:32:25 PM PDT 24 12465930172 ps
T1019 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1628585210 May 21 04:09:52 PM PDT 24 May 21 05:06:08 PM PDT 24 14268487827 ps
T1020 /workspace/coverage/default/2.chip_sw_aon_timer_irq.994730417 May 21 04:10:52 PM PDT 24 May 21 04:20:30 PM PDT 24 4377297816 ps
T1021 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2531870217 May 21 03:59:31 PM PDT 24 May 21 04:11:59 PM PDT 24 6103722787 ps
T1022 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615786702 May 21 04:17:26 PM PDT 24 May 21 04:27:32 PM PDT 24 4087332400 ps
T1023 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3106061623 May 21 03:59:11 PM PDT 24 May 21 04:06:23 PM PDT 24 4826031336 ps
T1024 /workspace/coverage/default/2.chip_sw_kmac_entropy.1555854390 May 21 04:09:08 PM PDT 24 May 21 04:13:32 PM PDT 24 2748367772 ps
T234 /workspace/coverage/default/2.chip_sw_power_sleep_load.3984253031 May 21 04:12:26 PM PDT 24 May 21 04:19:17 PM PDT 24 4672922336 ps
T1025 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3367165864 May 21 04:08:12 PM PDT 24 May 21 04:26:34 PM PDT 24 6376617212 ps
T1026 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.303935991 May 21 04:16:09 PM PDT 24 May 21 04:43:49 PM PDT 24 8796977160 ps
T78 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2859402170 May 21 04:12:49 PM PDT 24 May 21 04:32:56 PM PDT 24 12873271668 ps
T1027 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3404955926 May 21 04:01:59 PM PDT 24 May 21 04:09:24 PM PDT 24 4236200698 ps
T721 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2422635768 May 21 03:57:04 PM PDT 24 May 21 04:07:40 PM PDT 24 5277850206 ps
T1028 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2907337535 May 21 04:05:56 PM PDT 24 May 21 04:13:33 PM PDT 24 5963899362 ps
T1029 /workspace/coverage/default/2.chip_sw_example_manufacturer.3046799799 May 21 04:07:59 PM PDT 24 May 21 04:11:28 PM PDT 24 3044597136 ps
T1030 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1636708226 May 21 04:18:24 PM PDT 24 May 21 04:35:16 PM PDT 24 7603761895 ps
T1031 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.368804728 May 21 03:54:12 PM PDT 24 May 21 04:06:02 PM PDT 24 7017860770 ps
T736 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1845764305 May 21 04:23:50 PM PDT 24 May 21 04:35:34 PM PDT 24 5277047070 ps
T346 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.731855789 May 21 04:06:47 PM PDT 24 May 21 04:12:28 PM PDT 24 3321518563 ps
T1032 /workspace/coverage/default/0.chip_sw_aes_masking_off.4252138120 May 21 03:53:38 PM PDT 24 May 21 03:59:45 PM PDT 24 3535336985 ps
T271 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.40157434 May 21 04:02:26 PM PDT 24 May 21 04:13:05 PM PDT 24 4347120060 ps
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