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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 95.29 93.66 91.79 94.46 97.38 99.57


Total test records in report: 2795
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T164 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3630893200 May 21 04:12:37 PM PDT 24 May 21 04:23:00 PM PDT 24 5320626848 ps
T1169 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1838731796 May 21 04:09:58 PM PDT 24 May 21 04:19:34 PM PDT 24 3762333840 ps
T741 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.891699184 May 21 04:20:10 PM PDT 24 May 21 04:26:38 PM PDT 24 4031293794 ps
T194 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.4064565881 May 21 04:08:49 PM PDT 24 May 21 04:17:50 PM PDT 24 4586345880 ps
T1170 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.583894791 May 21 04:19:50 PM PDT 24 May 21 04:27:19 PM PDT 24 4341818052 ps
T673 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.293066239 May 21 03:52:47 PM PDT 24 May 21 03:58:10 PM PDT 24 3258550200 ps
T347 /workspace/coverage/default/1.chip_sw_hmac_enc.3155963147 May 21 04:01:21 PM PDT 24 May 21 04:05:23 PM PDT 24 2922659864 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1611438967 May 21 04:05:57 PM PDT 24 May 21 04:10:29 PM PDT 24 2442623065 ps
T1171 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2958326434 May 21 03:54:54 PM PDT 24 May 21 04:05:27 PM PDT 24 7545918356 ps
T1172 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2001786240 May 21 03:59:06 PM PDT 24 May 21 04:05:15 PM PDT 24 7321342264 ps
T1173 /workspace/coverage/default/3.chip_sw_uart_tx_rx.852249437 May 21 04:14:18 PM PDT 24 May 21 04:24:22 PM PDT 24 4956891504 ps
T1174 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3174383523 May 21 03:59:40 PM PDT 24 May 21 05:31:52 PM PDT 24 22562168168 ps
T219 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3834151617 May 21 04:17:32 PM PDT 24 May 21 04:47:07 PM PDT 24 25262858942 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.3114753284 May 21 03:55:35 PM PDT 24 May 21 04:03:44 PM PDT 24 4061259572 ps
T648 /workspace/coverage/default/1.chip_sw_edn_boot_mode.927137801 May 21 04:01:51 PM PDT 24 May 21 04:11:24 PM PDT 24 3165305304 ps
T1175 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2264447160 May 21 03:53:36 PM PDT 24 May 21 03:59:34 PM PDT 24 4478963472 ps
T1176 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4081238122 May 21 04:06:50 PM PDT 24 May 21 04:11:57 PM PDT 24 2821331269 ps
T323 /workspace/coverage/default/2.chip_plic_all_irqs_0.3627395911 May 21 04:11:33 PM PDT 24 May 21 04:31:49 PM PDT 24 5688124000 ps
T757 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3162495608 May 21 04:19:33 PM PDT 24 May 21 04:24:48 PM PDT 24 3631718380 ps
T1177 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.274465179 May 21 04:12:55 PM PDT 24 May 21 04:18:02 PM PDT 24 3583428678 ps
T1178 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2191197661 May 21 03:57:09 PM PDT 24 May 21 04:04:15 PM PDT 24 3813655316 ps
T782 /workspace/coverage/default/76.chip_sw_all_escalation_resets.3403536497 May 21 04:23:12 PM PDT 24 May 21 04:33:22 PM PDT 24 5340969224 ps
T1179 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4055748510 May 21 04:13:10 PM PDT 24 May 21 04:22:44 PM PDT 24 4199875194 ps
T1180 /workspace/coverage/default/0.chip_sw_edn_sw_mode.592984833 May 21 03:54:34 PM PDT 24 May 21 04:24:48 PM PDT 24 7206208098 ps
T1181 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3987484552 May 21 04:17:42 PM PDT 24 May 21 05:05:11 PM PDT 24 13005610092 ps
T1182 /workspace/coverage/default/0.chip_sw_example_rom.3765042182 May 21 03:50:42 PM PDT 24 May 21 03:52:44 PM PDT 24 2906484520 ps
T1183 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3340769125 May 21 04:16:31 PM PDT 24 May 21 04:30:42 PM PDT 24 4218475420 ps
T325 /workspace/coverage/default/2.chip_plic_all_irqs_20.3012453103 May 21 04:13:00 PM PDT 24 May 21 04:25:06 PM PDT 24 4217265038 ps
T699 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1714715173 May 21 04:10:51 PM PDT 24 May 21 04:23:36 PM PDT 24 5279715496 ps
T1184 /workspace/coverage/default/1.chip_sw_power_sleep_load.3956723118 May 21 04:03:05 PM PDT 24 May 21 04:11:43 PM PDT 24 10189097038 ps
T297 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.59097708 May 21 04:19:45 PM PDT 24 May 21 04:26:16 PM PDT 24 3837029400 ps
T294 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3876919245 May 21 03:53:48 PM PDT 24 May 21 07:25:35 PM PDT 24 255167766648 ps
T1185 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2941314176 May 21 03:52:19 PM PDT 24 May 21 03:56:48 PM PDT 24 2679084836 ps
T243 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4033805191 May 21 04:03:51 PM PDT 24 May 21 04:30:55 PM PDT 24 12025833400 ps
T750 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3895724159 May 21 04:19:47 PM PDT 24 May 21 04:26:27 PM PDT 24 2967969386 ps
T1186 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1515730286 May 21 03:53:55 PM PDT 24 May 21 04:02:29 PM PDT 24 5180133018 ps
T1187 /workspace/coverage/default/0.chip_tap_straps_prod.3917888954 May 21 03:55:30 PM PDT 24 May 21 04:20:25 PM PDT 24 11370717770 ps
T778 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2246668929 May 21 04:21:20 PM PDT 24 May 21 04:30:32 PM PDT 24 5591285000 ps
T1188 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2460620613 May 21 04:11:07 PM PDT 24 May 21 04:21:31 PM PDT 24 4235470256 ps
T1189 /workspace/coverage/default/1.chip_sw_aes_idle.932986017 May 21 03:59:41 PM PDT 24 May 21 04:04:00 PM PDT 24 2897693390 ps
T232 /workspace/coverage/default/0.chip_jtag_mem_access.139184296 May 21 03:46:24 PM PDT 24 May 21 04:09:25 PM PDT 24 13126073734 ps
T1190 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.245870374 May 21 04:05:54 PM PDT 24 May 21 04:10:45 PM PDT 24 3236604216 ps
T1191 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.324878086 May 21 03:52:25 PM PDT 24 May 21 04:24:41 PM PDT 24 8312917400 ps
T1192 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3035302464 May 21 04:00:22 PM PDT 24 May 21 04:06:16 PM PDT 24 3269682008 ps
T1193 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2625712176 May 21 04:18:24 PM PDT 24 May 21 05:04:39 PM PDT 24 14412568354 ps
T1194 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.296929342 May 21 04:03:29 PM PDT 24 May 21 04:10:06 PM PDT 24 2963933232 ps
T730 /workspace/coverage/default/61.chip_sw_all_escalation_resets.3977448186 May 21 04:21:01 PM PDT 24 May 21 04:28:44 PM PDT 24 5533517730 ps
T731 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1400257482 May 21 04:23:27 PM PDT 24 May 21 04:30:48 PM PDT 24 5068949968 ps
T755 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1609935916 May 21 04:22:29 PM PDT 24 May 21 04:29:57 PM PDT 24 3731973700 ps
T1195 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1864123132 May 21 04:01:16 PM PDT 24 May 21 04:08:33 PM PDT 24 3530666358 ps
T57 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1372930314 May 21 04:06:06 PM PDT 24 May 21 04:15:10 PM PDT 24 5483585000 ps
T121 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1882689573 May 21 04:17:22 PM PDT 24 May 21 04:27:46 PM PDT 24 5714621480 ps
T407 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2968554051 May 21 03:54:23 PM PDT 24 May 21 03:59:51 PM PDT 24 3196860654 ps
T408 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1266861387 May 21 04:06:32 PM PDT 24 May 21 04:16:35 PM PDT 24 3723794524 ps
T409 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3419541762 May 21 04:03:25 PM PDT 24 May 21 04:33:40 PM PDT 24 7839778824 ps
T410 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2673402628 May 21 04:17:04 PM PDT 24 May 21 04:27:00 PM PDT 24 4542656024 ps
T411 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.102146408 May 21 04:08:06 PM PDT 24 May 21 05:44:57 PM PDT 24 22527346580 ps
T412 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3758498962 May 21 03:54:42 PM PDT 24 May 21 04:00:47 PM PDT 24 2858336650 ps
T413 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2150392240 May 21 04:19:55 PM PDT 24 May 21 05:09:34 PM PDT 24 14690910512 ps
T414 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.954121132 May 21 04:09:17 PM PDT 24 May 21 04:29:32 PM PDT 24 5755823907 ps
T1196 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3851917472 May 21 03:51:44 PM PDT 24 May 21 07:38:28 PM PDT 24 76204461454 ps
T1197 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3120586843 May 21 04:00:18 PM PDT 24 May 21 04:13:03 PM PDT 24 3465078184 ps
T742 /workspace/coverage/default/5.chip_sw_all_escalation_resets.3669441757 May 21 04:17:04 PM PDT 24 May 21 04:28:58 PM PDT 24 4432053282 ps
T1198 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.417697995 May 21 04:14:55 PM PDT 24 May 21 04:23:39 PM PDT 24 7954832744 ps
T1199 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1848978221 May 21 03:54:19 PM PDT 24 May 21 04:11:23 PM PDT 24 4869926648 ps
T71 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.771372616 May 21 04:13:17 PM PDT 24 May 21 04:20:54 PM PDT 24 3605716916 ps
T1200 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1893642868 May 21 03:59:29 PM PDT 24 May 21 04:11:03 PM PDT 24 4128185906 ps
T1201 /workspace/coverage/default/11.chip_sw_all_escalation_resets.82233230 May 21 04:20:40 PM PDT 24 May 21 04:32:03 PM PDT 24 4470629080 ps
T1202 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.927144875 May 21 04:22:45 PM PDT 24 May 21 04:30:54 PM PDT 24 3900681126 ps
T1203 /workspace/coverage/default/1.chip_sw_aes_enc.4278558461 May 21 03:59:16 PM PDT 24 May 21 04:03:16 PM PDT 24 2799467484 ps
T746 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3481769986 May 21 04:23:41 PM PDT 24 May 21 04:33:08 PM PDT 24 5299273582 ps
T1204 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2647491215 May 21 03:53:15 PM PDT 24 May 21 04:02:14 PM PDT 24 3515451458 ps
T798 /workspace/coverage/default/39.chip_sw_all_escalation_resets.676257258 May 21 04:21:02 PM PDT 24 May 21 04:32:10 PM PDT 24 5400312674 ps
T769 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.300742343 May 21 04:22:25 PM PDT 24 May 21 04:29:14 PM PDT 24 3906094376 ps
T1205 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.119398992 May 21 03:55:32 PM PDT 24 May 21 04:12:16 PM PDT 24 7706595747 ps
T1206 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1046714284 May 21 04:21:45 PM PDT 24 May 21 04:27:13 PM PDT 24 3316142096 ps
T1207 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1610330884 May 21 03:53:38 PM PDT 24 May 21 04:12:56 PM PDT 24 9755161959 ps
T1208 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1447755567 May 21 04:11:48 PM PDT 24 May 21 04:15:16 PM PDT 24 2264441980 ps
T772 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2268062566 May 21 04:20:54 PM PDT 24 May 21 04:30:53 PM PDT 24 5963367536 ps
T1209 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2910327611 May 21 04:22:58 PM PDT 24 May 21 04:28:08 PM PDT 24 3923049936 ps
T748 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3440109763 May 21 04:19:07 PM PDT 24 May 21 04:28:52 PM PDT 24 5194192064 ps
T1210 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1708866208 May 21 04:20:20 PM PDT 24 May 21 04:39:52 PM PDT 24 7979695990 ps
T1211 /workspace/coverage/default/20.chip_sw_all_escalation_resets.3038926253 May 21 04:17:48 PM PDT 24 May 21 04:30:31 PM PDT 24 5296377272 ps
T338 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2528828756 May 21 03:59:21 PM PDT 24 May 21 04:12:14 PM PDT 24 5018212048 ps
T1212 /workspace/coverage/default/1.chip_sw_hmac_smoketest.3060428330 May 21 04:05:40 PM PDT 24 May 21 04:09:49 PM PDT 24 2814681924 ps
T102 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.26761078 May 21 03:53:17 PM PDT 24 May 21 04:02:08 PM PDT 24 5526526960 ps
T707 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1136911015 May 21 04:20:01 PM PDT 24 May 21 04:27:32 PM PDT 24 4144616744 ps
T1213 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1407638757 May 21 04:00:38 PM PDT 24 May 21 04:56:59 PM PDT 24 13648544572 ps
T744 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2111707211 May 21 04:25:40 PM PDT 24 May 21 04:37:59 PM PDT 24 4423345076 ps
T72 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2153079855 May 21 03:54:03 PM PDT 24 May 21 04:01:27 PM PDT 24 4370166448 ps
T1214 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1542393351 May 21 04:04:28 PM PDT 24 May 21 04:11:09 PM PDT 24 4907516466 ps
T1215 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4052167108 May 21 04:02:16 PM PDT 24 May 21 04:18:37 PM PDT 24 5455191404 ps
T1216 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3696457134 May 21 03:57:27 PM PDT 24 May 21 04:04:16 PM PDT 24 3290351350 ps
T1217 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3988253076 May 21 03:54:10 PM PDT 24 May 21 04:03:12 PM PDT 24 3920586734 ps
T1218 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2278500443 May 21 04:09:06 PM PDT 24 May 21 04:14:05 PM PDT 24 3339244078 ps
T1219 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1508491635 May 21 04:10:19 PM PDT 24 May 21 04:29:07 PM PDT 24 7137038825 ps
T1220 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2301621547 May 21 04:03:41 PM PDT 24 May 21 04:13:26 PM PDT 24 5139513941 ps
T1221 /workspace/coverage/default/1.chip_sw_kmac_idle.1973733715 May 21 04:00:11 PM PDT 24 May 21 04:04:55 PM PDT 24 3032093064 ps
T1222 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.562994503 May 21 04:01:43 PM PDT 24 May 21 04:20:00 PM PDT 24 5998380900 ps
T1223 /workspace/coverage/default/0.chip_sw_example_concurrency.2169430184 May 21 03:52:52 PM PDT 24 May 21 03:57:28 PM PDT 24 3260139402 ps
T1224 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.484832240 May 21 03:56:09 PM PDT 24 May 21 04:07:25 PM PDT 24 5930782150 ps
T280 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2187734843 May 21 04:28:05 PM PDT 24 May 21 04:37:22 PM PDT 24 5512992200 ps
T1225 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1009817381 May 21 03:55:16 PM PDT 24 May 21 04:00:32 PM PDT 24 3042857871 ps
T1226 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3754585766 May 21 04:01:57 PM PDT 24 May 21 04:07:10 PM PDT 24 3082413245 ps
T674 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3829684841 May 21 03:59:49 PM PDT 24 May 21 04:04:42 PM PDT 24 2498226940 ps
T1227 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.4177756092 May 21 04:09:50 PM PDT 24 May 21 04:16:16 PM PDT 24 3409894396 ps
T1228 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.161492270 May 21 04:19:28 PM PDT 24 May 21 04:24:57 PM PDT 24 3986534480 ps
T1229 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4253622187 May 21 03:55:12 PM PDT 24 May 21 03:59:13 PM PDT 24 2443675928 ps
T1230 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1522689012 May 21 03:54:19 PM PDT 24 May 21 03:58:10 PM PDT 24 2795771228 ps
T759 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2892812225 May 21 04:17:50 PM PDT 24 May 21 04:25:45 PM PDT 24 4256516760 ps
T1231 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.119171412 May 21 04:04:02 PM PDT 24 May 21 04:15:47 PM PDT 24 3756663896 ps
T1232 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2910068947 May 21 03:53:36 PM PDT 24 May 21 04:18:47 PM PDT 24 7061305386 ps
T259 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3991490995 May 21 04:17:27 PM PDT 24 May 21 04:31:43 PM PDT 24 5321908288 ps
T1233 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1457336517 May 21 04:05:10 PM PDT 24 May 21 04:55:15 PM PDT 24 10333075768 ps
T1234 /workspace/coverage/default/0.chip_sw_example_flash.3988911605 May 21 03:50:54 PM PDT 24 May 21 03:55:03 PM PDT 24 3136023374 ps
T1235 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1836431134 May 21 04:16:09 PM PDT 24 May 21 04:50:16 PM PDT 24 8331637636 ps
T1236 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3435813067 May 21 04:00:25 PM PDT 24 May 21 04:55:34 PM PDT 24 14701446856 ps
T247 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1128186636 May 21 04:08:31 PM PDT 24 May 21 04:17:27 PM PDT 24 6595611728 ps
T1237 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1398881682 May 21 04:28:19 PM PDT 24 May 21 04:40:04 PM PDT 24 4798743256 ps
T1238 /workspace/coverage/default/2.chip_sw_kmac_idle.1659224477 May 21 04:10:55 PM PDT 24 May 21 04:15:09 PM PDT 24 2611071312 ps
T38 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3537731016 May 21 04:09:20 PM PDT 24 May 21 04:18:02 PM PDT 24 6618213940 ps
T363 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.689313658 May 21 03:59:45 PM PDT 24 May 21 04:13:02 PM PDT 24 4825607036 ps
T1239 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4269959253 May 21 03:52:38 PM PDT 24 May 21 04:13:01 PM PDT 24 6159496186 ps
T248 /workspace/coverage/default/57.chip_sw_all_escalation_resets.834857818 May 21 04:21:11 PM PDT 24 May 21 04:29:46 PM PDT 24 4332430098 ps
T101 /workspace/coverage/default/2.chip_sw_alert_test.2089637823 May 21 04:10:04 PM PDT 24 May 21 04:15:37 PM PDT 24 3588171250 ps
T216 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1231578434 May 21 03:55:08 PM PDT 24 May 21 05:21:33 PM PDT 24 15119435612 ps
T1240 /workspace/coverage/default/2.rom_e2e_shutdown_output.50191543 May 21 04:18:24 PM PDT 24 May 21 05:07:50 PM PDT 24 24880055590 ps
T701 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1828340180 May 21 04:02:25 PM PDT 24 May 21 04:31:19 PM PDT 24 23959066750 ps
T1241 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3321575239 May 21 03:53:20 PM PDT 24 May 21 04:53:30 PM PDT 24 18896982315 ps
T1242 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.809661147 May 21 04:21:55 PM PDT 24 May 21 04:28:50 PM PDT 24 4006600786 ps
T1243 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1544729200 May 21 04:21:47 PM PDT 24 May 21 04:27:50 PM PDT 24 3754085352 ps
T86 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3053325900 May 21 03:53:02 PM PDT 24 May 21 04:01:27 PM PDT 24 5288242400 ps
T761 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890460665 May 21 04:22:46 PM PDT 24 May 21 04:28:56 PM PDT 24 3834721238 ps
T1244 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1108779883 May 21 04:01:42 PM PDT 24 May 21 04:13:23 PM PDT 24 4552445382 ps
T1245 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.523346244 May 21 03:54:31 PM PDT 24 May 21 04:27:20 PM PDT 24 18540206208 ps
T1246 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2627303140 May 21 04:00:35 PM PDT 24 May 21 04:08:09 PM PDT 24 3607970748 ps
T1247 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2278619309 May 21 04:18:23 PM PDT 24 May 21 04:27:41 PM PDT 24 3708856880 ps
T1248 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3348051741 May 21 04:00:04 PM PDT 24 May 21 04:03:45 PM PDT 24 2326722856 ps
T1249 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2155739097 May 21 03:53:54 PM PDT 24 May 21 04:42:56 PM PDT 24 13040438200 ps
T1250 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3542596434 May 21 04:03:50 PM PDT 24 May 21 05:07:13 PM PDT 24 14939410916 ps
T1251 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1207893014 May 21 04:09:09 PM PDT 24 May 21 04:57:34 PM PDT 24 20602865484 ps
T1252 /workspace/coverage/default/0.chip_sw_hmac_enc.1490961945 May 21 03:54:08 PM PDT 24 May 21 03:58:57 PM PDT 24 3034951480 ps
T1253 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1672296243 May 21 03:56:29 PM PDT 24 May 21 04:00:11 PM PDT 24 3950976736 ps
T732 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275805851 May 21 04:18:20 PM PDT 24 May 21 04:23:54 PM PDT 24 4347120028 ps
T1254 /workspace/coverage/default/0.chip_sival_flash_info_access.1326297286 May 21 03:52:19 PM PDT 24 May 21 03:56:47 PM PDT 24 2772443496 ps
T61 /workspace/coverage/cover_reg_top/74.xbar_error_random.4080912592 May 21 03:40:45 PM PDT 24 May 21 03:42:02 PM PDT 24 2413715367 ps
T62 /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1433385696 May 21 03:36:57 PM PDT 24 May 21 04:12:00 PM PDT 24 115248346309 ps
T63 /workspace/coverage/cover_reg_top/98.xbar_stress_all.2886722386 May 21 03:44:26 PM PDT 24 May 21 03:48:39 PM PDT 24 6983703094 ps
T67 /workspace/coverage/cover_reg_top/42.xbar_same_source.1929982374 May 21 03:35:49 PM PDT 24 May 21 03:36:58 PM PDT 24 2242913378 ps
T364 /workspace/coverage/cover_reg_top/26.chip_tl_errors.2687650992 May 21 03:33:11 PM PDT 24 May 21 03:35:39 PM PDT 24 3042413500 ps
T491 /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3124078454 May 21 03:32:34 PM PDT 24 May 21 03:32:40 PM PDT 24 40233091 ps
T229 /workspace/coverage/cover_reg_top/36.xbar_error_random.260852511 May 21 03:34:47 PM PDT 24 May 21 03:35:21 PM PDT 24 353951991 ps
T426 /workspace/coverage/cover_reg_top/63.xbar_random.2284159963 May 21 03:39:01 PM PDT 24 May 21 03:40:06 PM PDT 24 1806801535 ps
T435 /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2697047854 May 21 03:37:20 PM PDT 24 May 21 03:38:11 PM PDT 24 514218846 ps
T230 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1593965230 May 21 03:36:14 PM PDT 24 May 21 03:50:26 PM PDT 24 8408629379 ps
T488 /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.868888457 May 21 03:35:21 PM PDT 24 May 21 03:37:05 PM PDT 24 9541616891 ps
T598 /workspace/coverage/cover_reg_top/58.xbar_smoke.2861969435 May 21 03:38:15 PM PDT 24 May 21 03:38:24 PM PDT 24 157736026 ps
T486 /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3904843586 May 21 03:38:03 PM PDT 24 May 21 03:38:38 PM PDT 24 811685282 ps
T405 /workspace/coverage/cover_reg_top/48.xbar_same_source.2575872171 May 21 03:36:57 PM PDT 24 May 21 03:37:28 PM PDT 24 966466481 ps
T487 /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.4064455714 May 21 03:28:57 PM PDT 24 May 21 03:43:12 PM PDT 24 51246421684 ps
T727 /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1636332266 May 21 03:32:48 PM PDT 24 May 21 03:49:34 PM PDT 24 56326310230 ps
T490 /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.1578371502 May 21 03:39:49 PM PDT 24 May 21 03:41:12 PM PDT 24 7178869560 ps
T489 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.207501741 May 21 03:38:15 PM PDT 24 May 21 03:43:08 PM PDT 24 6986983621 ps
T403 /workspace/coverage/cover_reg_top/1.xbar_stress_all.1844574392 May 21 03:28:49 PM PDT 24 May 21 03:37:13 PM PDT 24 13289219697 ps
T406 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2803113295 May 21 03:39:05 PM PDT 24 May 21 03:53:50 PM PDT 24 8995000130 ps
T432 /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1962251398 May 21 03:42:05 PM PDT 24 May 21 03:43:45 PM PDT 24 2287661656 ps
T667 /workspace/coverage/cover_reg_top/7.xbar_access_same_device.674117746 May 21 03:29:15 PM PDT 24 May 21 03:30:07 PM PDT 24 1221289201 ps
T704 /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3438687098 May 21 03:43:43 PM PDT 24 May 21 03:44:07 PM PDT 24 568814856 ps
T585 /workspace/coverage/cover_reg_top/90.xbar_smoke.1595463384 May 21 03:43:07 PM PDT 24 May 21 03:43:18 PM PDT 24 189374500 ps
T427 /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1808240110 May 21 03:29:32 PM PDT 24 May 21 03:49:20 PM PDT 24 70877951747 ps
T666 /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1232754999 May 21 03:38:01 PM PDT 24 May 21 03:38:13 PM PDT 24 169740997 ps
T651 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1745175797 May 21 03:32:07 PM PDT 24 May 21 03:33:17 PM PDT 24 891420561 ps
T819 /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1387263375 May 21 03:38:50 PM PDT 24 May 21 03:41:10 PM PDT 24 2754528021 ps
T1255 /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3793106488 May 21 03:38:42 PM PDT 24 May 21 03:38:49 PM PDT 24 42679153 ps
T416 /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1094617810 May 21 03:34:23 PM PDT 24 May 21 03:35:46 PM PDT 24 289198724 ps
T178 /workspace/coverage/cover_reg_top/17.chip_csr_rw.3310313138 May 21 03:31:31 PM PDT 24 May 21 03:36:19 PM PDT 24 4271594746 ps
T803 /workspace/coverage/cover_reg_top/6.xbar_access_same_device.4058849378 May 21 03:29:11 PM PDT 24 May 21 03:30:25 PM PDT 24 1662774967 ps
T421 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2776553209 May 21 03:42:51 PM PDT 24 May 21 04:17:11 PM PDT 24 110096225430 ps
T599 /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.4149845349 May 21 03:42:06 PM PDT 24 May 21 03:43:46 PM PDT 24 9248729241 ps
T423 /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1126896906 May 21 03:32:03 PM PDT 24 May 21 03:48:11 PM PDT 24 86820859816 ps
T1256 /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.955178706 May 21 03:33:16 PM PDT 24 May 21 03:34:36 PM PDT 24 7990695167 ps
T559 /workspace/coverage/cover_reg_top/3.xbar_same_source.3745083932 May 21 03:28:55 PM PDT 24 May 21 03:29:13 PM PDT 24 511275850 ps
T1257 /workspace/coverage/cover_reg_top/8.xbar_smoke.4153702994 May 21 03:29:21 PM PDT 24 May 21 03:29:29 PM PDT 24 122261081 ps
T420 /workspace/coverage/cover_reg_top/58.xbar_stress_all.1793295577 May 21 03:38:23 PM PDT 24 May 21 03:43:31 PM PDT 24 3582133118 ps
T393 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3886669489 May 21 03:31:06 PM PDT 24 May 21 03:37:49 PM PDT 24 2718105115 ps
T551 /workspace/coverage/cover_reg_top/67.xbar_random.177537445 May 21 03:39:37 PM PDT 24 May 21 03:40:00 PM PDT 24 220181581 ps
T1258 /workspace/coverage/cover_reg_top/6.xbar_random.3843679404 May 21 03:29:08 PM PDT 24 May 21 03:29:19 PM PDT 24 65277497 ps
T702 /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2194329132 May 21 03:30:06 PM PDT 24 May 21 03:30:35 PM PDT 24 724164955 ps
T703 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.576452924 May 21 03:34:23 PM PDT 24 May 21 03:37:09 PM PDT 24 2745784610 ps
T584 /workspace/coverage/cover_reg_top/49.xbar_same_source.783043186 May 21 03:37:00 PM PDT 24 May 21 03:37:16 PM PDT 24 472856107 ps
T422 /workspace/coverage/cover_reg_top/81.xbar_stress_all.2351645235 May 21 03:41:49 PM PDT 24 May 21 03:54:18 PM PDT 24 18258167741 ps
T523 /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3409147382 May 21 03:29:06 PM PDT 24 May 21 03:34:32 PM PDT 24 28286860159 ps
T601 /workspace/coverage/cover_reg_top/2.xbar_smoke.236618693 May 21 03:28:51 PM PDT 24 May 21 03:28:57 PM PDT 24 42350254 ps
T1259 /workspace/coverage/cover_reg_top/50.xbar_error_random.628145842 May 21 03:37:15 PM PDT 24 May 21 03:37:22 PM PDT 24 32640533 ps
T611 /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.545324442 May 21 03:30:41 PM PDT 24 May 21 03:32:05 PM PDT 24 7532994945 ps
T582 /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1756472635 May 21 03:33:29 PM PDT 24 May 21 03:42:12 PM PDT 24 29565954911 ps
T696 /workspace/coverage/cover_reg_top/78.xbar_random.23829722 May 21 03:41:24 PM PDT 24 May 21 03:41:31 PM PDT 24 80089626 ps
T518 /workspace/coverage/cover_reg_top/91.xbar_same_source.1876342927 May 21 03:43:16 PM PDT 24 May 21 03:43:49 PM PDT 24 490465217 ps
T594 /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2855987582 May 21 03:42:36 PM PDT 24 May 21 03:42:43 PM PDT 24 43616934 ps
T1260 /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.241203002 May 21 03:43:31 PM PDT 24 May 21 03:45:23 PM PDT 24 2919358425 ps
T705 /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1095454226 May 21 03:44:09 PM PDT 24 May 21 03:44:38 PM PDT 24 695253401 ps
T825 /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.4120307981 May 21 03:36:26 PM PDT 24 May 21 03:40:45 PM PDT 24 15053910544 ps
T1261 /workspace/coverage/cover_reg_top/39.xbar_error_random.1957540680 May 21 03:35:20 PM PDT 24 May 21 03:35:44 PM PDT 24 267151530 ps
T1262 /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1578636980 May 21 03:28:50 PM PDT 24 May 21 03:29:26 PM PDT 24 394962326 ps
T485 /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1992594917 May 21 03:40:56 PM PDT 24 May 21 03:54:38 PM PDT 24 77566462665 ps
T1263 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2305963334 May 21 03:29:00 PM PDT 24 May 21 03:29:39 PM PDT 24 352807117 ps
T516 /workspace/coverage/cover_reg_top/35.xbar_stress_all.3998809955 May 21 03:34:41 PM PDT 24 May 21 03:38:04 PM PDT 24 5227910387 ps
T417 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3338624771 May 21 03:29:02 PM PDT 24 May 21 03:40:40 PM PDT 24 14115489191 ps
T602 /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.129791405 May 21 03:41:39 PM PDT 24 May 21 03:43:06 PM PDT 24 8298290178 ps
T692 /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2096144749 May 21 03:32:09 PM PDT 24 May 21 03:32:21 PM PDT 24 74385160 ps
T461 /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3292921629 May 21 03:32:04 PM PDT 24 May 21 03:32:59 PM PDT 24 499015149 ps
T1264 /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3271851325 May 21 03:31:24 PM PDT 24 May 21 03:31:37 PM PDT 24 58022653 ps
T1265 /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.605462439 May 21 03:41:38 PM PDT 24 May 21 03:41:44 PM PDT 24 44097592 ps
T404 /workspace/coverage/cover_reg_top/93.xbar_stress_all.3306093816 May 21 03:43:40 PM PDT 24 May 21 03:49:57 PM PDT 24 4238608565 ps
T554 /workspace/coverage/cover_reg_top/45.xbar_same_source.3912275376 May 21 03:36:24 PM PDT 24 May 21 03:37:11 PM PDT 24 1570665182 ps
T800 /workspace/coverage/cover_reg_top/67.xbar_access_same_device.675016891 May 21 03:39:37 PM PDT 24 May 21 03:41:51 PM PDT 24 3402014556 ps
T652 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3658140931 May 21 03:40:01 PM PDT 24 May 21 03:41:25 PM PDT 24 1233276789 ps
T838 /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.499302682 May 21 03:28:36 PM PDT 24 May 21 04:27:18 PM PDT 24 30407418180 ps
T1266 /workspace/coverage/cover_reg_top/25.xbar_same_source.2564845007 May 21 03:33:09 PM PDT 24 May 21 03:33:20 PM PDT 24 117357292 ps
T415 /workspace/coverage/cover_reg_top/12.xbar_stress_all.1076159760 May 21 03:30:25 PM PDT 24 May 21 03:39:29 PM PDT 24 14114830913 ps
T1267 /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1696743052 May 21 03:39:33 PM PDT 24 May 21 03:39:41 PM PDT 24 76118761 ps
T1268 /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.406949143 May 21 03:33:05 PM PDT 24 May 21 03:34:42 PM PDT 24 9085028120 ps
T1269 /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3081248827 May 21 03:33:22 PM PDT 24 May 21 03:33:30 PM PDT 24 46623098 ps
T799 /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.130953250 May 21 03:42:09 PM PDT 24 May 21 03:50:07 PM PDT 24 25912756845 ps
T615 /workspace/coverage/cover_reg_top/60.xbar_stress_all.3597129198 May 21 03:38:45 PM PDT 24 May 21 03:39:00 PM PDT 24 297047088 ps
T1270 /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3670117948 May 21 03:29:02 PM PDT 24 May 21 03:31:01 PM PDT 24 10544719655 ps
T1271 /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3225173294 May 21 03:42:43 PM PDT 24 May 21 03:44:10 PM PDT 24 7176199822 ps
T476 /workspace/coverage/cover_reg_top/2.xbar_random.63225872 May 21 03:28:49 PM PDT 24 May 21 03:30:04 PM PDT 24 1965921956 ps
T606 /workspace/coverage/cover_reg_top/11.xbar_smoke.2262625526 May 21 03:30:12 PM PDT 24 May 21 03:30:21 PM PDT 24 54818492 ps
T590 /workspace/coverage/cover_reg_top/17.xbar_same_source.1749265082 May 21 03:31:33 PM PDT 24 May 21 03:32:08 PM PDT 24 1029843173 ps
T549 /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3228667635 May 21 03:30:51 PM PDT 24 May 21 03:30:59 PM PDT 24 47453970 ps
T521 /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1582575708 May 21 03:39:31 PM PDT 24 May 21 03:39:38 PM PDT 24 52745247 ps
T510 /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.630610472 May 21 03:39:58 PM PDT 24 May 21 03:40:54 PM PDT 24 1386487296 ps
T447 /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3956545923 May 21 03:36:48 PM PDT 24 May 21 03:38:22 PM PDT 24 5406149560 ps
T433 /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.400213354 May 21 03:38:23 PM PDT 24 May 21 03:49:42 PM PDT 24 35499715828 ps
T494 /workspace/coverage/cover_reg_top/98.xbar_same_source.3075670832 May 21 03:44:24 PM PDT 24 May 21 03:45:07 PM PDT 24 1403368500 ps
T697 /workspace/coverage/cover_reg_top/73.xbar_smoke.3772790632 May 21 03:40:32 PM PDT 24 May 21 03:40:39 PM PDT 24 55105843 ps
T430 /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3177059690 May 21 03:34:57 PM PDT 24 May 21 04:18:18 PM PDT 24 144676083743 ps
T839 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1856212081 May 21 03:30:49 PM PDT 24 May 21 03:34:03 PM PDT 24 572475495 ps
T536 /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.2166043192 May 21 03:31:38 PM PDT 24 May 21 03:32:09 PM PDT 24 219842052 ps
T179 /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.329161734 May 21 03:29:54 PM PDT 24 May 21 04:01:05 PM PDT 24 14042875210 ps
T1272 /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2873144355 May 21 03:30:02 PM PDT 24 May 21 03:30:57 PM PDT 24 3053865311 ps
T592 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.4079791838 May 21 03:38:55 PM PDT 24 May 21 03:40:23 PM PDT 24 5323692706 ps
T463 /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.474007326 May 21 03:28:48 PM PDT 24 May 21 03:51:48 PM PDT 24 114117158663 ps
T1273 /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.3157812090 May 21 03:34:57 PM PDT 24 May 21 03:36:35 PM PDT 24 5825148756 ps
T513 /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2147681462 May 21 03:41:25 PM PDT 24 May 21 03:42:18 PM PDT 24 1378335194 ps
T623 /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1989855267 May 21 03:36:54 PM PDT 24 May 21 03:38:13 PM PDT 24 7825586904 ps
T464 /workspace/coverage/cover_reg_top/13.xbar_random.705022255 May 21 03:30:27 PM PDT 24 May 21 03:31:51 PM PDT 24 2200560134 ps
T468 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1616669611 May 21 03:33:30 PM PDT 24 May 21 03:37:58 PM PDT 24 2501358408 ps
T693 /workspace/coverage/cover_reg_top/18.xbar_same_source.3998806032 May 21 03:31:36 PM PDT 24 May 21 03:31:47 PM PDT 24 234889900 ps
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