Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.36 95.29 93.66 91.79 94.46 97.38 99.57


Total test records in report: 2795
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html
T1033 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3587150198 May 21 03:59:59 PM PDT 24 May 21 04:07:51 PM PDT 24 7011587110 ps
T94 /workspace/coverage/default/1.chip_sw_flash_init.640526433 May 21 04:00:08 PM PDT 24 May 21 04:37:08 PM PDT 24 26035517882 ps
T1034 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3382760453 May 21 04:07:08 PM PDT 24 May 21 04:19:26 PM PDT 24 4271740236 ps
T1035 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2202638540 May 21 04:04:36 PM PDT 24 May 21 04:32:53 PM PDT 24 7758959368 ps
T1036 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1996319953 May 21 04:05:21 PM PDT 24 May 21 04:10:23 PM PDT 24 2747685712 ps
T217 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4080775004 May 21 03:54:49 PM PDT 24 May 21 04:31:52 PM PDT 24 21646544882 ps
T1037 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2784087744 May 21 03:58:31 PM PDT 24 May 21 04:08:19 PM PDT 24 4240292776 ps
T789 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2854754530 May 21 04:22:48 PM PDT 24 May 21 04:31:53 PM PDT 24 6002796300 ps
T55 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2721016229 May 21 03:59:29 PM PDT 24 May 21 04:05:10 PM PDT 24 4170013792 ps
T1038 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3871197409 May 21 04:07:40 PM PDT 24 May 21 04:13:05 PM PDT 24 2628593608 ps
T1039 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2488116025 May 21 04:13:50 PM PDT 24 May 21 04:17:32 PM PDT 24 2824569080 ps
T723 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2871995230 May 21 04:22:32 PM PDT 24 May 21 04:32:19 PM PDT 24 4271569542 ps
T1040 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2435734457 May 21 04:07:27 PM PDT 24 May 21 04:27:18 PM PDT 24 8391096734 ps
T1041 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1084351544 May 21 04:18:56 PM PDT 24 May 21 05:11:48 PM PDT 24 14218030058 ps
T734 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3240789011 May 21 04:24:21 PM PDT 24 May 21 04:33:44 PM PDT 24 4846756860 ps
T85 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3124750293 May 21 04:25:40 PM PDT 24 May 21 04:39:30 PM PDT 24 5651363290 ps
T1042 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2654211830 May 21 03:58:28 PM PDT 24 May 21 04:20:50 PM PDT 24 5472317402 ps
T272 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1359894104 May 21 04:06:17 PM PDT 24 May 21 04:18:38 PM PDT 24 4555293768 ps
T1043 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1404984549 May 21 04:01:04 PM PDT 24 May 21 04:47:27 PM PDT 24 12962500118 ps
T1044 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1315321302 May 21 03:52:40 PM PDT 24 May 21 04:07:23 PM PDT 24 5392951974 ps
T735 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3665029712 May 21 04:20:39 PM PDT 24 May 21 04:25:38 PM PDT 24 3216319782 ps
T1045 /workspace/coverage/default/0.chip_sw_aes_entropy.1603764705 May 21 03:52:44 PM PDT 24 May 21 03:56:57 PM PDT 24 2912874500 ps
T1046 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2607470765 May 21 04:12:05 PM PDT 24 May 21 04:16:12 PM PDT 24 2715167988 ps
T1047 /workspace/coverage/default/2.chip_sw_uart_tx_rx.831710846 May 21 04:06:19 PM PDT 24 May 21 04:18:28 PM PDT 24 4781201500 ps
T779 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1792933182 May 21 04:19:32 PM PDT 24 May 21 04:31:32 PM PDT 24 6218356800 ps
T1048 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.99896620 May 21 04:01:53 PM PDT 24 May 21 04:07:03 PM PDT 24 2716026620 ps
T167 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.171149316 May 21 04:16:28 PM PDT 24 May 21 04:27:12 PM PDT 24 4159184178 ps
T1049 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1147438117 May 21 03:52:08 PM PDT 24 May 21 04:12:22 PM PDT 24 8195484868 ps
T1050 /workspace/coverage/default/1.chip_sw_edn_kat.2072246278 May 21 03:59:54 PM PDT 24 May 21 04:10:54 PM PDT 24 3229278150 ps
T311 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4272191761 May 21 03:54:54 PM PDT 24 May 21 04:27:58 PM PDT 24 10796676870 ps
T1051 /workspace/coverage/default/4.chip_tap_straps_rma.123106419 May 21 04:14:54 PM PDT 24 May 21 04:26:26 PM PDT 24 6388387797 ps
T214 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1650538415 May 21 04:09:59 PM PDT 24 May 21 04:37:35 PM PDT 24 10193991800 ps
T336 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3849332743 May 21 03:54:29 PM PDT 24 May 21 04:05:20 PM PDT 24 3648161128 ps
T1052 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.72963553 May 21 04:22:55 PM PDT 24 May 21 04:29:31 PM PDT 24 4171449640 ps
T1053 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3482121935 May 21 03:59:58 PM PDT 24 May 21 05:06:07 PM PDT 24 44494491844 ps
T33 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2891802527 May 21 03:59:56 PM PDT 24 May 21 04:04:17 PM PDT 24 2492917220 ps
T1054 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2328720597 May 21 04:02:58 PM PDT 24 May 21 04:06:58 PM PDT 24 3150094285 ps
T1055 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1649699175 May 21 04:06:00 PM PDT 24 May 21 04:11:11 PM PDT 24 2878362312 ps
T1056 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3212869554 May 21 03:59:03 PM PDT 24 May 21 04:03:41 PM PDT 24 2875276980 ps
T749 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1902056989 May 21 04:23:16 PM PDT 24 May 21 04:29:37 PM PDT 24 3812841428 ps
T1057 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3223554716 May 21 04:20:05 PM PDT 24 May 21 04:23:49 PM PDT 24 2655681684 ps
T1058 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2840921190 May 21 03:59:01 PM PDT 24 May 21 04:01:55 PM PDT 24 3234336456 ps
T1059 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.522810812 May 21 04:03:50 PM PDT 24 May 21 04:16:06 PM PDT 24 4996713880 ps
T1060 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2319713981 May 21 03:54:19 PM PDT 24 May 21 04:06:09 PM PDT 24 4502685944 ps
T1061 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2388451757 May 21 04:09:00 PM PDT 24 May 21 05:05:05 PM PDT 24 14402504932 ps
T1062 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2467115845 May 21 04:11:00 PM PDT 24 May 21 04:17:55 PM PDT 24 4735215770 ps
T773 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184454217 May 21 04:20:46 PM PDT 24 May 21 04:27:20 PM PDT 24 3260553444 ps
T1063 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.817072710 May 21 04:00:46 PM PDT 24 May 21 04:24:50 PM PDT 24 14105677802 ps
T1064 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1671757362 May 21 03:53:17 PM PDT 24 May 21 03:57:35 PM PDT 24 3450275068 ps
T1065 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3349001643 May 21 03:55:19 PM PDT 24 May 21 04:06:29 PM PDT 24 6524940996 ps
T34 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3447370490 May 21 04:05:36 PM PDT 24 May 21 04:08:44 PM PDT 24 2341319024 ps
T771 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998846600 May 21 04:23:18 PM PDT 24 May 21 04:29:30 PM PDT 24 3826631268 ps
T1066 /workspace/coverage/default/2.rom_keymgr_functest.423995963 May 21 04:13:48 PM PDT 24 May 21 04:24:16 PM PDT 24 4808661300 ps
T1067 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2577540270 May 21 03:53:40 PM PDT 24 May 21 04:01:04 PM PDT 24 5692185870 ps
T1068 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.227054659 May 21 04:15:43 PM PDT 24 May 21 04:18:32 PM PDT 24 2927739792 ps
T201 /workspace/coverage/default/2.chip_sw_gpio_smoketest.250570645 May 21 04:14:50 PM PDT 24 May 21 04:18:44 PM PDT 24 2459925548 ps
T313 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1450259403 May 21 03:55:50 PM PDT 24 May 21 04:05:15 PM PDT 24 4649152928 ps
T151 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3624488094 May 21 04:03:48 PM PDT 24 May 21 04:39:26 PM PDT 24 12538568985 ps
T1069 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3906060869 May 21 04:02:49 PM PDT 24 May 21 04:20:09 PM PDT 24 7748325882 ps
T1070 /workspace/coverage/default/1.chip_sw_csrng_kat_test.634042758 May 21 04:03:36 PM PDT 24 May 21 04:08:15 PM PDT 24 2730017508 ps
T654 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3746332841 May 21 04:05:11 PM PDT 24 May 21 04:15:16 PM PDT 24 5442540252 ps
T1071 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1655387663 May 21 04:01:07 PM PDT 24 May 21 04:12:05 PM PDT 24 5991446026 ps
T1072 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2298637128 May 21 04:15:04 PM PDT 24 May 21 04:38:15 PM PDT 24 9384597767 ps
T331 /workspace/coverage/default/1.chip_sw_pattgen_ios.2922037516 May 21 03:57:59 PM PDT 24 May 21 04:02:10 PM PDT 24 2765128664 ps
T425 /workspace/coverage/default/1.chip_jtag_mem_access.2002547487 May 21 03:54:34 PM PDT 24 May 21 04:19:24 PM PDT 24 13626423034 ps
T710 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1223025310 May 21 04:21:33 PM PDT 24 May 21 04:32:28 PM PDT 24 6285797200 ps
T119 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275039662 May 21 04:18:55 PM PDT 24 May 21 04:25:53 PM PDT 24 4023648430 ps
T1073 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3224486036 May 21 03:54:05 PM PDT 24 May 21 04:24:20 PM PDT 24 10760353005 ps
T1074 /workspace/coverage/default/1.chip_sw_all_escalation_resets.575312016 May 21 03:59:05 PM PDT 24 May 21 04:12:13 PM PDT 24 6013173976 ps
T318 /workspace/coverage/default/1.chip_plic_all_irqs_20.856786436 May 21 04:03:09 PM PDT 24 May 21 04:18:51 PM PDT 24 4635432438 ps
T1075 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1172598445 May 21 04:02:19 PM PDT 24 May 21 05:01:27 PM PDT 24 11795711169 ps
T643 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3110308862 May 21 03:56:59 PM PDT 24 May 21 04:14:16 PM PDT 24 4686833006 ps
T675 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3950173667 May 21 04:00:30 PM PDT 24 May 21 04:06:37 PM PDT 24 2664016734 ps
T1076 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.667932394 May 21 04:09:57 PM PDT 24 May 21 05:07:11 PM PDT 24 16811803550 ps
T1077 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2011169798 May 21 04:11:39 PM PDT 24 May 21 04:22:51 PM PDT 24 3990031672 ps
T1078 /workspace/coverage/default/1.chip_sw_aes_masking_off.1130053417 May 21 04:06:21 PM PDT 24 May 21 04:12:36 PM PDT 24 3270588055 ps
T279 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.41678948 May 21 04:21:56 PM PDT 24 May 21 04:27:12 PM PDT 24 3869094128 ps
T1079 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4247202828 May 21 04:02:32 PM PDT 24 May 21 04:19:20 PM PDT 24 7043131650 ps
T1080 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.709967165 May 21 03:59:26 PM PDT 24 May 21 04:03:37 PM PDT 24 2804146876 ps
T1081 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1684679690 May 21 04:09:56 PM PDT 24 May 21 04:15:02 PM PDT 24 3217290368 ps
T1082 /workspace/coverage/default/1.chip_sw_otbn_randomness.54808117 May 21 04:01:29 PM PDT 24 May 21 04:18:30 PM PDT 24 5582923756 ps
T286 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3799723987 May 21 03:53:38 PM PDT 24 May 21 03:58:34 PM PDT 24 3087029774 ps
T747 /workspace/coverage/default/48.chip_sw_all_escalation_resets.3038718159 May 21 04:21:40 PM PDT 24 May 21 04:32:56 PM PDT 24 4735185144 ps
T1083 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2585885341 May 21 04:05:40 PM PDT 24 May 21 05:00:48 PM PDT 24 14009900744 ps
T1084 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1855759161 May 21 04:13:26 PM PDT 24 May 21 04:27:42 PM PDT 24 5520746888 ps
T1085 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3683582616 May 21 04:12:55 PM PDT 24 May 21 07:58:20 PM PDT 24 255566051160 ps
T1086 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1293706559 May 21 03:51:53 PM PDT 24 May 21 04:47:37 PM PDT 24 12814329210 ps
T676 /workspace/coverage/default/1.chip_sw_plic_sw_irq.24961343 May 21 04:03:45 PM PDT 24 May 21 04:08:03 PM PDT 24 2747458000 ps
T1087 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.153808537 May 21 04:18:44 PM PDT 24 May 21 05:09:23 PM PDT 24 15306608724 ps
T360 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3424327679 May 21 04:06:30 PM PDT 24 May 21 04:08:52 PM PDT 24 1762523220 ps
T777 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4265217903 May 21 04:22:52 PM PDT 24 May 21 04:28:52 PM PDT 24 3370062046 ps
T1088 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.15703403 May 21 04:01:06 PM PDT 24 May 21 04:54:23 PM PDT 24 13894237985 ps
T1089 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3422556313 May 21 03:55:29 PM PDT 24 May 21 04:00:04 PM PDT 24 3661336207 ps
T1090 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2041846826 May 21 04:00:05 PM PDT 24 May 21 05:01:09 PM PDT 24 14158743766 ps
T787 /workspace/coverage/default/43.chip_sw_all_escalation_resets.906420011 May 21 04:20:47 PM PDT 24 May 21 04:30:08 PM PDT 24 5045627402 ps
T1091 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2750130245 May 21 04:11:19 PM PDT 24 May 21 04:17:18 PM PDT 24 3070704116 ps
T1092 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2884129442 May 21 04:08:45 PM PDT 24 May 21 04:18:38 PM PDT 24 6337240128 ps
T1093 /workspace/coverage/default/2.chip_sw_otbn_randomness.3424887004 May 21 04:11:13 PM PDT 24 May 21 04:27:25 PM PDT 24 5824398760 ps
T1094 /workspace/coverage/default/2.chip_sw_aes_entropy.2819737732 May 21 04:12:55 PM PDT 24 May 21 04:17:23 PM PDT 24 2915409542 ps
T1095 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1703243177 May 21 04:05:43 PM PDT 24 May 21 04:09:38 PM PDT 24 2246492432 ps
T380 /workspace/coverage/default/0.chip_sw_usbdev_stream.842721205 May 21 03:52:14 PM PDT 24 May 21 05:09:38 PM PDT 24 19225402488 ps
T655 /workspace/coverage/default/0.chip_tap_straps_dev.3016689014 May 21 03:53:27 PM PDT 24 May 21 04:24:18 PM PDT 24 15168440388 ps
T1096 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4031337713 May 21 04:09:38 PM PDT 24 May 21 04:18:31 PM PDT 24 5239370428 ps
T100 /workspace/coverage/default/0.chip_sw_alert_test.4165736821 May 21 03:53:35 PM PDT 24 May 21 03:58:27 PM PDT 24 2931375626 ps
T786 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3699273190 May 21 04:22:43 PM PDT 24 May 21 04:30:59 PM PDT 24 4579461510 ps
T737 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2107425850 May 21 04:14:34 PM PDT 24 May 21 04:24:33 PM PDT 24 5186658010 ps
T136 /workspace/coverage/default/1.chip_plic_all_irqs_10.3376422369 May 21 04:02:24 PM PDT 24 May 21 04:13:03 PM PDT 24 4219162100 ps
T40 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4060495403 May 21 03:59:00 PM PDT 24 May 21 04:04:39 PM PDT 24 3243155239 ps
T1097 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.541059679 May 21 03:55:46 PM PDT 24 May 21 04:06:20 PM PDT 24 4344966720 ps
T1098 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3812260770 May 21 04:06:57 PM PDT 24 May 21 04:23:39 PM PDT 24 6616395384 ps
T796 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3247443727 May 21 04:23:21 PM PDT 24 May 21 04:34:18 PM PDT 24 5688615748 ps
T1099 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.648209535 May 21 04:01:48 PM PDT 24 May 21 04:05:30 PM PDT 24 2008692901 ps
T1100 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2774385411 May 21 04:11:53 PM PDT 24 May 21 04:17:56 PM PDT 24 4082746274 ps
T765 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119714434 May 21 04:22:12 PM PDT 24 May 21 04:27:29 PM PDT 24 3487932484 ps
T290 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.652763408 May 21 03:53:21 PM PDT 24 May 21 04:11:41 PM PDT 24 9375101047 ps
T780 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.659098774 May 21 04:18:31 PM PDT 24 May 21 04:25:49 PM PDT 24 3290943450 ps
T131 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.4077328319 May 21 04:03:51 PM PDT 24 May 21 04:29:43 PM PDT 24 22326304972 ps
T1101 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1688677040 May 21 04:08:39 PM PDT 24 May 21 04:20:04 PM PDT 24 4588745040 ps
T762 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3583543569 May 21 04:20:14 PM PDT 24 May 21 04:26:57 PM PDT 24 3777826292 ps
T752 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1617320973 May 21 04:18:53 PM PDT 24 May 21 04:29:56 PM PDT 24 4267664000 ps
T1102 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2332161911 May 21 04:02:27 PM PDT 24 May 21 04:20:48 PM PDT 24 9726747986 ps
T307 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3261287586 May 21 04:24:45 PM PDT 24 May 21 04:34:23 PM PDT 24 4696201864 ps
T1103 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2316219707 May 21 04:06:58 PM PDT 24 May 21 04:18:52 PM PDT 24 4968280960 ps
T273 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.62675883 May 21 03:53:11 PM PDT 24 May 21 04:02:54 PM PDT 24 3490980250 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.1132381819 May 21 04:06:14 PM PDT 24 May 21 04:13:36 PM PDT 24 3590525225 ps
T1104 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3668663794 May 21 04:06:45 PM PDT 24 May 21 04:12:46 PM PDT 24 3121375192 ps
T1105 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.980287882 May 21 03:53:24 PM PDT 24 May 21 04:05:01 PM PDT 24 3993343160 ps
T1106 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1176794639 May 21 04:18:04 PM PDT 24 May 21 04:27:25 PM PDT 24 3597538500 ps
T1107 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2804681749 May 21 03:54:19 PM PDT 24 May 21 04:05:33 PM PDT 24 3827949724 ps
T1108 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.649215670 May 21 04:01:14 PM PDT 24 May 21 04:58:58 PM PDT 24 13090338912 ps
T763 /workspace/coverage/default/75.chip_sw_all_escalation_resets.667258504 May 21 04:23:20 PM PDT 24 May 21 04:33:49 PM PDT 24 5765805146 ps
T1109 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1382868801 May 21 04:17:57 PM PDT 24 May 21 04:51:58 PM PDT 24 12829814340 ps
T1110 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3357455076 May 21 04:05:38 PM PDT 24 May 21 04:08:59 PM PDT 24 2580124480 ps
T1111 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.967646771 May 21 04:00:01 PM PDT 24 May 21 04:12:26 PM PDT 24 4657474640 ps
T1112 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2682025590 May 21 03:52:34 PM PDT 24 May 21 04:08:04 PM PDT 24 6041286534 ps
T1113 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.635156723 May 21 04:02:34 PM PDT 24 May 21 05:29:17 PM PDT 24 23389040070 ps
T793 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600861087 May 21 04:23:36 PM PDT 24 May 21 04:28:22 PM PDT 24 3770964624 ps
T1114 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2614613616 May 21 03:54:52 PM PDT 24 May 21 04:02:52 PM PDT 24 3537162312 ps
T794 /workspace/coverage/default/15.chip_sw_all_escalation_resets.3301813181 May 21 04:19:51 PM PDT 24 May 21 04:31:15 PM PDT 24 4484008376 ps
T245 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2942465131 May 21 04:21:20 PM PDT 24 May 21 04:28:51 PM PDT 24 5931522740 ps
T756 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3023255753 May 21 04:16:09 PM PDT 24 May 21 04:24:48 PM PDT 24 3846769644 ps
T1115 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1243521812 May 21 04:00:09 PM PDT 24 May 21 04:07:06 PM PDT 24 4394106076 ps
T1116 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2580895728 May 21 04:00:22 PM PDT 24 May 21 04:08:43 PM PDT 24 17905963660 ps
T738 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818701916 May 21 04:22:57 PM PDT 24 May 21 04:30:11 PM PDT 24 4108723954 ps
T711 /workspace/coverage/default/80.chip_sw_all_escalation_resets.2142744697 May 21 04:21:53 PM PDT 24 May 21 04:30:40 PM PDT 24 4395916664 ps
T1117 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1511362770 May 21 04:05:40 PM PDT 24 May 21 04:10:39 PM PDT 24 3335668800 ps
T1118 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3573748443 May 21 04:03:20 PM PDT 24 May 21 04:15:13 PM PDT 24 4666222266 ps
T1119 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.376618698 May 21 04:04:01 PM PDT 24 May 21 04:15:59 PM PDT 24 5545293395 ps
T1120 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2873324472 May 21 04:15:03 PM PDT 24 May 21 04:27:43 PM PDT 24 3821437550 ps
T1121 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1216267102 May 21 04:06:41 PM PDT 24 May 21 04:10:16 PM PDT 24 2331307896 ps
T296 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2067067300 May 21 04:18:32 PM PDT 24 May 21 04:23:42 PM PDT 24 3627341256 ps
T1122 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3323327460 May 21 03:54:17 PM PDT 24 May 21 03:58:40 PM PDT 24 2721086352 ps
T1123 /workspace/coverage/default/0.chip_sw_otbn_randomness.4032858110 May 21 03:52:58 PM PDT 24 May 21 04:09:41 PM PDT 24 6370772176 ps
T35 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2998702852 May 21 03:55:19 PM PDT 24 May 21 03:59:08 PM PDT 24 2992888052 ps
T1124 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3952630554 May 21 04:06:01 PM PDT 24 May 21 04:32:24 PM PDT 24 7363145348 ps
T113 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1410255350 May 21 03:54:27 PM PDT 24 May 21 05:46:11 PM PDT 24 31322324604 ps
T1125 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3410403466 May 21 03:57:45 PM PDT 24 May 21 04:01:57 PM PDT 24 2456887760 ps
T1126 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1742834157 May 21 04:15:53 PM PDT 24 May 21 04:30:48 PM PDT 24 5171983376 ps
T644 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3728450478 May 21 04:12:49 PM PDT 24 May 21 04:22:03 PM PDT 24 2551212728 ps
T8 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.687512588 May 21 03:58:18 PM PDT 24 May 21 04:04:31 PM PDT 24 2980499912 ps
T1127 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1629709815 May 21 04:13:37 PM PDT 24 May 21 04:26:54 PM PDT 24 6345127424 ps
T1128 /workspace/coverage/default/1.rom_e2e_shutdown_output.260297864 May 21 04:10:47 PM PDT 24 May 21 04:58:13 PM PDT 24 24620573843 ps
T1129 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1261028037 May 21 03:58:21 PM PDT 24 May 21 04:07:53 PM PDT 24 3816199914 ps
T797 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1712729329 May 21 04:20:45 PM PDT 24 May 21 04:30:11 PM PDT 24 6076736840 ps
T1130 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1730514133 May 21 03:59:09 PM PDT 24 May 21 04:15:50 PM PDT 24 8268997816 ps
T1131 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.227263636 May 21 04:10:58 PM PDT 24 May 21 04:20:32 PM PDT 24 4092558380 ps
T790 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1145879312 May 21 04:24:38 PM PDT 24 May 21 04:35:20 PM PDT 24 5216432988 ps
T1132 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1339221357 May 21 04:07:39 PM PDT 24 May 21 04:19:17 PM PDT 24 4042793978 ps
T1133 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4090440667 May 21 04:07:35 PM PDT 24 May 21 04:27:46 PM PDT 24 15148424758 ps
T56 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2547554560 May 21 03:52:26 PM PDT 24 May 21 03:56:55 PM PDT 24 3377867048 ps
T319 /workspace/coverage/default/0.chip_plic_all_irqs_20.3430378318 May 21 04:00:51 PM PDT 24 May 21 04:17:45 PM PDT 24 4805084324 ps
T788 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1605630736 May 21 04:21:51 PM PDT 24 May 21 04:28:26 PM PDT 24 3127618264 ps
T1134 /workspace/coverage/default/2.chip_tap_straps_rma.1359041631 May 21 04:12:18 PM PDT 24 May 21 04:20:39 PM PDT 24 5914506545 ps
T1135 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1164941529 May 21 03:59:54 PM PDT 24 May 21 04:53:25 PM PDT 24 14315538780 ps
T205 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.822912241 May 21 03:53:32 PM PDT 24 May 21 07:00:12 PM PDT 24 63412406924 ps
T1136 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2339462413 May 21 04:09:39 PM PDT 24 May 21 04:23:10 PM PDT 24 18878740680 ps
T706 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4074454980 May 21 04:18:14 PM PDT 24 May 21 04:25:50 PM PDT 24 3328539578 ps
T1137 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4214389154 May 21 04:13:49 PM PDT 24 May 21 04:18:51 PM PDT 24 2334967656 ps
T137 /workspace/coverage/default/2.chip_plic_all_irqs_10.138112954 May 21 04:11:07 PM PDT 24 May 21 04:21:02 PM PDT 24 3513771418 ps
T231 /workspace/coverage/default/1.chip_jtag_csr_rw.1328583022 May 21 03:55:17 PM PDT 24 May 21 04:19:15 PM PDT 24 10473356232 ps
T1138 /workspace/coverage/default/1.rom_e2e_asm_init_dev.330181171 May 21 04:08:41 PM PDT 24 May 21 05:12:55 PM PDT 24 14445680442 ps
T169 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1899716447 May 21 04:07:04 PM PDT 24 May 21 04:13:31 PM PDT 24 4413478580 ps
T21 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2711775191 May 21 03:57:49 PM PDT 24 May 21 04:23:56 PM PDT 24 22693068090 ps
T767 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2797801421 May 21 04:22:04 PM PDT 24 May 21 04:29:13 PM PDT 24 4403705144 ps
T1139 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1216394709 May 21 03:58:42 PM PDT 24 May 21 04:11:01 PM PDT 24 5799127720 ps
T1140 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.271718554 May 21 04:07:05 PM PDT 24 May 21 04:26:44 PM PDT 24 6050412060 ps
T1141 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2467193786 May 21 04:01:33 PM PDT 24 May 21 04:31:00 PM PDT 24 7204020240 ps
T1142 /workspace/coverage/default/0.chip_sw_power_idle_load.4100673886 May 21 03:56:28 PM PDT 24 May 21 04:11:35 PM PDT 24 4731596368 ps
T1143 /workspace/coverage/default/1.chip_sw_flash_crash_alert.2250341086 May 21 04:04:30 PM PDT 24 May 21 04:14:15 PM PDT 24 5589950240 ps
T1144 /workspace/coverage/default/0.chip_sw_example_manufacturer.2487278275 May 21 03:51:20 PM PDT 24 May 21 03:54:58 PM PDT 24 2854817496 ps
T1145 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3317326500 May 21 04:17:22 PM PDT 24 May 21 04:28:18 PM PDT 24 3984369206 ps
T1146 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3771411480 May 21 03:54:41 PM PDT 24 May 21 04:00:14 PM PDT 24 2756054535 ps
T37 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.843654039 May 21 03:58:59 PM PDT 24 May 21 04:06:44 PM PDT 24 6372795980 ps
T1147 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.486381220 May 21 04:09:32 PM PDT 24 May 21 04:17:14 PM PDT 24 7713321654 ps
T1148 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3475109315 May 21 03:53:28 PM PDT 24 May 21 03:59:23 PM PDT 24 3034466672 ps
T792 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1461623769 May 21 04:19:54 PM PDT 24 May 21 04:29:43 PM PDT 24 4154917434 ps
T165 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.428391179 May 21 04:05:08 PM PDT 24 May 21 04:11:53 PM PDT 24 5324050198 ps
T349 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.883656521 May 21 03:59:15 PM PDT 24 May 21 07:43:27 PM PDT 24 77351405679 ps
T775 /workspace/coverage/default/95.chip_sw_all_escalation_resets.4082855303 May 21 04:23:00 PM PDT 24 May 21 04:32:35 PM PDT 24 4817754542 ps
T292 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3526152232 May 21 04:04:26 PM PDT 24 May 21 04:12:41 PM PDT 24 5596842840 ps
T172 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4267332843 May 21 03:56:12 PM PDT 24 May 21 04:39:09 PM PDT 24 19951870525 ps
T647 /workspace/coverage/default/0.chip_sw_edn_boot_mode.56929040 May 21 03:58:05 PM PDT 24 May 21 04:07:53 PM PDT 24 2583002424 ps
T208 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3888499159 May 21 03:52:13 PM PDT 24 May 21 04:50:44 PM PDT 24 20438702056 ps
T1149 /workspace/coverage/default/1.chip_sival_flash_info_access.3718197421 May 21 03:58:57 PM PDT 24 May 21 04:03:54 PM PDT 24 2909330716 ps
T1150 /workspace/coverage/default/3.chip_tap_straps_dev.4096749043 May 21 04:14:06 PM PDT 24 May 21 04:19:09 PM PDT 24 4288025242 ps
T781 /workspace/coverage/default/91.chip_sw_all_escalation_resets.1108833303 May 21 04:22:58 PM PDT 24 May 21 04:32:50 PM PDT 24 4653888330 ps
T758 /workspace/coverage/default/13.chip_sw_all_escalation_resets.457754442 May 21 04:18:23 PM PDT 24 May 21 04:29:32 PM PDT 24 5879560200 ps
T1151 /workspace/coverage/default/2.chip_sw_uart_smoketest.2850288983 May 21 04:14:01 PM PDT 24 May 21 04:18:38 PM PDT 24 2155628688 ps
T795 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3056299244 May 21 04:16:27 PM PDT 24 May 21 04:25:29 PM PDT 24 3724178446 ps
T1152 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2182690065 May 21 04:09:34 PM PDT 24 May 21 04:21:13 PM PDT 24 8535947434 ps
T138 /workspace/coverage/default/0.chip_plic_all_irqs_10.961521805 May 21 03:55:00 PM PDT 24 May 21 04:07:49 PM PDT 24 3672004560 ps
T1153 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2873638158 May 21 04:06:10 PM PDT 24 May 21 07:12:24 PM PDT 24 63008679046 ps
T1154 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2725841552 May 21 04:02:57 PM PDT 24 May 21 05:31:46 PM PDT 24 17445054049 ps
T1155 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1718319838 May 21 04:03:30 PM PDT 24 May 21 04:11:40 PM PDT 24 3429494910 ps
T784 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885380439 May 21 04:28:08 PM PDT 24 May 21 04:35:14 PM PDT 24 4110151560 ps
T760 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753571663 May 21 04:20:13 PM PDT 24 May 21 04:25:46 PM PDT 24 4121488864 ps
T1156 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1170131405 May 21 04:04:23 PM PDT 24 May 21 04:08:25 PM PDT 24 2638181684 ps
T59 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1311490120 May 21 04:16:13 PM PDT 24 May 21 04:44:07 PM PDT 24 18934571280 ps
T1157 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3242258240 May 21 04:10:04 PM PDT 24 May 21 05:20:44 PM PDT 24 18398860662 ps
T1158 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2679759523 May 21 04:08:50 PM PDT 24 May 21 04:19:01 PM PDT 24 5124958730 ps
T287 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.485732741 May 21 03:55:57 PM PDT 24 May 21 03:59:42 PM PDT 24 2514438050 ps
T246 /workspace/coverage/default/21.chip_sw_all_escalation_resets.288632786 May 21 04:18:36 PM PDT 24 May 21 04:27:02 PM PDT 24 4991314892 ps
T1159 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1267820662 May 21 04:00:08 PM PDT 24 May 21 04:04:19 PM PDT 24 2628874832 ps
T1160 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4220358537 May 21 04:13:42 PM PDT 24 May 21 04:23:32 PM PDT 24 4814570900 ps
T1161 /workspace/coverage/default/0.chip_sw_gpio_smoketest.52928085 May 21 03:56:39 PM PDT 24 May 21 04:02:35 PM PDT 24 3358089270 ps
T218 /workspace/coverage/default/0.chip_sw_flash_init.909911296 May 21 03:51:37 PM PDT 24 May 21 04:30:35 PM PDT 24 21689563416 ps
T1162 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1759518868 May 21 04:05:34 PM PDT 24 May 21 04:35:43 PM PDT 24 9038016256 ps
T1163 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1550913210 May 21 03:52:50 PM PDT 24 May 21 04:31:25 PM PDT 24 19900090214 ps
T1164 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.420474457 May 21 04:01:07 PM PDT 24 May 21 04:06:35 PM PDT 24 2320046605 ps
T1165 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1122803859 May 21 04:14:04 PM PDT 24 May 21 04:20:12 PM PDT 24 3936685120 ps
T1166 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2243012900 May 21 03:54:17 PM PDT 24 May 21 04:49:39 PM PDT 24 16543112576 ps
T384 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1043143637 May 21 04:12:06 PM PDT 24 May 21 04:21:46 PM PDT 24 9559941310 ps
T642 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3499231360 May 21 04:03:45 PM PDT 24 May 21 05:04:10 PM PDT 24 24562949749 ps
T365 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1766704677 May 21 03:56:58 PM PDT 24 May 21 04:10:05 PM PDT 24 4884016720 ps
T753 /workspace/coverage/default/59.chip_sw_all_escalation_resets.2551201893 May 21 04:21:52 PM PDT 24 May 21 04:33:41 PM PDT 24 5566125640 ps
T745 /workspace/coverage/default/47.chip_sw_all_escalation_resets.1822085923 May 21 04:20:31 PM PDT 24 May 21 04:29:08 PM PDT 24 5716828552 ps
T1167 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1918655597 May 21 03:56:11 PM PDT 24 May 21 04:00:01 PM PDT 24 2748044728 ps
T1168 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1932536605 May 21 04:10:26 PM PDT 24 May 21 04:46:31 PM PDT 24 10029140527 ps
T324 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1784484982 May 21 04:08:14 PM PDT 24 May 21 04:21:54 PM PDT 24 5013699562 ps
T120 /workspace/coverage/default/73.chip_sw_all_escalation_resets.2179330138 May 21 04:22:48 PM PDT 24 May 21 04:30:26 PM PDT 24 5099111516 ps
T60 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3063851259 May 21 03:58:04 PM PDT 24 May 21 04:05:31 PM PDT 24 5580909320 ps
T394 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3185906555 May 21 04:02:12 PM PDT 24 May 21 04:05:40 PM PDT 24 2737915832 ps
T395 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3485743095 May 21 04:08:16 PM PDT 24 May 21 04:19:24 PM PDT 24 7375410050 ps
T396 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2445038719 May 21 03:54:37 PM PDT 24 May 21 04:00:24 PM PDT 24 3533973032 ps
T397 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2107220180 May 21 04:14:45 PM PDT 24 May 21 04:26:25 PM PDT 24 3928640192 ps
T398 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2494662517 May 21 03:56:12 PM PDT 24 May 21 04:04:54 PM PDT 24 5198134014 ps
T399 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1254760471 May 21 04:10:18 PM PDT 24 May 21 04:28:44 PM PDT 24 4483172950 ps
T400 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3131076854 May 21 04:14:44 PM PDT 24 May 21 04:35:52 PM PDT 24 7965340360 ps
T401 /workspace/coverage/default/0.chip_sw_uart_smoketest.1885543536 May 21 03:57:11 PM PDT 24 May 21 04:02:11 PM PDT 24 3437319992 ps
T402 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1288079922 May 21 04:19:04 PM PDT 24 May 21 04:29:32 PM PDT 24 5224734388 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%