CHIP Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.139m	3.136ms	3	3	100.00
		chip_sw_example_rom	2.209m	2.109ms	3	3	100.00
		chip_sw_example_manufacturer	3.869m	3.113ms	3	3	100.00
		chip_sw_example_concurrency	4.588m	3.260ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.106m	5.935ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.613m	6.221ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.550h	55.617ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.593h	54.659ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.967m	3.070ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.593h	54.659ms	4	5	80.00
		chip_csr_rw	11.613m	6.221ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.490s	255.769us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.129m	4.061ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.129m	4.061ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.129m	4.061ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.461m	4.716ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.461m	4.716ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	13.162m	4.516ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.647m	3.821ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	11.623m	4.043ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	46.239m	13.006ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	55.702m	12.814ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	23.167m	9.385ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.562m	5.390ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.562m	5.390ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.214m	2.980ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	9.046m	5.484ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.522m	4.088ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.824m	15.168ms	5	5	100.00
		chip_tap_straps_testunlock0	18.313m	9.727ms	4	5	80.00
		chip_tap_straps_rma	12.095m	6.854ms	5	5	100.00
		chip_tap_straps_prod	24.891m	11.371ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.990m	3.010ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	25.673m	8.677ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.741m	5.322ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.741m	5.322ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.313m	7.748ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	42.931m	19.952ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.015m	4.467ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.642m	6.050ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.177h	18.399ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.895m	3.034ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.435m	6.474ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.672m	3.322ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	36.788m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.977m	2.637ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.867m	4.666ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.361m	3.482ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.245m	3.043ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	11.212m	6.837ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.325m	5.693ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.833m	2.347ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.325m	5.693ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.725m	2.656ms	3	3	100.00
		chip_sw_aes_smoketest	5.727m	3.199ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.005m	3.121ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.033m	2.335ms	3	3	100.00
		chip_sw_csrng_smoketest	5.183m	2.878ms	3	3	100.00
		chip_sw_entropy_src_smoketest	11.052m	4.188ms	3	3	100.00
		chip_sw_gpio_smoketest	5.920m	3.358ms	3	3	100.00
		chip_sw_hmac_smoketest	6.807m	3.290ms	3	3	100.00
		chip_sw_kmac_smoketest	5.621m	3.091ms	3	3	100.00
		chip_sw_otbn_smoketest	30.149m	9.038ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.846m	3.237ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	11.060m	5.483ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.928m	5.838ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.971m	3.336ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.147m	2.716ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.171m	2.629ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.608m	2.875ms	3	3	100.00
		chip_sw_uart_smoketest	4.987m	3.437ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.458m	4.809ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.778h	76.204ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	56.714m	14.402ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	4.040m	3.871ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	15.101m	4.732ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.609m	10.189ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	5.100m	3.021ms	0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.110h	63.412ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	10.109m	5.111ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	10.109m	5.111ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.593h	54.659ms	4	5	80.00
		chip_same_csr_outstanding	1.264h	28.277ms	20	20	100.00
		chip_csr_hw_reset	6.106m	5.935ms	5	5	100.00
		chip_csr_rw	11.613m	6.221ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.593h	54.659ms	4	5	80.00
		chip_same_csr_outstanding	1.264h	28.277ms	20	20	100.00
		chip_csr_hw_reset	6.106m	5.935ms	5	5	100.00
		chip_csr_rw	11.613m	6.221ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.607m	2.323ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.550s	52.267us	100	100	100.00
		xbar_smoke_large_delays	1.953m	10.545ms	100	100	100.00
		xbar_smoke_slow_rsp	2.097m	7.005ms	100	100	100.00
		xbar_random_zero_delays	56.750s	624.063us	100	100	100.00
		xbar_random_large_delays	22.966m	114.117ms	100	100	100.00
		xbar_random_slow_rsp	22.720m	70.452ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.075m	1.355ms	100	100	100.00
		xbar_error_and_unmapped_addr	56.020s	1.306ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.643m	2.452ms	100	100	100.00
		xbar_error_and_unmapped_addr	56.020s	1.306ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.516m	4.009ms	100	100	100.00
		xbar_access_same_device_slow_rsp	43.310m	144.676ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.524m	2.693ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.464m	18.258ms	100	100	100.00
		xbar_stress_all_with_error	12.290m	21.201ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	25.910m	13.419ms	100	100	100.00
		xbar_stress_all_with_reset_error	16.355m	10.106ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	56.714m	14.402ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	49.221m	25.787ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	56.071m	14.403ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	44.971m	10.990ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	55.120m	14.701ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	54.633m	14.198ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	53.516m	14.559ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	50.949m	14.461ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	55.505m	11.172ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.268h	14.577ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	1.056h	14.939ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.013h	14.041ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.191h	14.188ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.123h	18.169ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.445h	23.389ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.381h	22.852ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.674h	23.190ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.537h	22.562ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.480h	17.445ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.460h	21.645ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.614h	22.527ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.422h	21.457ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.362h	21.868ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	53.114m	10.810ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	52.831m	13.988ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	56.333m	13.649ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	51.014m	12.953ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	1.170h	13.479ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	50.072m	10.333ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	1.267h	14.254ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	57.710m	13.090ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	57.196m	13.292ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	1.271h	13.885ms	1	1	100.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	59.132m	11.796ms	3	3	100.00
		rom_e2e_asm_init_dev	1.070h	14.446ms	3	3	100.00
		rom_e2e_asm_init_prod	1.092h	14.197ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.205h	14.335ms	3	3	100.00
		rom_e2e_asm_init_rma	56.218m	14.268ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.008h	15.570ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.017h	14.159ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.037h	14.471ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.050h	20.015ms	0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.617m	2.871ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.895m	3.034ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.460m	2.915ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.348m	3.193ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.982m	10.010ms	2	3	66.67
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	18.879ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	18.879ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	9.607m	4.377ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	11.060m	5.483ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	9.607m	4.377ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.664m	8.269ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.664m	8.269ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.717m	7.955ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.315m	5.799ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.011m	5.583ms	3	3	100.00
		chip_sw_aes_idle	4.348m	3.193ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.884m	3.270ms	3	3	100.00
		chip_sw_kmac_idle	4.708m	3.032ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.042m	4.519ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.378m	5.531ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.955m	5.991ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	7.493m	5.220ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	31.106m	9.880ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.724m	3.465ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.352m	5.203ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.769m	3.974ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.548m	4.345ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.202m	3.828ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.793m	4.503ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.313m	7.748ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	2.825m	3.082ms	0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.769m	3.974ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.548m	4.345ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.015m	4.467ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.642m	6.050ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.177h	18.399ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.895m	3.034ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.435m	6.474ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.672m	3.322ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	36.788m	10.010ms	2	3	66.67
		chip_sw_kmac_mode_kmac_jitter_en	5.977m	2.637ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.867m	4.666ms	3	3	100.00
		chip_sw_clkmgr_jitter	5.361m	3.482ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.551m	2.727ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	11.950m	5.545ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.142m	7.094ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.074h	24.584ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.079m	2.808ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.210m	2.963ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	28.417m	10.038ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	7.220m	3.230ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.190m	5.849ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	37.040m	21.647ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.123h	24.037ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.313m	7.748ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.386m	4.657ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.605m	3.332ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	30.246m	8.258ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	32.347m	7.077ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.171m	4.788ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.262m	8.044ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.625m	2.730ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.943m	6.578ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	28.877m	23.959ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.332m	2.922ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.120s	10.400us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.616m	4.552ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	28.877m	23.959ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	28.877m	23.959ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	58.489m	20.439ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	58.489m	20.439ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.767m	5.206ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.212m	18.879ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	49.018m	13.040ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.914m	2.888ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.847m	7.950ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.914m	2.888ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	32.347m	7.077ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.561m	2.137ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.276m	21.690ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.558m	5.722ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.642m	6.050ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	11.557m	4.128ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.015m	4.467ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	8.222m	4.843ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.276m	21.690ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	5.763m	3.534ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	8.222m	4.843ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.247m	9.832ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.376m	6.159ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.249m	5.521ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	14.249m	5.521ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.797m	3.035ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.672m	3.322ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.884m	3.270ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.340m	5.800ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.628m	5.026ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.785m	4.915ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.563m	4.165ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
		chip_sw_keymgr_key_derivation_jitter_en	36.788m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	32.454m	8.145ms	2	3	66.67
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.982m	10.010ms	2	3	66.67
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.440h	15.119ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.359m	2.721ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.980m	3.071ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.977m	2.637ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.898m	2.644ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.378m	2.748ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.708m	3.032ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.831m	5.961ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.824m	15.168ms	5	5	100.00
		chip_tap_straps_rma	12.095m	6.854ms	5	5	100.00
		chip_tap_straps_prod	24.891m	11.371ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.402m	2.629ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	31.922m	10.010ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.343m	2.425ms	0	3	0.00
		chip_sw_flash_rma_unlocked	8.222m	4.843ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.822m	4.786ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.620m	8.723ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.157m	7.061ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	18.851m	6.719ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
		chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
		chip_sw_rom_ctrl_integrity_check	10.991m	9.044ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.320m	9.375ms	3	3	100.00
		chip_prim_tl_access	5.247m	9.832ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	2.825m	3.082ms	0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.724m	3.465ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.352m	5.203ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.769m	3.974ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.548m	4.345ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.202m	3.828ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.793m	4.503ms	3	3	100.00
		chip_tap_straps_dev	30.824m	15.168ms	5	5	100.00
		chip_tap_straps_rma	12.095m	6.854ms	5	5	100.00
		chip_tap_straps_prod	24.891m	11.371ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.128m	10.733ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	6.801m	4.401ms	0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	3.938m	4.527ms	0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.823m	3.332ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	4.880m	3.327ms	0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	3.303m	3.597ms	0	3	0.00
		chip_rv_dm_lc_disabled	7.128m	10.733ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	4.090m	4.205ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	3.762m	4.382ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	3.621m	4.602ms	0	3	0.00
		chip_sw_lc_walkthrough_rma	3.212m	4.352ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	3.303m	3.597ms	0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	3.990m	4.117ms	0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	3.999m	3.757ms	0	3	0.00
		rom_volatile_raw_unlock	2.655m	3.610ms	0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.276m	21.690ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.694m	3.491ms	3	3	100.00
		chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	10.629m	4.347ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.451m	2.806ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.276m	21.690ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.694m	3.491ms	3	3	100.00
		chip_sw_keymgr_key_derivation	31.047m	10.010ms	2	3	66.67
		chip_sw_sram_ctrl_scrambled_access	10.629m	4.347ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.451m	2.806ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.383m	14.553ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.402m	2.629ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.822m	4.786ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.620m	8.723ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	25.157m	7.061ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	18.851m	6.719ms	3	3	100.00
		chip_sw_lc_ctrl_transition	3.644m	4.484ms	0	15	0.00
		chip_prim_tl_access	5.247m	9.832ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.247m	9.832ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.889m	8.306ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	31.296m	20.331ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.622m	7.066ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	16.781m	7.043ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.456m	6.104ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	32.573m	23.590ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	24.049m	14.106ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.664m	8.269ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	21.976m	12.466ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.410m	4.589ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.889m	8.306ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.173m	5.125ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.102h	44.494ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.118m	7.375ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.935m	5.811ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.173m	21.280ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.943m	6.578ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	30.236m	10.760ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	40.936m	27.672ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.370m	3.259ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.991m	9.044ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.991m	9.044ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	30.236m	10.760ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.173m	21.280ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.410m	4.589ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	11.060m	5.483ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.792m	4.549ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.444m	5.772ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.525m	3.629ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	33.088m	12.918ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.168m	2.974ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.233m	7.840ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	20.250m	5.688ms	3	3	100.00
		chip_plic_all_irqs_10	12.809m	3.672ms	3	3	100.00
		chip_plic_all_irqs_20	16.870m	4.805ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.088m	2.664ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.650m	2.472ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	56.714m	14.402ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.483m	7.540ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.409m	3.730ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	8.477m	3.832ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.325m	2.493ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.629m	4.347ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.867m	4.666ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.692m	7.268ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	13.383m	8.556ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.320m	9.375ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
		chip_sw_data_integrity_escalation	12.741m	5.322ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.809m	3.119ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.098m	3.109ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.531m	2.887ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.427m	4.291ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	33.354m	7.681ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.862h	31.322ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.057m	11.677ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.536m	3.588ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.831m	5.961ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.382m	3.410ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	33.088m	12.918ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.092m	4.228ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.577m	4.087ms	85	90	94.44
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.060m	12.026ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	30.246m	8.258ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.233m	7.840ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.756h	255.566ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	38.244m	19.025ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.815m	13.626ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.792m	4.549ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.698m	5.248ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.774m	3.377ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	12.095m	6.854ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.128m	10.733ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2538	2627	96.61
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.249m	3.271ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.273m	5.257ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.166m	2.358ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.906m	1.962ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.890m	2.276ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.231h	51.095ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.123h	52.208ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.122h	56.291ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.155m	3.429ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.785m	2.583ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.418m	4.483ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	30.222m	7.206ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.596m	3.616ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	22.349m	5.472ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	6.924m	2.955ms	0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	8.406m	5.288ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.180m	5.767ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.728m	4.379ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	30.236m	10.760ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.693m	5.393ms	100	100	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.461m	4.716ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.290h	19.225ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.166m	2.358ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.906m	1.962ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.890m	2.276ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.073m	5.443ms	3	3	100.00
V3		TOTAL			29	45	64.44
	Unmapped tests	chip_sival_flash_info_access	4.922m	2.909ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.890m	4.968ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.006h	17.225ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.023m	4.870ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.890m	4.707ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.064m	6.707ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.588m	2.151ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.491m	2.932ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear	6.592m	2.964ms	3	3	100.00
		TOTAL			2795	2922	95.65

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	18	18	16	88.89
V2	281	266	234	83.27
V2S	1	1	1	100.00
V3	90	21	11	12.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.36	95.29	93.66	91.79	--	94.46	97.38	99.57

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:829) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.99261498484803214899938135922847322399285290229305610179572403209041992931230
    Line 362, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2123.284319 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2123.284319 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.48213322386291271048071851005905016260067638768680584842473185341031133705642
    Line 390, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2376.047097 us: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2376.047097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 18 failures:

Test chip_sw_lc_ctrl_transition has 15 failures.

0.chip_sw_lc_ctrl_transition.79757488228893769851694042117834933974449739904091849195373135534441278477064
Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4484.468483 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4484.468483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_transition.5937379942423228777552408214547501354357569780079302507009212932823108295525
Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_transition/latest/run.log

  UVM_FATAL @ 4706.590586 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4706.590586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test chip_sw_clkmgr_external_clk_src_for_lc has 3 failures.

0.chip_sw_clkmgr_external_clk_src_for_lc.108097895719779142629407874658121419138988446485840910545737688538837006796846
Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3082.016751 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3082.016751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_clkmgr_external_clk_src_for_lc.96475070037242269877065971739496307773688426465322983631626601014482387485754
Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_external_clk_src_for_lc/latest/run.log

  UVM_FATAL @ 3013.796520 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_transition_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3013.796520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 12 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.68660305010827845499705995970193527040206592861674756277161718239274207397599
Line 811, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 3201.899575 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3201.899575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.13220594001193702664823672318647155532319145878556203643902389236506067496230
Line 894, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_FATAL @ 4204.679898 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4204.679898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.68474980643308306211060509200431947985176507071798500614341985324023636832321
Line 816, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 4382.416075 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4382.416075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.22119999213467177314959464563886680315634747630573523906528689895742523270581
Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_FATAL @ 2730.896615 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2730.896615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prodend has 3 failures.

0.chip_sw_lc_walkthrough_prodend.43830161965583349635009801951050354577447734932174348862090876318118975787983
Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 3551.852853 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3551.852853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prodend.36979851747431713148769819057489140812662045077860042847867287911314746792054
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prodend/latest/run.log

  UVM_FATAL @ 4336.696045 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4336.696045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.51324779835216172443087952628407725101397892338398428153697373501527517742605
Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 4351.530386 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4351.530386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.56482539040941819079484931409599108272955644797868074703484746838246346115559
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_FATAL @ 3146.973493 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3146.973493 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 9 failures:

Test chip_sw_lc_ctrl_volatile_raw_unlock has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock.65150596951330131092531724723407300626016971525490952005588587046298158440018
Line 819, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3845.597397 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3845.597397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock.30387367075461510407048448676947339684500267490071768467205970932651572168667
Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 4323.444429 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4323.444429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 3 failures.

0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.108769984102557408335255753445978531663018093886585261325310251878167316120649
Line 736, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 4645.610186 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4645.610186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.69712928435389249803281265811069881878909761896752933445807477943320616371782
Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log

  UVM_FATAL @ 4636.590108 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4636.590108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test rom_volatile_raw_unlock has 3 failures.

0.rom_volatile_raw_unlock.47001518246910028593126507682341983922076105431580947956555123969395736401257
Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 2728.030933 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2728.030933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_volatile_raw_unlock.42987575948572623767333909409535444340941127874723930317151367794421341806484
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log

  UVM_FATAL @ 3609.909919 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3609.909919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.46358360518477660227320220863088725350461201640286380168818243627714422647308
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:dba93df4-179f-4896-8b78-35f5a8647bcd
```
  - 1.chip_sw_rv_timer_systick_test.99910099731918367403849403837794080620319064218824421005599498472043657469622
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:6708ade0-d3cc-48b3-ac70-23ba001695bc
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.69737170492474821333075735080570576128170868773639010971428675115848544044289
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:ffb4e14b-db62-4384-80c2-6789a86a3772
```
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.50659468423681292809653985343693159245591491958177146422791908218336393981275
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:732dcfb4-61ec-446f-95ed-665db20c8778
```
  - 2.chip_sw_power_virus.41034083805625959550646954251301064041158774096018103232986314556012657198208
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:edf0bcb7-7068-4567-ba35-35767c346e94
```
- Test chip_sw_uart_tx_rx_bootstrap has 1 failures.
  - 2.chip_sw_uart_tx_rx_bootstrap.13336304373898283980953037674008943558298359986442654654162433213547823833994
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:003091f6-fcd3-4f6e-8eb2-70e6e9edaf7a
```
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 2.chip_sw_ast_clk_rst_inputs.25547210814566232643245086856158229051327177215271828635662914893750861512526
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:730b1e0e-9d77-459c-929c-7882baf69251
```

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 6 failures:

Test chip_sw_lc_ctrl_rma_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_rma_to_scrap.56463032803177420877752137226336897298479481203893889542795396424862591034778
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rma_to_scrap/latest/run.log

  UVM_FATAL @ 4400.666701 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4400.666701 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_raw_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_raw_to_scrap.24422855016993243898490430129464368951659782570547045261952613378649595728221
Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log

  UVM_FATAL @ 4526.511068 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4526.511068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.

0.chip_sw_lc_ctrl_test_locked0_to_scrap.84229786313162309411635657477150210278174779803613406545625325667766779241607
Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log

  UVM_FATAL @ 3332.054000 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3332.054000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_lc_ctrl_rand_to_scrap has 3 failures.

0.chip_sw_lc_ctrl_rand_to_scrap.101177640125395712473351206656038461122247603590609071730517264114343288540171
Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3250.891823 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3250.891823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_ctrl_rand_to_scrap.110376863903272103420471134575399802997271370394184127262939248991497210050025
Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log

  UVM_FATAL @ 3327.019331 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3327.019331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 5 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 5 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.83656302546142471418661052821087547177447804798417935172818421851695340184791
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3655.681936 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3655.681936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.chip_sw_alert_handler_lpg_sleep_mode_alerts.39417307432221291174463604086857560886932567487295231035758103252985386604606
    Line 824, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3410.158480 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 3410.158480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_key_derivation_vseq] wait timeout occurred! has 5 failures:
- Test chip_sw_keymgr_key_derivation_prod has 3 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.108386903652395016262823198814319318319261150952359921009673966383407007926740
    Line 830, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.360001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_prod.96301052018933942039513274155368672684010496333574251904484490801005286399071
    Line 832, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 1.chip_sw_keymgr_key_derivation.37542707902859864873875587823034390019411437827801788514869242857203124601979
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en has 1 failures.
  - 1.chip_sw_keymgr_key_derivation_jitter_en.817864086410221602658391855963344723568303056139896501487594735228714005451
    Line 804, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_key_derivation_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.25169270411592906646097335019191346205668284166976785557865901843095169397598
    Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3800.901043 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3800.901043 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.42378587138531252612631428774932544387047811443858754912134196288913305071181
    Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  UVM_FATAL @ 3582.980690 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_exit_test_unlocked_bootstrap_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3582.980690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns * has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.102435581646624286761457924779924285753811374771235777811542926755932060146608
    Line 847, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2425.443158 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2425.443158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.113513666925368465327787384742811869963069923347719805189955169791082455625024
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2307.436072 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/tests/sim_dv/flash_ctrl_lc_rw_en_test.c:101)] DIF-fail: dif_keymgr_advance_state(keymgr, params) returns 3
  UVM_INFO @ 2307.436072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_flash_rma_unlocked_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.6307264009441881081270091503738088324486366800993612494919915966595753151280
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4842.514187 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4842.514187 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.17640036616948113726225983529671754869808322576015395121174631298577831433258
    Line 743, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 4281.218405 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4281.218405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_otp_ctrl_vendor_test_csr_access has 3 failures.
  - 0.chip_sw_otp_ctrl_vendor_test_csr_access.71731815424432226201479477338467482636455701352829213584462364803451947163697
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 2954.818125 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2954.818125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_vendor_test_csr_access.7352256063368928086473120084955632169754977040354154363886389929565976470002
    Line 749, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest/run.log
```
  UVM_FATAL @ 3446.815565 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_vendor_test_csr_access_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3446.815565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:
- Test chip_sw_lc_walkthrough_testunlocks has 3 failures.
  - 0.chip_sw_lc_walkthrough_testunlocks.32133790222714010921491436659376136115908582588319766966080895997051216582949
    Line 846, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 2885.897693 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 2885.897693 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_lc_walkthrough_testunlocks.96501434163598331671416728120948575132869789809090489245194099472537206878917
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log
```
  UVM_FATAL @ 4327.528144 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_walkthrough_testunlocks_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4327.528144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.14714772538233150672227037166426002903943167671667862631201395711910280979598
    Line 861, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.69253772864132877630543871481954051917226071743743800172269149973456213951390
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.63016631849398612272838767640434955186034709579530614080161182648640039173260
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14553.263672 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14553.263672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.5034862006234037238516500570221157768482104087304686038762157240942390014393
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15038.818580 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15038.818580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.80300709425422404323873223269767930902251994538073626905424775577751621185579
    Line 853, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3498.103956 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3498.103956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.38570481166325298750522107216786741998088998544051833820846778758161514620906
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3377.363167 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3377.363167 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.71421629905503089923032115273326386254333163650717655128841896848239721632548
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2357.921000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2357.921000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.65278121602115438758996018046293507679878949377991015453915128085018057713842
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1962.171500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1962.171500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.75310795534665707344249505229477261825191064278135733120369699851133641650684
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2276.279000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2276.279000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.54070493332058758656145031687800150082259444457615162904027443417728416330438
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 51095.173186 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51095.173186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.103969174188120805977881362067177470356642998445501181191288788214839421926666
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 52207.909453 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 52207.909453 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.67810790969820799761008929611053510466824001989634291296680663513899739673960
    Line 897, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 56291.159877 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 56291.159877 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL @ * us: (chip_sw_base_vseq.sv:781) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.106516373294647642125752560017439172095403074589558917393593490966105748888771
Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 3870.570267 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 3870.570267 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.12101843042798128555171544964252429835135027178386781854603538861165203060556
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_FATAL @ 4489.408764 us: (chip_sw_base_vseq.sv:781) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Cycle timeout (100000) for pinmux to connect JTAG to lc_ctrl
  UVM_INFO @ 4489.408764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 2 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 2 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.34382500656656742387232683941416338069970138940369584992038645264474652175735
    Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6806.049636 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6806.049636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.85093554875062043142251859196881507658041182846315901240009916098485731756841
    Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6052.836088 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6052.836088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:

Test rom_e2e_static_critical has 2 failures.

1.rom_e2e_static_critical.82663318872069101053877956870541260583324133788123539253534828439633577605746
Line 800, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_static_critical/latest/run.log

  UVM_ERROR @ 20016.095275 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20016.095275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_e2e_static_critical.53562640215798288583064899859170104074607349363346156853014711317821238094217
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_e2e_static_critical/latest/run.log

  UVM_ERROR @ 20014.641589 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20014.641589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred! has 1 failures:
- Test chip_sw_keymgr_sideload_aes has 1 failures.
  - 0.chip_sw_keymgr_sideload_aes.112922197997129763080650288720686993067805104891737172790626112438530318636720
    Line 857, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_aes_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.94786481105023994480270530169796689160572741519002140668188164463443656948801
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
  UVM_ERROR @ 2931.850450 us: (tlul_assert.sv:258) [ASSERT FAILED] respOpcode_M
  UVM_INFO @ 2931.850450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test rom_e2e_static_critical has 1 failures.
  - 0.rom_e2e_static_critical.73699551230585698298437642874171168680904184350182749378054330853602426584989
    Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log
```
  UVM_ERROR @ 20017.174864 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 20000000 ns
  
  UVM_INFO @ 20017.174864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred! has 1 failures:
- Test chip_sw_keymgr_sideload_kmac has 1 failures.
  - 1.chip_sw_keymgr_sideload_kmac.49022847213189128748959617289077103807851184994191287627516787970122120409862
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_keymgr_key_derivation_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_sideload_kmac_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.19212918261964510719383975744158455263568096278041811773109217154156082870367
    Line 1019, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5257.423897 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 5257.423897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 2.chip_csr_aliasing.12615203083368998815251763547830548040362353565345513101026464557578356897747
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:1f4b3581-6872-41f2-b626-1084495d2339
```
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test chip_tap_straps_testunlock0 has 1 failures.
  - 3.chip_tap_straps_testunlock0.84404052818027108625342031953663456774065259521281313800224284562291390643210
    Line 5978, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest/run.log
```
  UVM_ERROR @ 3847.251074 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 3847.251074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```