Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.25			94.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	94.19			94.19
tb.dut.top_earlgrey.u_i2c1	94.22			94.22
tb.dut.top_earlgrey.u_i2c2	94.22			94.22

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.35			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.35			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.22			94.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.35			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	348	328	94.25
Total Bits 0->1	174	164	94.25
Total Bits 1->0	174	164	94.25

Ports	52	48	92.31
Port Bits	348	328	94.25
Port Bits 0->1	174	164	94.25
Port Bits 1->0	174	164	94.25

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T225,T229	Yes	T224,T225,T229	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T225,T229	Yes	T224,T225,T229	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	INPUT
tl_i.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_o.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T225,T229,T27	Yes	T225,T229,T27	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T225,*T229	Yes	T224,T225,T229	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T387,T142,T388	Yes	T387,T142,T388	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T388,T52,T44	Yes	T52,T44,T254	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T52,T44,T254	Yes	T388,T52,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T387,T142,T388	Yes	T387,T142,T388	OUTPUT
cio_scl_i	Yes	Yes	T225,T229,T264	Yes	T225,T229,T264	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	OUTPUT
cio_sda_i	Yes	Yes	T225,T229,T264	Yes	T225,T229,T264	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T225,T229,T27	Yes	T225,T229,T27	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	OUTPUT
intr_rx_threshold_o	Yes	Yes	T225,T264,T272	Yes	T225,T264,T272	OUTPUT
intr_acq_threshold_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_controller_halt_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_scl_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_unstable_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_cmd_complete_o	Yes	Yes	T225,T229,T264	Yes	T225,T229,T264	OUTPUT
intr_tx_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_tx_threshold_o	Yes	Yes	T27,T257,T263	Yes	T27,T257,T263	OUTPUT
intr_acq_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_unexp_stop_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_host_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	344	324	94.19
Total Bits 0->1	172	162	94.19
Total Bits 1->0	172	162	94.19

Ports	52	48	92.31
Port Bits	344	324	94.19
Port Bits 0->1	172	162	94.19
Port Bits 1->0	172	162	94.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T225,T27	Yes	T224,T225,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T225,T27	Yes	T224,T225,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	INPUT
tl_i.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_o.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_error	Yes	Yes	T23,T25,T137	Yes	T23,T25,T137	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T225,*T27	Yes	T224,T225,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T387,T142,T52	Yes	T387,T142,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T52,T44,T45	Yes	T52,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T52,T44,T45	Yes	T52,T44,T45	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T387,T142,T52	Yes	T387,T142,T52	OUTPUT
cio_scl_i	Yes	Yes	T225,T264,T265	Yes	T225,T264,T265	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T225,T264,T283	Yes	T225,T264,T283	OUTPUT
cio_sda_i	Yes	Yes	T225,T264,T265	Yes	T225,T264,T265	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	OUTPUT
intr_rx_threshold_o	Yes	Yes	T225,T264,T257	Yes	T225,T264,T257	OUTPUT
intr_acq_threshold_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_controller_halt_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_scl_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_unstable_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_cmd_complete_o	Yes	Yes	T225,T264,T265	Yes	T225,T264,T265	OUTPUT
intr_tx_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_tx_threshold_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_acq_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_unexp_stop_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_host_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T27,T389	Yes	T224,T27,T389	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T27,T389	Yes	T224,T27,T389	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	INPUT
tl_i.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_o.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T27,T257,T269	Yes	T27,T257,T269	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T27,*T389	Yes	T224,T27,T389	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T142,T52,T143	Yes	T142,T52,T143	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T52,T44,T45	Yes	T52,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T52,T44,T45	Yes	T52,T44,T45	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T142,T52,T143	Yes	T142,T52,T143	OUTPUT
cio_scl_i	Yes	Yes	T269,T270,T271	Yes	T269,T270,T271	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T269,T270,T271	Yes	T269,T270,T271	OUTPUT
cio_sda_i	Yes	Yes	T269,T270,T271	Yes	T269,T270,T271	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T27,T269,T270	Yes	T27,T269,T270	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T257,T269,T270	Yes	T257,T269,T270	OUTPUT
intr_rx_threshold_o	Yes	Yes	T257,T269,T270	Yes	T257,T269,T270	OUTPUT
intr_acq_threshold_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_controller_halt_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_scl_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_unstable_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_cmd_complete_o	Yes	Yes	T257,T269,T270	Yes	T257,T269,T270	OUTPUT
intr_tx_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_tx_threshold_o	Yes	Yes	T27,T257,T263	Yes	T27,T257,T263	OUTPUT
intr_acq_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_unexp_stop_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_host_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	48	92.31
Total Bits	346	326	94.22
Total Bits 0->1	173	163	94.22
Total Bits 1->0	173	163	94.22

Ports	52	48	92.31
Port Bits	346	326	94.22
Port Bits 0->1	173	163	94.22
Port Bits 1->0	173	163	94.22

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T224,T229,T27	Yes	T224,T229,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T224,T229,T27	Yes	T224,T229,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	INPUT
tl_i.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_o.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T229,T27,T272	Yes	T229,T27,T272	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T224,*T229,*T27	Yes	T224,T229,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T142,T388,T52	Yes	T142,T388,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T388,T52,T44	Yes	T52,T44,T254	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T52,T44,T254	Yes	T388,T52,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T142,T388,T52	Yes	T142,T388,T52	OUTPUT
cio_scl_i	Yes	Yes	T229,T272,T390	Yes	T229,T272,T390	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T27,T272,T273	Yes	T27,T272,T273	OUTPUT
cio_sda_i	Yes	Yes	T229,T272,T390	Yes	T229,T272,T390	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T229,T27,T272	Yes	T229,T27,T272	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T272,T257,T273	Yes	T272,T257,T273	OUTPUT
intr_rx_threshold_o	Yes	Yes	T272,T257,T273	Yes	T272,T257,T273	OUTPUT
intr_acq_threshold_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_controller_halt_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_scl_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_interference_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_sda_unstable_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_cmd_complete_o	Yes	Yes	T229,T272,T390	Yes	T229,T272,T390	OUTPUT
intr_tx_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_tx_threshold_o	Yes	Yes	T27,T257,T263	Yes	T27,T257,T263	OUTPUT
intr_acq_stretch_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_unexp_stop_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT
intr_host_timeout_o	Yes	Yes	T257,T263,T266	Yes	T257,T263,T266	OUTPUT

*Tests covering at least one bit in the range