Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : top_earlgrey
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.45 90.68 59.67 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey 93.34 90.68 89.35 100.00



Module Instance : tb.dut.top_earlgrey

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.34 90.68 89.35 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.57 95.44 93.67 91.93 94.76 97.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.83 80.00 100.00 98.48 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clk_ctrl_and_main_pd_sva_if 100.00 100.00
u_adc_ctrl_aon 100.00 100.00
u_aes 100.00 100.00
u_alert_handler 99.92 99.92
u_aon_timer_aon 100.00 100.00
u_clkmgr_aon 94.77 94.77
u_csrng 99.27 99.27
u_dft_tap_breakout 100.00 100.00 100.00
u_edn0 99.17 99.17
u_edn1 99.02 99.02
u_entropy_src 99.18 99.18
u_flash_ctrl 97.21 97.21
u_gpio 100.00 100.00
u_hmac 100.00 100.00
u_i2c0 94.19 94.19
u_i2c1 94.22 94.22
u_i2c2 94.22 94.22
u_keymgr 89.72 89.72
u_kmac 86.23 86.23
u_lc_ctrl 72.80 72.80
u_otbn 99.34 99.34
u_otp_ctrl 80.51 80.51
u_pattgen 100.00 100.00
u_pinmux_aon 97.20 96.24 95.48 98.85 96.14 99.30
u_pwm_aon 100.00 100.00
u_pwrmgr_aon 99.57 99.57
u_rom_ctrl 99.93 99.93
u_rstmgr_aon 100.00 100.00
u_rv_core_ibex 96.77 97.76 95.75 98.81 98.66 92.86
u_rv_dm 100.00 100.00
u_rv_plic 93.93 93.87 91.00 99.18 92.74 92.86
u_rv_timer 100.00 100.00
u_sensor_ctrl_aon 91.38 93.95 86.84 79.93 96.17 100.00
u_spi_device 98.42 98.42
u_spi_host0 96.59 96.59
u_spi_host1 96.30 96.30
u_sram_ctrl_main 100.00 100.00
u_sram_ctrl_ret_aon 100.00 100.00
u_sysrst_ctrl_aon 100.00 100.00
u_uart0 100.00 100.00
u_uart1 100.00 100.00
u_uart2 100.00 100.00
u_uart3 100.00 100.00
u_usbdev 95.05 95.05
u_xbar_main 100.00 100.00
u_xbar_peri 100.00 100.00

Line Coverage for Module : top_earlgrey
Line No.TotalCoveredPercent
TOTAL27925390.68
CONT_ASSIGN75411100.00
CONT_ASSIGN75511100.00
CONT_ASSIGN75611100.00
CONT_ASSIGN757100.00
CONT_ASSIGN758100.00
CONT_ASSIGN759100.00
CONT_ASSIGN760100.00
CONT_ASSIGN761100.00
CONT_ASSIGN77411100.00
CONT_ASSIGN775100.00
CONT_ASSIGN776100.00
CONT_ASSIGN777100.00
CONT_ASSIGN778100.00
CONT_ASSIGN779100.00
CONT_ASSIGN780100.00
CONT_ASSIGN781100.00
CONT_ASSIGN79511100.00
CONT_ASSIGN79711100.00
CONT_ASSIGN79911100.00
CONT_ASSIGN80111100.00
CONT_ASSIGN80311100.00
CONT_ASSIGN80511100.00
CONT_ASSIGN80911100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN82011100.00
CONT_ASSIGN82411100.00
CONT_ASSIGN84811100.00
CONT_ASSIGN84911100.00
CONT_ASSIGN85111100.00
CONT_ASSIGN85211100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN85511100.00
CONT_ASSIGN85711100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86611100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86911100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN87211100.00
CONT_ASSIGN87311100.00
CONT_ASSIGN87511100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN878100.00
CONT_ASSIGN87911100.00
CONT_ASSIGN881100.00
CONT_ASSIGN88211100.00
CONT_ASSIGN88411100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN91211100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91511100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN92400
CONT_ASSIGN92600
CONT_ASSIGN92800
CONT_ASSIGN93000
CONT_ASSIGN93200
CONT_ASSIGN93400
CONT_ASSIGN93600
CONT_ASSIGN93800
CONT_ASSIGN94000
CONT_ASSIGN94200
CONT_ASSIGN94400
CONT_ASSIGN94600
CONT_ASSIGN94800
CONT_ASSIGN95000
CONT_ASSIGN95200
CONT_ASSIGN95400
CONT_ASSIGN95600
CONT_ASSIGN95800
CONT_ASSIGN96000
CONT_ASSIGN96200
CONT_ASSIGN96400
CONT_ASSIGN96600
CONT_ASSIGN96800
CONT_ASSIGN97000
CONT_ASSIGN97200
CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN101200
CONT_ASSIGN101400
CONT_ASSIGN101600
CONT_ASSIGN265611100.00
CONT_ASSIGN305611100.00
CONT_ASSIGN305711100.00
CONT_ASSIGN305811100.00
CONT_ASSIGN305911100.00
CONT_ASSIGN306011100.00
CONT_ASSIGN306111100.00
CONT_ASSIGN306211100.00
CONT_ASSIGN306311100.00
CONT_ASSIGN306411100.00
CONT_ASSIGN306511100.00
CONT_ASSIGN306611100.00
CONT_ASSIGN306711100.00
CONT_ASSIGN306811100.00
CONT_ASSIGN306911100.00
CONT_ASSIGN307011100.00
CONT_ASSIGN307111100.00
CONT_ASSIGN307211100.00
CONT_ASSIGN307311100.00
CONT_ASSIGN307411100.00
CONT_ASSIGN307511100.00
CONT_ASSIGN307611100.00
CONT_ASSIGN307711100.00
CONT_ASSIGN307811100.00
CONT_ASSIGN307911100.00
CONT_ASSIGN308011100.00
CONT_ASSIGN308111100.00
CONT_ASSIGN308211100.00
CONT_ASSIGN308311100.00
CONT_ASSIGN308411100.00
CONT_ASSIGN308511100.00
CONT_ASSIGN308611100.00
CONT_ASSIGN308711100.00
CONT_ASSIGN308811100.00
CONT_ASSIGN308911100.00
CONT_ASSIGN309011100.00
CONT_ASSIGN309111100.00
CONT_ASSIGN309211100.00
CONT_ASSIGN309311100.00
CONT_ASSIGN309411100.00
CONT_ASSIGN309511100.00
CONT_ASSIGN309611100.00
CONT_ASSIGN309711100.00
CONT_ASSIGN309811100.00
CONT_ASSIGN309911100.00
CONT_ASSIGN310011100.00
CONT_ASSIGN310111100.00
CONT_ASSIGN310211100.00
CONT_ASSIGN310311100.00
CONT_ASSIGN310411100.00
CONT_ASSIGN310511100.00
CONT_ASSIGN310611100.00
CONT_ASSIGN310711100.00
CONT_ASSIGN310811100.00
CONT_ASSIGN310911100.00
CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
CONT_ASSIGN311211100.00
CONT_ASSIGN311511100.00
CONT_ASSIGN311611100.00
CONT_ASSIGN311711100.00
CONT_ASSIGN311811100.00
CONT_ASSIGN311911100.00
CONT_ASSIGN312011100.00
CONT_ASSIGN312111100.00
CONT_ASSIGN312211100.00
CONT_ASSIGN312311100.00
CONT_ASSIGN312411100.00
CONT_ASSIGN312511100.00
CONT_ASSIGN312611100.00
CONT_ASSIGN312711100.00
CONT_ASSIGN312811100.00
CONT_ASSIGN312911100.00
CONT_ASSIGN313011100.00
CONT_ASSIGN313111100.00
CONT_ASSIGN313211100.00
CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN313611100.00
CONT_ASSIGN313711100.00
CONT_ASSIGN313811100.00
CONT_ASSIGN313911100.00
CONT_ASSIGN314011100.00
CONT_ASSIGN314111100.00
CONT_ASSIGN314211100.00
CONT_ASSIGN314311100.00
CONT_ASSIGN314411100.00
CONT_ASSIGN314511100.00
CONT_ASSIGN314611100.00
CONT_ASSIGN314700
CONT_ASSIGN314800
CONT_ASSIGN314900
CONT_ASSIGN315000
CONT_ASSIGN315100
CONT_ASSIGN315200
CONT_ASSIGN315311100.00
CONT_ASSIGN3154100.00
CONT_ASSIGN3155100.00
CONT_ASSIGN3156100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN315911100.00
CONT_ASSIGN316011100.00
CONT_ASSIGN316111100.00
CONT_ASSIGN316211100.00
CONT_ASSIGN316311100.00
CONT_ASSIGN316411100.00
CONT_ASSIGN316511100.00
CONT_ASSIGN316611100.00
CONT_ASSIGN3167100.00
CONT_ASSIGN316800
CONT_ASSIGN316900
CONT_ASSIGN317000
CONT_ASSIGN317100
CONT_ASSIGN317200
CONT_ASSIGN317300
CONT_ASSIGN317400
CONT_ASSIGN317500
CONT_ASSIGN317600
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN317911100.00
CONT_ASSIGN318011100.00
CONT_ASSIGN318111100.00
CONT_ASSIGN318211100.00
CONT_ASSIGN3183100.00
CONT_ASSIGN318411100.00
CONT_ASSIGN318511100.00
CONT_ASSIGN318611100.00
CONT_ASSIGN318711100.00
CONT_ASSIGN318811100.00
CONT_ASSIGN318911100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN319511100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN320011100.00
CONT_ASSIGN320111100.00
CONT_ASSIGN320211100.00
CONT_ASSIGN320311100.00
CONT_ASSIGN320411100.00
CONT_ASSIGN320511100.00
CONT_ASSIGN320611100.00
CONT_ASSIGN320711100.00
CONT_ASSIGN320811100.00
CONT_ASSIGN320911100.00
CONT_ASSIGN321011100.00
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN321311100.00
CONT_ASSIGN321411100.00
CONT_ASSIGN321511100.00
CONT_ASSIGN321611100.00
CONT_ASSIGN321711100.00
CONT_ASSIGN321811100.00
CONT_ASSIGN321911100.00
CONT_ASSIGN322011100.00
CONT_ASSIGN322111100.00
CONT_ASSIGN322211100.00
CONT_ASSIGN322311100.00
CONT_ASSIGN322411100.00
CONT_ASSIGN322511100.00
CONT_ASSIGN322611100.00
CONT_ASSIGN322711100.00
CONT_ASSIGN322811100.00
CONT_ASSIGN322911100.00
CONT_ASSIGN323011100.00
CONT_ASSIGN3231100.00
CONT_ASSIGN3232100.00
CONT_ASSIGN3233100.00
CONT_ASSIGN323400
CONT_ASSIGN323500
CONT_ASSIGN323600
CONT_ASSIGN323700
CONT_ASSIGN323800
CONT_ASSIGN323900
CONT_ASSIGN324000
CONT_ASSIGN324100
CONT_ASSIGN324211100.00
CONT_ASSIGN324311100.00
CONT_ASSIGN3244100.00
CONT_ASSIGN324500
CONT_ASSIGN324600
CONT_ASSIGN324700
CONT_ASSIGN324800
CONT_ASSIGN324900
CONT_ASSIGN325000
CONT_ASSIGN325100
CONT_ASSIGN325200
CONT_ASSIGN325300
CONT_ASSIGN325400
CONT_ASSIGN325500
CONT_ASSIGN325600
CONT_ASSIGN325700
CONT_ASSIGN325800
CONT_ASSIGN325900
CONT_ASSIGN326011100.00
CONT_ASSIGN326100
CONT_ASSIGN326200
CONT_ASSIGN326300
CONT_ASSIGN326400
CONT_ASSIGN326500
CONT_ASSIGN326600
CONT_ASSIGN327011100.00
CONT_ASSIGN327111100.00
CONT_ASSIGN327211100.00
CONT_ASSIGN327311100.00
CONT_ASSIGN327411100.00
CONT_ASSIGN327511100.00
CONT_ASSIGN327611100.00
CONT_ASSIGN327711100.00
CONT_ASSIGN327811100.00
CONT_ASSIGN327911100.00
CONT_ASSIGN328011100.00
CONT_ASSIGN328111100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328711100.00
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
CONT_ASSIGN329011100.00
CONT_ASSIGN329111100.00
CONT_ASSIGN329211100.00
CONT_ASSIGN329311100.00
CONT_ASSIGN329411100.00
CONT_ASSIGN329511100.00
CONT_ASSIGN329611100.00
CONT_ASSIGN329711100.00
CONT_ASSIGN329811100.00
CONT_ASSIGN330111100.00
CONT_ASSIGN330211100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN330611100.00
CONT_ASSIGN330711100.00
CONT_ASSIGN3308100.00
CONT_ASSIGN3309100.00
CONT_ASSIGN3310100.00
CONT_ASSIGN331111100.00
CONT_ASSIGN331211100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331411100.00
CONT_ASSIGN331500
CONT_ASSIGN331600
CONT_ASSIGN331911100.00
CONT_ASSIGN332011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
754 1 1
755 1 1
756 1 1
757 0 1
758 0 1
759 0 1
760 0 1
761 0 1
774 1 1
775 0 1
776 0 1
777 0 1
778 0 1
779 0 1
780 0 1
781 0 1
795 1 1
797 1 1
799 1 1
801 1 1
803 1 1
805 1 1
809 1 1
819 1 1
820 1 1
824 1 1
848 1 1
849 1 1
851 1 1
852 1 1
854 1 1
855 1 1
857 1 1
858 1 1
860 1 1
861 1 1
863 1 1
864 1 1
866 1 1
867 1 1
869 1 1
870 1 1
872 1 1
873 1 1
875 1 1
876 1 1
878 0 1
879 1 1
881 0 1
882 1 1
884 1 1
885 1 1
887 1 1
888 1 1
890 1 1
891 1 1
893 1 1
894 1 1
896 1 1
897 1 1
899 1 1
900 1 1
902 1 1
903 1 1
905 1 1
906 1 1
908 1 1
909 1 1
911 1 1
912 1 1
914 1 1
915 1 1
917 1 1
918 1 1
924 unreachable
926 unreachable
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
1012 unreachable
1014 unreachable
1016 unreachable
2656 1 1
3056 1 1
3057 1 1
3058 1 1
3059 1 1
3060 1 1
3061 1 1
3062 1 1
3063 1 1
3064 1 1
3065 1 1
3066 1 1
3067 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3082 1 1
3083 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3115 1 1
3116 1 1
3117 1 1
3118 1 1
3119 1 1
3120 1 1
3121 1 1
3122 1 1
3123 1 1
3124 1 1
3125 1 1
3126 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 1 1
3137 1 1
3138 1 1
3139 1 1
3140 1 1
3141 1 1
3142 1 1
3143 1 1
3144 1 1
3145 1 1
3146 1 1
3147 unreachable
3148 unreachable
3149 unreachable
3150 unreachable
3151 unreachable
3152 unreachable
3153 1 1
3154 0 1
3155 0 1
3156 0 1
3157 1 1
3158 1 1
3159 1 1
3160 1 1
3161 1 1
3162 1 1
3163 1 1
3164 1 1
3165 1 1
3166 1 1
3167 0 1
3168 unreachable
3169 unreachable
3170 unreachable
3171 unreachable
3172 unreachable
3173 unreachable
3174 unreachable
3175 unreachable
3176 unreachable
3177 1 1
3178 1 1
3179 1 1
3180 1 1
3181 1 1
3182 1 1
3183 0 1
3184 1 1
3185 1 1
3186 1 1
3187 1 1
3188 1 1
3189 1 1
3192 1 1
3193 1 1
3194 1 1
3195 1 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 1 1
3201 1 1
3202 1 1
3203 1 1
3204 1 1
3205 1 1
3206 1 1
3207 1 1
3208 1 1
3209 1 1
3210 1 1
3211 1 1
3212 1 1
3213 1 1
3214 1 1
3215 1 1
3216 1 1
3217 1 1
3218 1 1
3219 1 1
3220 1 1
3221 1 1
3222 1 1
3223 1 1
3224 1 1
3225 1 1
3226 1 1
3227 1 1
3228 1 1
3229 1 1
3230 1 1
3231 0 1
3232 0 1
3233 0 1
3234 unreachable
3235 unreachable
3236 unreachable
3237 unreachable
3238 unreachable
3239 unreachable
3240 unreachable
3241 unreachable
3242 1 1
3243 1 1
3244 0 1
3245 unreachable
3246 unreachable
3247 unreachable
3248 unreachable
3249 unreachable
3250 unreachable
3251 unreachable
3252 unreachable
3253 unreachable
3254 unreachable
3255 unreachable
3256 unreachable
3257 unreachable
3258 unreachable
3259 unreachable
3260 1 1
3261 unreachable
3262 unreachable
3263 unreachable
3264 unreachable
3265 unreachable
3266 unreachable
3270 1 1
3271 1 1
3272 1 1
3273 1 1
3274 1 1
3275 1 1
3276 1 1
3277 1 1
3278 1 1
3279 1 1
3280 1 1
3281 1 1
3282 1 1
3283 1 1
3284 1 1
3287 1 1
3288 1 1
3289 1 1
3290 1 1
3291 1 1
3292 1 1
3293 1 1
3294 1 1
3295 1 1
3296 1 1
3297 1 1
3298 1 1
3301 1 1
3302 1 1
3305 1 1
3306 1 1
3307 1 1
3308 0 1
3309 0 1
3310 0 1
3311 1 1
3312 1 1
3313 1 1
3314 1 1
3315 unreachable
3316 unreachable
3319 1 1
3320 1 1


Toggle Coverage for Module : top_earlgrey
TotalCoveredPercent
Totals 891 500 56.12
Total Bits 3176 1895 59.67
Total Bits 0->1 1588 951 59.89
Total Bits 1->0 1588 944 59.45

Ports 891 500 56.12
Port Bits 3176 1895 59.67
Port Bits 0->1 1588 951 59.89
Port Bits 1->0 1588 944 59.45

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
mio_in_i[46:0] Yes Yes T74,T75,T1 Yes T74,T75,T1 INPUT
mio_out_o[46:0] Yes Yes T1,T82,T83 Yes T1,T82,T83 OUTPUT
mio_oe_o[46:0] Yes Yes T83,T84,T85 Yes T1,T82,T68 OUTPUT
dio_in_i[15:0] Yes Yes T76,T77,T102 Yes T76,T77,T102 INPUT
dio_out_o[11:0] Yes Yes *T76,*T77,*T3 Yes T76,T77,T3 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T71,T72,T73 Yes T71,T72,T73 OUTPUT
dio_oe_o[15:0] Yes Yes T77,T80,T81 Yes T68,T77,T69 OUTPUT
mio_attr_o[0].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].pull_en Yes Yes T86,T87,T88 Yes T95,T96,T97 OUTPUT
mio_attr_o[7].pull_select Yes Yes T86,T87,T88 Yes T95,T96,T97 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[9].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[10].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[12].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[13].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[14].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[15].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[22].pull_select Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[23].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[24].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].pull_en Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
mio_attr_o[25].pull_select Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en Yes Yes T38,T99,T39 Yes T42,T43,T38 OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en Yes Yes T38,T99,T39 Yes T42,T43,T38 OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
dio_attr_o[0].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[4].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[5].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T86,T88,T91 Yes T86,T88,T91 OUTPUT
dio_attr_o[6].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].input_disable Yes Yes T87,T88,T91 Yes T87,T88,T91 OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T86,*T88,*T91 Yes T86,T88,T91 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T86,T87,T88 Yes T92,T93,T94 OUTPUT
dio_attr_o[10].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T86,T87,T88 Yes T92,T93,T94 OUTPUT
dio_attr_o[11].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[14].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[15].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
adc_req_o.pd Yes Yes T148,T154,T155 Yes T148,T154,T155 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T148,T154,T155 Yes T148,T154,T155 OUTPUT
adc_rsp_i.data_valid Yes Yes T148,T154,T155 Yes T148,T154,T155 INPUT
adc_rsp_i.data[9:0] Yes Yes T148,T154,T155 Yes T148,T154,T155 INPUT
ast_edn_req_i.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T4,T5,T19 Yes T4,T5,T19 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T156,T157,T158 Yes T63,T159,T160 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
clk_main_jitter_en_o[3:0] Yes Yes T112,T161,T63 Yes T63,T159,T160 OUTPUT
io_clk_byp_req_o[3:0] No No No OUTPUT
io_clk_byp_ack_i[3:0] No No No INPUT
all_clk_byp_req_o[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 INPUT
hi_speed_sel_o[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
div_step_down_req_i[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 INPUT
calib_rdy_i[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T4,T5,T6 Yes T6,T147,T148 INPUT
flash_power_ready_h_i No No Yes T4,T5,T6 INPUT
flash_test_mode_a_io[1:0] No No Yes T68,T69,T70 INOUT
flash_test_voltage_h_io No No Yes T68,T69,T70 INOUT
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_rsp_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_fips_o Yes Yes T163,T164,T165 Yes T166,T167,T163 OUTPUT
ast_tl_req_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T27,T29,T30 Yes T27,T29,T30 OUTPUT
ast_tl_req_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
dft_strap_test_o.straps[1:0] No No Yes T103,T104,T105 OUTPUT
dft_strap_test_o.valid Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T76,T77,T3 Yes T76,T77,T3 OUTPUT
usb_dn_pullup_en_o Yes Yes T76,T77,T102 Yes T76,T77,T102 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T4,T5,T6 Yes T6,T20,T36 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T6,T20,T36 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T6,T147,T148 Yes T6,T147,T148 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T6,T20,T36 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T42,T43,T168 Yes T4,T5,T6 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T4,T5,T6 Yes T6,T147,T148 INPUT
otp_ext_voltage_h_io No No Yes T68,T69,T70 INOUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T20,T36,T59 Yes T4,T5,T6 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T169,T170,T171 Yes T169,T170,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T169,T170,T172 Yes T169,T170,T171 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T171,T173,T174 Yes T175,T176,T177 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T175,T176,T177 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T171,T173,T172 Yes T172,T178,T176 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T172,T178,T176 Yes T171,T173,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n Yes Yes T179,T171,T173 Yes T179,T180,T176 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p Yes Yes T179,T180,T176 Yes T179,T171,T173 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T171,T173,T172 Yes T172,T178,T175 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T172,T178,T175 Yes T171,T173,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T171,T173,T174 Yes T176,T177,T181 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T176,T177,T181 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T171,T173,T174 Yes T176,T182,T183 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T176,T182,T183 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T171,T173,T174 Yes T157,T158,T177 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T157,T158,T177 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T171,T173,T174 Yes T157,T158,T182 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T157,T158,T182 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T171,T173,T174 Yes T176,T177,T182 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T176,T177,T182 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T171,T173,T174 Yes T176,T177,T181 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T176,T177,T181 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T168,T184,T185 Yes T4,T5,T6 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
sensor_ctrl_manual_pad_attr_o[0].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].drive_strength[3:0] No No No OUTPUT
sck_monitor_o Yes Yes T71,T72,T95 Yes T71,T72,T68 OUTPUT
usbdev_usb_rx_d_i Yes Yes T76,T77,T102 Yes T76,T77,T102 INPUT
usbdev_usb_tx_d_o Yes Yes T76,T77,T3 Yes T76,T77,T3 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T186,T187,T188 Yes T186,T187,T188 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T77,T189,T190 Yes T76,T77,T102 OUTPUT
usbdev_usb_ref_val_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clks_ast_o.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T20,T36,T59 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 407935536 407935536 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 407935536 407935536 0 0
T4 95755 95755 0 0
T5 251720 251720 0 0
T6 101385 101385 0 0
T17 171968 171968 0 0
T18 267994 267994 0 0
T19 163667 163667 0 0
T20 113601 113601 0 0
T51 271006 271006 0 0
T111 97218 97218 0 0
T112 72094 72094 0 0

Line Coverage for Instance : tb.dut.top_earlgrey
Line No.TotalCoveredPercent
TOTAL27925390.68
CONT_ASSIGN75411100.00
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CONT_ASSIGN86111100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
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CONT_ASSIGN89611100.00
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CONT_ASSIGN92400
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CONT_ASSIGN93000
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CONT_ASSIGN94000
CONT_ASSIGN94200
CONT_ASSIGN94400
CONT_ASSIGN94600
CONT_ASSIGN94800
CONT_ASSIGN95000
CONT_ASSIGN95200
CONT_ASSIGN95400
CONT_ASSIGN95600
CONT_ASSIGN95800
CONT_ASSIGN96000
CONT_ASSIGN96200
CONT_ASSIGN96400
CONT_ASSIGN96600
CONT_ASSIGN96800
CONT_ASSIGN97000
CONT_ASSIGN97200
CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN101200
CONT_ASSIGN101400
CONT_ASSIGN101600
CONT_ASSIGN265611100.00
CONT_ASSIGN305611100.00
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CONT_ASSIGN306011100.00
CONT_ASSIGN306111100.00
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CONT_ASSIGN307111100.00
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CONT_ASSIGN308011100.00
CONT_ASSIGN308111100.00
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CONT_ASSIGN309011100.00
CONT_ASSIGN309111100.00
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CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
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CONT_ASSIGN311911100.00
CONT_ASSIGN312011100.00
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CONT_ASSIGN313011100.00
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CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN313611100.00
CONT_ASSIGN313711100.00
CONT_ASSIGN313811100.00
CONT_ASSIGN313911100.00
CONT_ASSIGN314011100.00
CONT_ASSIGN314111100.00
CONT_ASSIGN314211100.00
CONT_ASSIGN314311100.00
CONT_ASSIGN314411100.00
CONT_ASSIGN314511100.00
CONT_ASSIGN314611100.00
CONT_ASSIGN314700
CONT_ASSIGN314800
CONT_ASSIGN314900
CONT_ASSIGN315000
CONT_ASSIGN315100
CONT_ASSIGN315200
CONT_ASSIGN315311100.00
CONT_ASSIGN3154100.00
CONT_ASSIGN3155100.00
CONT_ASSIGN3156100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN315911100.00
CONT_ASSIGN316011100.00
CONT_ASSIGN316111100.00
CONT_ASSIGN316211100.00
CONT_ASSIGN316311100.00
CONT_ASSIGN316411100.00
CONT_ASSIGN316511100.00
CONT_ASSIGN316611100.00
CONT_ASSIGN3167100.00
CONT_ASSIGN316800
CONT_ASSIGN316900
CONT_ASSIGN317000
CONT_ASSIGN317100
CONT_ASSIGN317200
CONT_ASSIGN317300
CONT_ASSIGN317400
CONT_ASSIGN317500
CONT_ASSIGN317600
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN317911100.00
CONT_ASSIGN318011100.00
CONT_ASSIGN318111100.00
CONT_ASSIGN318211100.00
CONT_ASSIGN3183100.00
CONT_ASSIGN318411100.00
CONT_ASSIGN318511100.00
CONT_ASSIGN318611100.00
CONT_ASSIGN318711100.00
CONT_ASSIGN318811100.00
CONT_ASSIGN318911100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN319511100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN320011100.00
CONT_ASSIGN320111100.00
CONT_ASSIGN320211100.00
CONT_ASSIGN320311100.00
CONT_ASSIGN320411100.00
CONT_ASSIGN320511100.00
CONT_ASSIGN320611100.00
CONT_ASSIGN320711100.00
CONT_ASSIGN320811100.00
CONT_ASSIGN320911100.00
CONT_ASSIGN321011100.00
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN321311100.00
CONT_ASSIGN321411100.00
CONT_ASSIGN321511100.00
CONT_ASSIGN321611100.00
CONT_ASSIGN321711100.00
CONT_ASSIGN321811100.00
CONT_ASSIGN321911100.00
CONT_ASSIGN322011100.00
CONT_ASSIGN322111100.00
CONT_ASSIGN322211100.00
CONT_ASSIGN322311100.00
CONT_ASSIGN322411100.00
CONT_ASSIGN322511100.00
CONT_ASSIGN322611100.00
CONT_ASSIGN322711100.00
CONT_ASSIGN322811100.00
CONT_ASSIGN322911100.00
CONT_ASSIGN323011100.00
CONT_ASSIGN3231100.00
CONT_ASSIGN3232100.00
CONT_ASSIGN3233100.00
CONT_ASSIGN323400
CONT_ASSIGN323500
CONT_ASSIGN323600
CONT_ASSIGN323700
CONT_ASSIGN323800
CONT_ASSIGN323900
CONT_ASSIGN324000
CONT_ASSIGN324100
CONT_ASSIGN324211100.00
CONT_ASSIGN324311100.00
CONT_ASSIGN3244100.00
CONT_ASSIGN324500
CONT_ASSIGN324600
CONT_ASSIGN324700
CONT_ASSIGN324800
CONT_ASSIGN324900
CONT_ASSIGN325000
CONT_ASSIGN325100
CONT_ASSIGN325200
CONT_ASSIGN325300
CONT_ASSIGN325400
CONT_ASSIGN325500
CONT_ASSIGN325600
CONT_ASSIGN325700
CONT_ASSIGN325800
CONT_ASSIGN325900
CONT_ASSIGN326011100.00
CONT_ASSIGN326100
CONT_ASSIGN326200
CONT_ASSIGN326300
CONT_ASSIGN326400
CONT_ASSIGN326500
CONT_ASSIGN326600
CONT_ASSIGN327011100.00
CONT_ASSIGN327111100.00
CONT_ASSIGN327211100.00
CONT_ASSIGN327311100.00
CONT_ASSIGN327411100.00
CONT_ASSIGN327511100.00
CONT_ASSIGN327611100.00
CONT_ASSIGN327711100.00
CONT_ASSIGN327811100.00
CONT_ASSIGN327911100.00
CONT_ASSIGN328011100.00
CONT_ASSIGN328111100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328711100.00
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
CONT_ASSIGN329011100.00
CONT_ASSIGN329111100.00
CONT_ASSIGN329211100.00
CONT_ASSIGN329311100.00
CONT_ASSIGN329411100.00
CONT_ASSIGN329511100.00
CONT_ASSIGN329611100.00
CONT_ASSIGN329711100.00
CONT_ASSIGN329811100.00
CONT_ASSIGN330111100.00
CONT_ASSIGN330211100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN330611100.00
CONT_ASSIGN330711100.00
CONT_ASSIGN3308100.00
CONT_ASSIGN3309100.00
CONT_ASSIGN3310100.00
CONT_ASSIGN331111100.00
CONT_ASSIGN331211100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331411100.00
CONT_ASSIGN331500
CONT_ASSIGN331600
CONT_ASSIGN331911100.00
CONT_ASSIGN332011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
754 1 1
755 1 1
756 1 1
757 0 1
758 0 1
759 0 1
760 0 1
761 0 1
774 1 1
775 0 1
776 0 1
777 0 1
778 0 1
779 0 1
780 0 1
781 0 1
795 1 1
797 1 1
799 1 1
801 1 1
803 1 1
805 1 1
809 1 1
819 1 1
820 1 1
824 1 1
848 1 1
849 1 1
851 1 1
852 1 1
854 1 1
855 1 1
857 1 1
858 1 1
860 1 1
861 1 1
863 1 1
864 1 1
866 1 1
867 1 1
869 1 1
870 1 1
872 1 1
873 1 1
875 1 1
876 1 1
878 0 1
879 1 1
881 0 1
882 1 1
884 1 1
885 1 1
887 1 1
888 1 1
890 1 1
891 1 1
893 1 1
894 1 1
896 1 1
897 1 1
899 1 1
900 1 1
902 1 1
903 1 1
905 1 1
906 1 1
908 1 1
909 1 1
911 1 1
912 1 1
914 1 1
915 1 1
917 1 1
918 1 1
924 unreachable
926 unreachable
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
1012 unreachable
1014 unreachable
1016 unreachable
2656 1 1
3056 1 1
3057 1 1
3058 1 1
3059 1 1
3060 1 1
3061 1 1
3062 1 1
3063 1 1
3064 1 1
3065 1 1
3066 1 1
3067 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3082 1 1
3083 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3115 1 1
3116 1 1
3117 1 1
3118 1 1
3119 1 1
3120 1 1
3121 1 1
3122 1 1
3123 1 1
3124 1 1
3125 1 1
3126 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 1 1
3137 1 1
3138 1 1
3139 1 1
3140 1 1
3141 1 1
3142 1 1
3143 1 1
3144 1 1
3145 1 1
3146 1 1
3147 unreachable
3148 unreachable
3149 unreachable
3150 unreachable
3151 unreachable
3152 unreachable
3153 1 1
3154 0 1
3155 0 1
3156 0 1
3157 1 1
3158 1 1
3159 1 1
3160 1 1
3161 1 1
3162 1 1
3163 1 1
3164 1 1
3165 1 1
3166 1 1
3167 0 1
3168 unreachable
3169 unreachable
3170 unreachable
3171 unreachable
3172 unreachable
3173 unreachable
3174 unreachable
3175 unreachable
3176 unreachable
3177 1 1
3178 1 1
3179 1 1
3180 1 1
3181 1 1
3182 1 1
3183 0 1
3184 1 1
3185 1 1
3186 1 1
3187 1 1
3188 1 1
3189 1 1
3192 1 1
3193 1 1
3194 1 1
3195 1 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 1 1
3201 1 1
3202 1 1
3203 1 1
3204 1 1
3205 1 1
3206 1 1
3207 1 1
3208 1 1
3209 1 1
3210 1 1
3211 1 1
3212 1 1
3213 1 1
3214 1 1
3215 1 1
3216 1 1
3217 1 1
3218 1 1
3219 1 1
3220 1 1
3221 1 1
3222 1 1
3223 1 1
3224 1 1
3225 1 1
3226 1 1
3227 1 1
3228 1 1
3229 1 1
3230 1 1
3231 0 1
3232 0 1
3233 0 1
3234 unreachable
3235 unreachable
3236 unreachable
3237 unreachable
3238 unreachable
3239 unreachable
3240 unreachable
3241 unreachable
3242 1 1
3243 1 1
3244 0 1
3245 unreachable
3246 unreachable
3247 unreachable
3248 unreachable
3249 unreachable
3250 unreachable
3251 unreachable
3252 unreachable
3253 unreachable
3254 unreachable
3255 unreachable
3256 unreachable
3257 unreachable
3258 unreachable
3259 unreachable
3260 1 1
3261 unreachable
3262 unreachable
3263 unreachable
3264 unreachable
3265 unreachable
3266 unreachable
3270 1 1
3271 1 1
3272 1 1
3273 1 1
3274 1 1
3275 1 1
3276 1 1
3277 1 1
3278 1 1
3279 1 1
3280 1 1
3281 1 1
3282 1 1
3283 1 1
3284 1 1
3287 1 1
3288 1 1
3289 1 1
3290 1 1
3291 1 1
3292 1 1
3293 1 1
3294 1 1
3295 1 1
3296 1 1
3297 1 1
3298 1 1
3301 1 1
3302 1 1
3305 1 1
3306 1 1
3307 1 1
3308 0 1
3309 0 1
3310 0 1
3311 1 1
3312 1 1
3313 1 1
3314 1 1
3315 unreachable
3316 unreachable
3319 1 1
3320 1 1


Toggle Coverage for Instance : tb.dut.top_earlgrey
TotalCoveredPercent
Totals 629 559 88.87
Total Bits 2112 1887 89.35
Total Bits 0->1 1056 945 89.49
Total Bits 1->0 1056 942 89.20

Ports 629 559 88.87
Port Bits 2112 1887 89.35
Port Bits 0->1 1056 945 89.49
Port Bits 1->0 1056 942 89.20

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
mio_in_i[46:0] Yes Yes T74,T75,T1 Yes T74,T75,T1 INPUT
mio_out_o[46:0] Yes Yes T1,T82,T83 Yes T1,T82,T83 OUTPUT
mio_oe_o[46:0] Yes Yes T83,T84,T85 Yes T1,T82,T68 OUTPUT
dio_in_i[15:0] Yes Yes T76,T77,T102 Yes T76,T77,T102 INPUT
dio_out_o[11:0] Yes Yes *T76,*T77,*T3 Yes T76,T77,T3 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T71,T72,T73 Yes T71,T72,T73 OUTPUT
dio_oe_o[15:0] Yes Yes T77,T80,T81 Yes T68,T77,T69 OUTPUT
mio_attr_o[0].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].pull_en Yes Yes T86,T87,T88 Yes T95,T96,T97 OUTPUT
mio_attr_o[7].pull_select Yes Yes T86,T87,T88 Yes T95,T96,T97 OUTPUT
mio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[9].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[10].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[12].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
mio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[13].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[14].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[15].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
mio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[16].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[17].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[18].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[19].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[20].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[21].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[22].pull_select Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
mio_attr_o[22].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[22].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[23].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[23].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].pull_en Yes Yes T20,T36,T98 Yes T20,T21,T22 OUTPUT
mio_attr_o[24].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[24].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].pull_en Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
mio_attr_o[25].pull_select Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
mio_attr_o[25].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[25].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[26].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[27].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[28].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[29].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[30].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[31].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[32].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[33].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[34].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[35].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[36].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[37].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[38].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[39].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[40].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[41].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[42].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[43].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[44].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[45].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
mio_attr_o[46].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[0].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
dio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].drive_strength[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
dio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[4].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].pull_en Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[5].pull_select Yes Yes T86,T87,T88 Yes T71,T72,T89 OUTPUT
dio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T86,T88,T91 Yes T86,T88,T91 OUTPUT
dio_attr_o[6].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].input_disable Yes Yes T87,T88,T91 Yes T87,T88,T91 OUTPUT
dio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].drive_strength[0] Yes Yes *T86,*T88,*T91 Yes T86,T88,T91 OUTPUT
dio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T86,T87,T88 Yes T92,T93,T94 OUTPUT
dio_attr_o[10].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T86,T87,T88 Yes T92,T93,T94 OUTPUT
dio_attr_o[11].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].drive_strength[0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].drive_strength[0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[14].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].invert Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].pull_en Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[15].pull_select Yes Yes T86,T87,T88 Yes T89,T73,T90 OUTPUT
dio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].drive_strength[0] Yes Yes *T86,*T87,*T88 Yes T86,T87,T88 OUTPUT
dio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
adc_req_o.pd Yes Yes T148,T154,T155 Yes T148,T154,T155 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T148,T154,T155 Yes T148,T154,T155 OUTPUT
adc_rsp_i.data_valid Yes Yes T148,T154,T155 Yes T148,T154,T155 INPUT
adc_rsp_i.data[9:0] Yes Yes T148,T154,T155 Yes T148,T154,T155 INPUT
ast_edn_req_i.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T4,T5,T19 Yes T4,T5,T19 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T156,T157,T158 Yes T63,T159,T160 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
obs_ctrl_i.obmen[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
ram_1p_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
clk_main_jitter_en_o[3:0] Yes Yes T112,T161,T63 Yes T63,T159,T160 OUTPUT
io_clk_byp_req_o[3:0] No No No OUTPUT
io_clk_byp_ack_i[3:0] No No No INPUT
all_clk_byp_req_o[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 INPUT
hi_speed_sel_o[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
div_step_down_req_i[3:0] Yes Yes T42,T43,T162 Yes T42,T43,T120 INPUT
calib_rdy_i[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T4,T5,T6 Yes T6,T147,T148 INPUT
flash_power_ready_h_i No No Yes T4,T5,T6 INPUT
flash_test_mode_a_io[1:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_rsp_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_fips_o Yes Yes T163,T164,T165 Yes T166,T167,T163 OUTPUT
ast_tl_req_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T27,T29,T30 Yes T27,T29,T30 OUTPUT
ast_tl_req_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
dft_strap_test_o.straps[1:0] No No Yes T103,T104,T105 OUTPUT
dft_strap_test_o.valid Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T76,T77,T3 Yes T76,T77,T3 OUTPUT
usb_dn_pullup_en_o Yes Yes T76,T77,T102 Yes T76,T77,T102 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T6,T17,T20 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T4,T5,T6 Yes T6,T20,T36 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T6,T20,T36 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T6,T147,T148 Yes T6,T147,T148 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T6,T20,T36 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T6,T17,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T42,T43,T168 Yes T4,T5,T6 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T4,T5,T6 Yes T6,T147,T148 INPUT
otp_ext_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T20,T36,T59 Yes T4,T5,T6 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T169,T170,T171 Yes T169,T170,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T169,T170,T172 Yes T169,T170,T171 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T171,T173,T174 Yes T175,T176,T177 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T175,T176,T177 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T171,T173,T172 Yes T172,T178,T176 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T172,T178,T176 Yes T171,T173,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n Yes Yes T179,T171,T173 Yes T179,T180,T176 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p Yes Yes T179,T180,T176 Yes T179,T171,T173 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T171,T173,T172 Yes T172,T178,T175 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T172,T178,T175 Yes T171,T173,T172 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T171,T173,T174 Yes T176,T177,T181 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T176,T177,T181 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T171,T173,T174 Yes T176,T182,T183 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T176,T182,T183 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T171,T173,T174 Yes T157,T158,T177 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T157,T158,T177 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T171,T173,T174 Yes T157,T158,T182 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T157,T158,T182 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T171,T173,T174 Yes T176,T177,T182 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T176,T177,T182 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T171,T173,T174 Yes T176,T177,T181 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T176,T177,T181 Yes T171,T173,T174 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T169,T170,T171 Yes T169,T170,T171 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T179,T171,T173 Yes T179,T171,T173 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T171,T173,T172 Yes T171,T173,T172 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T171,T173,T174 Yes T171,T173,T174 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T168,T184,T185 Yes T4,T5,T6 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
sensor_ctrl_manual_pad_attr_o[0].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_en Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_select Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].input_disable Yes Yes T86,T87,T88 Yes T86,T87,T88 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].drive_strength[3:0] No No No OUTPUT
sck_monitor_o Yes Yes T71,T72,T95 Yes T71,T72,T68 OUTPUT
usbdev_usb_rx_d_i Yes Yes T76,T77,T102 Yes T76,T77,T102 INPUT
usbdev_usb_tx_d_o Yes Yes T76,T77,T3 Yes T76,T77,T3 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T186,T187,T188 Yes T186,T187,T188 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T77,T189,T190 Yes T76,T77,T102 OUTPUT
usbdev_usb_ref_val_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T77,T80,T81 Yes T77,T80,T81 OUTPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clks_ast_o.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T5,*T6,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T20,*T36,*T59 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T20,T36,T59 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Instance : tb.dut.top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 407935536 407935536 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 407935536 407935536 0 0
T4 95755 95755 0 0
T5 251720 251720 0 0
T6 101385 101385 0 0
T17 171968 171968 0 0
T18 267994 267994 0 0
T19 163667 163667 0 0
T20 113601 113601 0 0
T51 271006 271006 0 0
T111 97218 97218 0 0
T112 72094 72094 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%