Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.35 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 550 100.00
Total Bits 6824 6824 100.00
Total Bits 0->1 3412 3412 100.00
Total Bits 1->0 3412 3412 100.00

Ports 550 550 100.00
Port Bits 6824 6824 100.00
Port Bits 0->1 3412 3412 100.00
Port Bits 1->0 3412 3412 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready Yes Yes T23,T25,T137 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] Yes Yes T318,T319,T320 Yes T318,T319,T320 INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T18,T235,T236 Yes T18,T235,T236 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] Yes Yes T18,T235,T236 Yes T18,T235,T236 OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T27,T29,T30 Yes T27,T29,T30 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T29,T11,T210 Yes T29,T11,T210 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T29,T11,T210 Yes T29,T11,T210 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T18,T51,T202 Yes T18,T51,T202 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T26,T27,T41 Yes T26,T27,T41 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T26,T27,T41 Yes T26,T27,T41 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T26,T27,T41 Yes T26,T27,T41 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T26,T27,T41 Yes T26,T27,T41 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] Yes Yes T27,T41,T107 Yes T27,T41,T107 OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T26,T27,T41 Yes T26,T27,T41 OUTPUT
tl_rv_dm__sba_o.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__sba_o.d_source[5:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T26,*T27,*T41 Yes T26,T27,T41 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T26,T27,T41 Yes T26,T27,T41 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] Yes Yes *T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T11,T23,T24 Yes T11,T23,T24 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T11,T23,T25 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__regs_i.d_source[5:0] Yes Yes *T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T11,*T23,*T24 Yes T11,T23,T24 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[5:0] Yes Yes *T26,*T28,*T35 Yes T26,T28,T35 OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T26,T28,T209 Yes T26,T28,T209 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T26,T28,T35 Yes T26,T28,T35 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] Yes Yes T26,T28,T209 Yes T26,T28,T209 INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_rv_dm__mem_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__mem_i.d_source[5:0] Yes Yes *T26,*T28,*T35 Yes T26,T28,T35 INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T5,T6,T19 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T26,T28,T209 Yes T26,T28,T209 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T20,T21,T59 Yes T20,T21,T59 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__rom_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T34,T11,T100 Yes T34,T11,T100 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T413,T127,T414 Yes T413,T127,T414 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] Yes Yes T413,T127,T414 Yes T413,T127,T414 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T34,T11,T100 Yes T34,T11,T100 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T413,T127,T414 Yes T413,T127,T414 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0] Yes Yes *T11,*T23,*T24 Yes T11,T23,T24 OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T413,T127,T414 Yes T413,T127,T414 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T413,T127,T414 Yes T413,T127,T414 INPUT
tl_rom_ctrl__regs_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T413,T127,T414 Yes T413,T127,T414 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] Yes Yes T11,T23,T24 Yes T34,T11,T100 INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T413,T127,T414 Yes T413,T127,T414 INPUT
tl_rom_ctrl__regs_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__regs_i.d_source[5:0] Yes Yes *T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T127,*T415,*T11 Yes T413,T127,T414 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T413,T127,T414 Yes T413,T127,T414 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[2:0] Yes Yes T27,T29,T30 Yes T27,T29,T30 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T5,T285,T50 Yes T5,T285,T50 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_peri_i.d_source[5:0] Yes Yes *T26,*T27,*T28 Yes T26,T27,T28 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[2:0] Yes Yes T71,T199,T200 Yes T71,T199,T200 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T71,T224,T142 Yes T71,T224,T142 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T71,T224,T142 Yes T71,T224,T142 INPUT
tl_spi_host0_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T71,T224,T72 Yes T71,T224,T72 INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0] Yes Yes T71,T224,T142 Yes T71,T224,T142 INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T71,T224,T72 Yes T71,T224,T72 INPUT
tl_spi_host0_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host0_i.d_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T71,*T224,*T72 Yes T71,T224,T72 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T71,T224,T142 Yes T71,T224,T142 INPUT
tl_spi_host1_o.d_ready Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T224,T89,T389 Yes T224,T89,T389 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T224,T89,T389 Yes T224,T89,T389 INPUT
tl_spi_host1_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T224,T89,T389 Yes T224,T89,T389 INPUT
tl_spi_host1_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host1_i.d_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T224,*T89,*T389 Yes T224,T89,T389 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T224,T89,T389 Yes T224,T89,T389 INPUT
tl_usbdev_o.d_ready Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_o.a_user.instr_type[3:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T224,T237,T76 Yes T224,T237,T76 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[5:0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_usbdev_o.a_valid Yes Yes T201,T224,T237 Yes T201,T224,T237 OUTPUT
tl_usbdev_i.a_ready Yes Yes T201,T224,T237 Yes T201,T224,T237 INPUT
tl_usbdev_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 INPUT
tl_usbdev_i.d_user.rsp_intg[6:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T201,T224,T237 Yes T201,T224,T237 INPUT
tl_usbdev_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_usbdev_i.d_source[5:0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T201,*T224,*T237 Yes T201,T224,T237 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T201,T224,T237 Yes T201,T224,T237 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_flash_ctrl__core_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__core_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] Yes Yes *T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T27,T23,T24 Yes T27,T23,T24 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T27,T23,T25 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_error Yes Yes T23,T24,T137 Yes T23,T24,T25 INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T27,T23,T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T137 INPUT
tl_flash_ctrl__prim_i.d_source[5:0] Yes Yes *T27,T23,T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T27,T23,T24 Yes T27,T23,T24 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__mem_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] Yes Yes *T23,*T24,*T25 Yes T23,T24,T25 INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_o.a_user.instr_type[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[2:0] Yes Yes T293,T294,T295 Yes T293,T294,T295 OUTPUT
tl_hmac_o.a_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_hmac_i.a_ready Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_hmac_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_hmac_i.d_user.rsp_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_hmac_i.d_data[31:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_hmac_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_hmac_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T20,*T21,*T22 Yes T20,T21,T22 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_kmac_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T111,T161,T62 Yes T111,T161,T62 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 OUTPUT
tl_kmac_o.a_user.instr_type[3:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T111,T161,T62 Yes T111,T161,T62 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[2:0] Yes Yes T111,T161,T219 Yes T111,T161,T219 OUTPUT
tl_kmac_o.a_valid Yes Yes T111,T37,T161 Yes T111,T37,T161 OUTPUT
tl_kmac_i.a_ready Yes Yes T111,T37,T161 Yes T111,T37,T161 INPUT
tl_kmac_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 INPUT
tl_kmac_i.d_user.rsp_intg[6:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 INPUT
tl_kmac_i.d_data[31:0] Yes Yes T111,T37,T161 Yes T111,T37,T161 INPUT
tl_kmac_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_kmac_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T111,*T37,*T161 Yes T111,T37,T161 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T111,T37,T161 Yes T111,T37,T161 INPUT
tl_aes_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T4,T721,T164 Yes T4,T721,T164 OUTPUT
tl_aes_o.a_user.cmd_intg[6:0] Yes Yes T4,T721,T164 Yes T4,T721,T164 OUTPUT
tl_aes_o.a_user.instr_type[3:0] Yes Yes T4,T166,T314 Yes T4,T166,T314 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T4,T721,T164 Yes T4,T721,T164 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T4,T166,T314 Yes T4,T166,T314 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_aes_o.a_valid Yes Yes T4,T166,T314 Yes T4,T166,T314 OUTPUT
tl_aes_i.a_ready Yes Yes T4,T166,T314 Yes T4,T166,T314 INPUT
tl_aes_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T4,T166,T314 Yes T4,T166,T314 INPUT
tl_aes_i.d_user.rsp_intg[6:0] Yes Yes T4,T166,T721 Yes T4,T166,T721 INPUT
tl_aes_i.d_data[31:0] Yes Yes T4,T166,T314 Yes T4,T166,T314 INPUT
tl_aes_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_aes_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T4,*T166,*T314 Yes T4,T166,T314 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T4,T166,T314 Yes T4,T166,T314 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_entropy_src_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T166,*T167,*T163 Yes T21,T22,T166 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_csrng_i.d_user.rsp_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_csrng_i.d_data[31:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_csrng_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T166,*T167,*T163 Yes T166,T167,T163 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T137 INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_edn0_i.d_user.rsp_intg[6:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_edn0_i.d_data[31:0] Yes Yes T5,T6,T19 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_edn0_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T166,*T167,*T163 Yes T166,T167,T163 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_o.a_user.instr_type[3:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_edn1_o.a_valid Yes Yes T166,T167,T163 Yes T166,T167,T163 OUTPUT
tl_edn1_i.a_ready Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_edn1_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_edn1_i.d_user.rsp_intg[6:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_edn1_i.d_data[31:0] Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_edn1_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_edn1_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T166,*T167,*T163 Yes T166,T167,T163 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T166,T167,T163 Yes T166,T167,T163 INPUT
tl_rv_plic_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T5,T17,T18 Yes T5,T17,T18 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_rv_plic_i.d_error Yes Yes T23,T24,T137 Yes T23,T24,T25 INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T5,T18,T51 Yes T5,T18,T51 INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_rv_plic_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_plic_i.d_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T5,*T17,*T18 Yes T5,T17,T18 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_otbn_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_o.a_user.instr_type[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[5:0] Yes Yes *T29,*T30,*T210 Yes T29,T30,T210 OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_otbn_o.a_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_otbn_i.a_ready Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_otbn_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_otbn_i.d_user.rsp_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_otbn_i.d_data[31:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_otbn_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_otbn_i.d_source[5:0] Yes Yes *T29,*T30,*T210 Yes T29,T30,T210 INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T20,*T21,*T22 Yes T20,T21,T22 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_keymgr_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_o.a_user.instr_type[3:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_keymgr_o.a_valid Yes Yes T21,T22,T37 Yes T21,T22,T37 OUTPUT
tl_keymgr_i.a_ready Yes Yes T21,T22,T37 Yes T21,T22,T37 INPUT
tl_keymgr_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T37,T62,T138 Yes T37,T62,T138 INPUT
tl_keymgr_i.d_user.rsp_intg[6:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T21,T22,T37 Yes T21,T22,T37 INPUT
tl_keymgr_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_keymgr_i.d_source[5:0] Yes Yes *T27,*T23,*T24 Yes T27,T23,T24 INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T21,*T22,*T37 Yes T21,T22,T37 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T21,T22,T37 Yes T21,T22,T37 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0] Yes Yes *T11,*T23,*T24 Yes T11,T23,T24 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T11,T23,T24 Yes T11,T23,T24 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T5,T17,T18 Yes T5,T17,T18 INPUT
tl_rv_core_ibex__cfg_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0] Yes Yes *T11,*T23,*T24 Yes T11,T23,T24 INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T5,T6,T19 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_sram_ctrl_main__regs_i.d_error Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T66,T67,T209 Yes T66,T67,T209 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] Yes Yes T20,T36,T98 Yes T20,T21,T22 INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T20,T36,T98 Yes T20,T21,T22 INPUT
tl_sram_ctrl_main__regs_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0] Yes Yes *T209,*T23,*T24 Yes T209,T23,T24 INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T66,*T119,*T149 Yes T465,T66,T119 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T20,T21,T22 Yes T20,T21,T22 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T5,T6,T19 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%