Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.35			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T5,T285,T50	Yes	T5,T285,T50	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_uart0_i.d_error	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T20,T36,T232	Yes	T20,T36,T232	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T36,T232	Yes	T20,T21,T22	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T20,T36,T232	Yes	T20,T21,T22	INPUT
tl_uart0_i.d_sink	Yes	Yes	T23,T24,T137	Yes	T23,T24,T137	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T137	Yes	T23,T24,T25	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T23,T24,T137	Yes	T23,T24,T137	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T20,*T36,*T232	Yes	T20,T36,T232	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T226,T128,T129	Yes	T226,T128,T129	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T226,T128,T129	Yes	T226,T128,T129	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T142,T226,T143	Yes	T142,T226,T143	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T142,T226,T143	Yes	T142,T226,T143	INPUT
tl_uart1_i.d_error	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T226,T128,T129	Yes	T226,T128,T129	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T142,T226,T143	Yes	T142,T226,T143	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T142,T226,T143	Yes	T142,T226,T143	INPUT
tl_uart1_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T226,*T128,*T129	Yes	T226,T128,T129	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T142,T226,T143	Yes	T142,T226,T143	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T191,T142,T192	Yes	T191,T142,T192	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T191,T142,T192	Yes	T191,T142,T192	INPUT
tl_uart2_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T191,T192,T193	Yes	T191,T192,T193	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T191,T142,T192	Yes	T191,T142,T192	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T191,T142,T192	Yes	T191,T142,T192	INPUT
tl_uart2_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T191,*T192,*T193	Yes	T191,T192,T193	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T191,T142,T192	Yes	T191,T142,T192	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T256	Yes	T74,T75,T256	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T74,T75,T256	Yes	T74,T75,T256	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T142,T74,T75	Yes	T142,T74,T75	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T142,T74,T75	Yes	T142,T74,T75	INPUT
tl_uart3_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T74,T75,T256	Yes	T74,T75,T256	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T142,T74,T75	Yes	T142,T74,T75	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T142,T74,T75	Yes	T142,T74,T75	INPUT
tl_uart3_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T256	Yes	T74,T75,T256	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T142,T74,T75	Yes	T142,T74,T75	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T224,T225,T27	Yes	T224,T225,T27	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T224,T225,T27	Yes	T224,T225,T27	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c0_i.d_error	Yes	Yes	T23,T25,T137	Yes	T23,T25,T137	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T225,T27,T264	Yes	T225,T27,T264	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T224,*T225,*T27	Yes	T224,T225,T27	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T224,T27,T389	Yes	T224,T27,T389	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T224,T27,T389	Yes	T224,T27,T389	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c1_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T27,T257,T269	Yes	T27,T257,T269	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T224,*T27,*T389	Yes	T224,T27,T389	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T224,T229,T27	Yes	T224,T229,T27	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T224,T229,T27	Yes	T224,T229,T27	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c2_i.d_error	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T229,T27,T272	Yes	T229,T27,T272	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T224,*T229,*T27	Yes	T224,T229,T27	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T224,T142,T143	Yes	T224,T142,T143	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T139,T140,T277	Yes	T139,T140,T277	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T139,T140,T277	Yes	T139,T140,T277	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T139,T34,T140	Yes	T139,T34,T140	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T139,T34,T140	Yes	T139,T34,T140	INPUT
tl_pattgen_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T139,T140,T277	Yes	T139,T140,T277	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T139,T140,T277	Yes	T139,T34,T140	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T139,T140,T277	Yes	T139,T34,T140	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T139,*T140,*T277	Yes	T139,T140,T277	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T139,T34,T140	Yes	T139,T34,T140	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T11,T23,*T24	Yes	T11,T23,T24	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T227,*T228,*T407	Yes	T227,T228,T407	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T227,T228,T407	Yes	T227,T228,T407	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T27,T82,T83	Yes	T27,T82,T83	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T82,T83	Yes	T1,T27,T82	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T27,T82,T83	Yes	T1,T27,T82	INPUT
tl_gpio_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T19	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	INPUT
tl_spi_device_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T209,*T23,*T24	Yes	T209,T23,T24	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T71,*T224,*T72	Yes	T71,T224,T72	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T71,T224,T72	Yes	T71,T224,T72	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T321,T322,T139	Yes	T321,T322,T139	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T209,*T23,*T24	Yes	T209,T23,T24	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T321,*T117,*T322	Yes	T321,T117,T322	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T321,T117,T322	Yes	T321,T117,T322	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T201	Yes	T6,T17,T201	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T17,*T20	Yes	T6,T17,T20	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T6,T17,T20	Yes	T6,T17,T20	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T111,T112,T235	Yes	T111,T112,T235	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T111,T112,T161	Yes	T111,T112,T161	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T111,T112,T235	Yes	T111,T112,T235	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T111,*T112,*T235	Yes	T111,T112,T235	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T137	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T37,*T62,*T138	Yes	T37,T62,T138	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T19	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T19	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T19	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T33	Yes	T31,T34,T32	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T26,*T28,*T35	Yes	T26,T28,T35	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T20,*T36,*T37	Yes	T20,T21,T22	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T179,T169,T170	Yes	T179,T169,T170	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T179,T169,T170	Yes	T179,T169,T170	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T209,*T23,*T24	Yes	T209,T23,T24	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T19	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T18	Yes	T5,T17,T18	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T119,T149,T209	Yes	T119,T149,T209	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T36,T98	Yes	T20,T21,T22	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T20,T36,T98	Yes	T20,T21,T22	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T209,*T23,*T24	Yes	T209,T23,T24	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T119,*T149,*T209	Yes	T465,T119,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T5,T6,T19	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T5,T6,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T5,T6,T19	Yes	T5,T6,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T29,*T30,*T210	Yes	T29,T30,T210	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T23,T24,T137	Yes	T23,T24,T25	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T18	Yes	T5,T17,T18	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T202,T275	Yes	T6,T202,T275	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T209,*T23,*T24	Yes	T209,T23,T24	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T6,*T202,*T275	Yes	T6,T202,T194	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T6,T202,T194	Yes	T6,T202,T194	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T27,*T23,*T24	Yes	T27,T23,T24	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T148,*T154,*T155	Yes	T148,T154,T155	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T148,T154,T155	Yes	T148,T154,T155	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T23,*T24,*T25	Yes	T23,T24,T25	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range