Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.93 97.65 89.29 100.00 100.00 72.73 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 802549274 4069 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 802549274 4069 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 802549274 4069 0 0
T4 93640 1 0 0
T5 249665 4 0 0
T6 100839 4 0 0
T17 152411 2 0 0
T18 265023 4 0 0
T19 160818 2 0 0
T20 113222 14 0 0
T22 121622 0 0 0
T36 838867 0 0 0
T37 465053 0 0 0
T51 268782 4 0 0
T71 227083 0 0 0
T111 94323 1 0 0
T112 70683 1 0 0
T151 87634 5 0 0
T152 0 8 0 0
T153 0 11 0 0
T166 166533 0 0 0
T202 583286 0 0 0
T224 95134 0 0 0
T238 150005 0 0 0
T285 281292 0 0 0
T307 0 9 0 0
T308 0 8 0 0
T309 0 8 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 802549274 4069 0 0
T4 93640 1 0 0
T5 249665 4 0 0
T6 100839 4 0 0
T17 152411 2 0 0
T18 265023 4 0 0
T19 160818 2 0 0
T20 113222 14 0 0
T22 121622 0 0 0
T36 838867 0 0 0
T37 465053 0 0 0
T51 268782 4 0 0
T71 227083 0 0 0
T111 94323 1 0 0
T112 70683 1 0 0
T151 87634 5 0 0
T152 0 8 0 0
T153 0 11 0 0
T166 166533 0 0 0
T202 583286 0 0 0
T224 95134 0 0 0
T238 150005 0 0 0
T285 281292 0 0 0
T307 0 9 0 0
T308 0 8 0 0
T309 0 8 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 401274637 49 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 401274637 49 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 401274637 49 0 0
T22 121622 0 0 0
T36 838867 0 0 0
T37 465053 0 0 0
T71 227083 0 0 0
T151 87634 5 0 0
T152 0 8 0 0
T153 0 11 0 0
T166 166533 0 0 0
T202 583286 0 0 0
T224 95134 0 0 0
T238 150005 0 0 0
T285 281292 0 0 0
T307 0 9 0 0
T308 0 8 0 0
T309 0 8 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 401274637 49 0 0
T22 121622 0 0 0
T36 838867 0 0 0
T37 465053 0 0 0
T71 227083 0 0 0
T151 87634 5 0 0
T152 0 8 0 0
T153 0 11 0 0
T166 166533 0 0 0
T202 583286 0 0 0
T224 95134 0 0 0
T238 150005 0 0 0
T285 281292 0 0 0
T307 0 9 0 0
T308 0 8 0 0
T309 0 8 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 401274637 4020 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 401274637 4020 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 401274637 4020 0 0
T4 93640 1 0 0
T5 249665 4 0 0
T6 100839 4 0 0
T17 152411 2 0 0
T18 265023 4 0 0
T19 160818 2 0 0
T20 113222 14 0 0
T51 268782 4 0 0
T111 94323 1 0 0
T112 70683 1 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 401274637 4020 0 0
T4 93640 1 0 0
T5 249665 4 0 0
T6 100839 4 0 0
T17 152411 2 0 0
T18 265023 4 0 0
T19 160818 2 0 0
T20 113222 14 0 0
T51 268782 4 0 0
T111 94323 1 0 0
T112 70683 1 0 0

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