Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.69	97.65	89.29	98.77		100.00	72.73

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	91.93	97.65	89.29	100.00		100.00	72.73

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.93	97.65	89.29	100.00		100.00	72.73

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.77	97.76	95.75	98.81		98.66	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.35			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	87.50			87.50
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.21	98.85	98.40			99.58	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	83	97.65
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	1	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T119,T149,T310
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T311,T312,T313
1	0	Covered	T20,T201,T314

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T201,T314

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T11,T100

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T100,T101
1	0	Covered	T4,T5,T6
1	1	Covered	T142,T38,T99

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T100,T101

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T100,T101

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T20,T201,T314
0	1	0	Covered	T119,T149,T310
1	0	0	Covered	T315,T316,T317

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T19
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T23,T25,T137	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T318,T319,T320	Yes	T318,T319,T320	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T18,T235,T236	Yes	T18,T235,T236	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T235,T236	Yes	T18,T235,T236	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T18,T51,T202	Yes	T18,T51,T202	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T239,T240,T241	Yes	T239,T240,T241	INPUT
irq_timer_i	Yes	Yes	T321,T322,T139	Yes	T321,T322,T139	INPUT
irq_external_i	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_tx_i.esc_n	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_tx_i.esc_p	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_rx_o.resp_n	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
nmi_wdog_i	Yes	Yes	T202,T142,T275	Yes	T202,T142,T275	INPUT
debug_req_i	Yes	Yes	T26,T28,T35	Yes	T26,T28,T35	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T23,*T24,*T137	Yes	T23,T24,T137	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T11,T23,T24	Yes	T11,T23,T24	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T5,T6,T19	Yes	T5,T6,T19	INPUT
edn_i.edn_fips	Yes	Yes	T166,T164,T165	Yes	T166,T167,T164	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T151,T66,T152	Yes	T151,T66,T152	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T18,T51,T20	Yes	T4,T17,T18	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
icache_otp_key_i.ack	Yes	Yes	T151,T152,T153	Yes	T151,T152,T153	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T44,T323,T45	Yes	T44,T323,T45	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T142,T38,T99	Yes	T142,T38,T99	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T44,T119,T149	Yes	T44,T119,T149	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T146	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T44,T45,T146	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T44,T323,T45	Yes	T44,T323,T45	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T142,T38,T99	Yes	T142,T38,T99	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T44,T119,T149	Yes	T324,T44,T119	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T44,T45,T46	Yes	T324,T44,T45	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T201,T314
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T311,T312,T313
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T17,T18
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	16	72.73
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	16	72.73

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	401274637	7	0	0
FpvSecCmIbexFetchEnable1_A	401274637	19942933	0	58
FpvSecCmIbexFetchEnable2_A	401274637	56070357	0	64
FpvSecCmIbexFetchEnable3Rev_A	401274637	340683026	0	1830
FpvSecCmIbexFetchEnable3_A	401274637	340684732	0	1763
FpvSecCmIbexInstrIntgErrCheck_A	401274637	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	401274637	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	401274637	0	0	0
FpvSecCmIbexPcMismatchCheck_A	401274637	0	0	0
FpvSecCmIbexRfEccErrCheck_A	401274637	1	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	401274637	0	0	0
FpvSecCmRegWeOnehotCheck_A	401274637	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	401274637	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	401274637	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	401274637	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	926	926	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	926	926	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	401274637	200	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	401274637	199	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	7	0	0
T264	313240	0	0	0
T286	285536	0	0	0
T295	83776	0	0	0
T311	0	1	0	0
T312	0	1	0	0
T313	0	1	0	0
T325	39944	1	0	0
T326	0	1	0	0
T327	0	1	0	0
T328	0	1	0	0
T329	87810	0	0	0
T330	220648	0	0	0
T331	135879	0	0	0
T332	158923	0	0	0
T333	83797	0	0	0
T334	242979	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	19942933	0	58
T4	93640	9927	0	0
T5	249665	40607	0	0
T6	100839	49627	0	0
T17	152411	9931	0	0
T18	265023	40987	0	0
T19	160818	19858	0	0
T20	113222	10068	0	2
T27	0	0	0	2
T29	0	0	0	2
T30	0	0	0	2
T36	0	0	0	2
T51	268782	40611	0	0
T98	0	0	0	2
T111	94323	9927	0	0
T112	70683	9927	0	0
T209	0	0	0	2
T335	0	0	0	2
T336	0	0	0	2
T337	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	56070357	0	64
T4	93640	34775	0	0
T5	249665	69554	0	0
T6	100839	173894	0	0
T17	152411	38803	0	0
T18	265023	69555	0	0
T19	160818	69555	0	0
T20	113222	34924	0	2
T27	0	0	0	2
T29	0	0	0	2
T30	0	0	0	2
T36	0	0	0	2
T51	268782	69554	0	0
T98	0	0	0	2
T111	94323	34775	0	0
T112	70683	34775	0	0
T127	0	0	0	2
T335	0	0	0	2
T336	0	0	0	2
T337	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	340683026	0	1830
T4	93640	58804	0	2
T5	249665	159242	0	2
T6	100839	834221	0	2
T17	152411	113545	0	2
T18	265023	174217	0	2
T19	160818	91133	0	2
T20	113222	109719	0	2
T51	268782	178352	0	2
T111	94323	59487	0	2
T112	70683	35847	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	340684732	0	1763
T4	93640	58805	0	2
T5	249665	159244	0	2
T6	100839	834224	0	2
T17	152411	113548	0	2
T18	265023	174219	0	2
T19	160818	91135	0	2
T20	113222	109719	0	0
T21	0	0	0	2
T51	268782	178354	0	2
T111	94323	59488	0	2
T112	70683	35848	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	76	0	0
T198	520392	0	0	0
T290	71049	0	0	0
T338	277431	76	0	0
T339	148429	0	0	0
T340	343393	0	0	0
T341	280357	0	0	0
T342	237945	0	0	0
T343	167239	0	0	0
T344	249097	0	0	0
T345	168889	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	590	0	0
T76	85468	0	0	0
T82	102839	0	0	0
T119	214236	31	0	0
T120	190514	0	0	0
T121	123346	0	0	0
T122	137784	0	0	0
T149	0	32	0	0
T310	0	100	0	0
T345	0	100	0	0
T346	0	1	0	0
T347	0	1	0	0
T348	0	32	0	0
T349	0	31	0	0
T350	0	32	0	0
T351	0	32	0	0
T352	262773	0	0	0
T353	267645	0	0	0
T354	130750	0	0	0
T355	155407	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	1	0	0
T264	313240	0	0	0
T286	285536	0	0	0
T295	83776	0	0	0
T325	39944	1	0	0
T329	87810	0	0	0
T330	220648	0	0	0
T331	135879	0	0	0
T332	158923	0	0	0
T333	83797	0	0	0
T334	242979	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	6	0	0
T83	185111	0	0	0
T220	150335	0	0	0
T315	137171	1	0	0
T316	0	1	0	0
T317	0	1	0	0
T356	0	1	0	0
T357	0	1	0	0
T358	0	1	0	0
T359	83680	0	0	0
T360	128795	0	0	0
T361	152702	0	0	0
T362	108775	0	0	0
T363	194176	0	0	0
T364	347800	0	0	0
T365	208787	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	200	0	0
T22	121622	0	0	0
T36	838867	0	0	0
T37	465053	0	0	0
T71	227083	0	0	0
T151	87634	20	0	0
T152	0	33	0	0
T153	0	45	0	0
T166	166533	0	0	0
T202	583286	0	0	0
T224	95134	0	0	0
T238	150005	0	0	0
T285	281292	0	0	0
T307	0	38	0	0
T308	0	32	0	0
T309	0	32	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	199	0	0
T22	121622	0	0	0
T36	838867	0	0	0
T37	465053	0	0	0
T66	0	16	0	0
T67	0	16	0	0
T71	227083	0	0	0
T151	87634	5	0	0
T152	0	42	0	0
T153	0	11	0	0
T166	166533	0	0	0
T202	583286	0	0	0
T224	95134	0	0	0
T238	150005	0	0	0
T285	281292	0	0	0
T307	0	9	0	0
T308	0	42	0	0
T309	0	42	0	0
T366	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	83	97.65
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	1	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T119,T149,T310
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T311,T312,T313
1	0	Covered	T20,T201,T314

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T20,T201,T314

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T11,T100

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T100,T101
1	0	Covered	T4,T5,T6
1	1	Covered	T142,T38,T99

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T100,T101

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T142,T38,T99
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T100,T101

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T20,T201,T314
0	1	0	Covered	T119,T149,T310
1	0	0	Covered	T315,T316,T317

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T19
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T23,T25,T137	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T318,T319,T320	Yes	T318,T319,T320	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T18,T235,T236	Yes	T18,T235,T236	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T235,T236	Yes	T18,T235,T236	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T27,T29,T30	Yes	T27,T29,T30	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T29,T11,T210	Yes	T29,T11,T210	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T18,T51,T202	Yes	T18,T51,T202	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T239,T240,T241	Yes	T239,T240,T241	INPUT
irq_timer_i	Yes	Yes	T321,T322,T139	Yes	T321,T322,T139	INPUT
irq_external_i	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_tx_i.esc_n	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_tx_i.esc_p	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
esc_rx_o.resp_n	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
nmi_wdog_i	Yes	Yes	T202,T142,T275	Yes	T202,T142,T275	INPUT
debug_req_i	Yes	Yes	T26,T28,T35	Yes	T26,T28,T35	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	*T23,*T24,*T137	Yes	T23,T24,T137	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T11,T23,T24	Yes	T11,T23,T24	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	*T11,*T23,*T24	Yes	T11,T23,T24	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T5,T6,T19	Yes	T5,T6,T19	INPUT
edn_i.edn_fips	Yes	Yes	T166,T164,T165	Yes	T166,T167,T164	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T151,T66,T152	Yes	T151,T66,T152	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T5,T6,T19	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T18,T51,T20	Yes	T4,T17,T18	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
icache_otp_key_i.ack	Yes	Yes	T151,T152,T153	Yes	T151,T152,T153	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T44,T323,T45	Yes	T44,T323,T45	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T142,T38,T99	Yes	T142,T38,T99	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T44,T119,T149	Yes	T44,T119,T149	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T146	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T44,T45,T146	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T44,T323,T45	Yes	T44,T323,T45	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T142,T38,T99	Yes	T142,T38,T99	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T44,T119,T149	Yes	T324,T44,T119	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T44,T45,T46	Yes	T324,T44,T45	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T201,T314
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T311,T312,T313
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T17,T18
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	16	72.73
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	16	72.73

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	401274637	7	0	0
FpvSecCmIbexFetchEnable1_A	401274637	19942933	0	58
FpvSecCmIbexFetchEnable2_A	401274637	56070357	0	64
FpvSecCmIbexFetchEnable3Rev_A	401274637	340683026	0	1830
FpvSecCmIbexFetchEnable3_A	401274637	340684732	0	1763
FpvSecCmIbexInstrIntgErrCheck_A	401274637	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	401274637	590	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	401274637	0	0	0
FpvSecCmIbexPcMismatchCheck_A	401274637	0	0	0
FpvSecCmIbexRfEccErrCheck_A	401274637	1	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	401274637	0	0	0
FpvSecCmRegWeOnehotCheck_A	401274637	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	401274637	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	401274637	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	401274637	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	926	926	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	926	926	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	926	926	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	401274637	200	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	401274637	199	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	7	0	0
T264	313240	0	0	0
T286	285536	0	0	0
T295	83776	0	0	0
T311	0	1	0	0
T312	0	1	0	0
T313	0	1	0	0
T325	39944	1	0	0
T326	0	1	0	0
T327	0	1	0	0
T328	0	1	0	0
T329	87810	0	0	0
T330	220648	0	0	0
T331	135879	0	0	0
T332	158923	0	0	0
T333	83797	0	0	0
T334	242979	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	19942933	0	58
T4	93640	9927	0	0
T5	249665	40607	0	0
T6	100839	49627	0	0
T17	152411	9931	0	0
T18	265023	40987	0	0
T19	160818	19858	0	0
T20	113222	10068	0	2
T27	0	0	0	2
T29	0	0	0	2
T30	0	0	0	2
T36	0	0	0	2
T51	268782	40611	0	0
T98	0	0	0	2
T111	94323	9927	0	0
T112	70683	9927	0	0
T209	0	0	0	2
T335	0	0	0	2
T336	0	0	0	2
T337	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	56070357	0	64
T4	93640	34775	0	0
T5	249665	69554	0	0
T6	100839	173894	0	0
T17	152411	38803	0	0
T18	265023	69555	0	0
T19	160818	69555	0	0
T20	113222	34924	0	2
T27	0	0	0	2
T29	0	0	0	2
T30	0	0	0	2
T36	0	0	0	2
T51	268782	69554	0	0
T98	0	0	0	2
T111	94323	34775	0	0
T112	70683	34775	0	0
T127	0	0	0	2
T335	0	0	0	2
T336	0	0	0	2
T337	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	340683026	0	1830
T4	93640	58804	0	2
T5	249665	159242	0	2
T6	100839	834221	0	2
T17	152411	113545	0	2
T18	265023	174217	0	2
T19	160818	91133	0	2
T20	113222	109719	0	2
T51	268782	178352	0	2
T111	94323	59487	0	2
T112	70683	35847	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	340684732	0	1763
T4	93640	58805	0	2
T5	249665	159244	0	2
T6	100839	834224	0	2
T17	152411	113548	0	2
T18	265023	174219	0	2
T19	160818	91135	0	2
T20	113222	109719	0	0
T21	0	0	0	2
T51	268782	178354	0	2
T111	94323	59488	0	2
T112	70683	35848	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	76	0	0
T198	520392	0	0	0
T290	71049	0	0	0
T338	277431	76	0	0
T339	148429	0	0	0
T340	343393	0	0	0
T341	280357	0	0	0
T342	237945	0	0	0
T343	167239	0	0	0
T344	249097	0	0	0
T345	168889	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	590	0	0
T76	85468	0	0	0
T82	102839	0	0	0
T119	214236	31	0	0
T120	190514	0	0	0
T121	123346	0	0	0
T122	137784	0	0	0
T149	0	32	0	0
T310	0	100	0	0
T345	0	100	0	0
T346	0	1	0	0
T347	0	1	0	0
T348	0	32	0	0
T349	0	31	0	0
T350	0	32	0	0
T351	0	32	0	0
T352	262773	0	0	0
T353	267645	0	0	0
T354	130750	0	0	0
T355	155407	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	1	0	0
T264	313240	0	0	0
T286	285536	0	0	0
T295	83776	0	0	0
T325	39944	1	0	0
T329	87810	0	0	0
T330	220648	0	0	0
T331	135879	0	0	0
T332	158923	0	0	0
T333	83797	0	0	0
T334	242979	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	6	0	0
T83	185111	0	0	0
T220	150335	0	0	0
T315	137171	1	0	0
T316	0	1	0	0
T317	0	1	0	0
T356	0	1	0	0
T357	0	1	0	0
T358	0	1	0	0
T359	83680	0	0	0
T360	128795	0	0	0
T361	152702	0	0	0
T362	108775	0	0	0
T363	194176	0	0	0
T364	347800	0	0	0
T365	208787	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T51	1	1	0	0
T111	1	1	0	0
T112	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	200	0	0
T22	121622	0	0	0
T36	838867	0	0	0
T37	465053	0	0	0
T71	227083	0	0	0
T151	87634	20	0	0
T152	0	33	0	0
T153	0	45	0	0
T166	166533	0	0	0
T202	583286	0	0	0
T224	95134	0	0	0
T238	150005	0	0	0
T285	281292	0	0	0
T307	0	38	0	0
T308	0	32	0	0
T309	0	32	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401274637	199	0	0
T22	121622	0	0	0
T36	838867	0	0	0
T37	465053	0	0	0
T66	0	16	0	0
T67	0	16	0	0
T71	227083	0	0	0
T151	87634	5	0	0
T152	0	42	0	0
T153	0	11	0	0
T166	166533	0	0	0
T202	583286	0	0	0
T224	95134	0	0	0
T238	150005	0	0	0
T285	281292	0	0	0
T307	0	9	0	0
T308	0	42	0	0
T309	0	42	0	0
T366	0	16	0	0