| T325 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1824418012 |
|
|
May 26 04:11:34 PM PDT 24 |
May 26 04:13:36 PM PDT 24 |
2097744416 ps |
| T329 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3385524451 |
|
|
May 26 04:15:13 PM PDT 24 |
May 26 04:20:50 PM PDT 24 |
3493732704 ps |
| T330 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4070445288 |
|
|
May 26 04:20:33 PM PDT 24 |
May 26 04:29:32 PM PDT 24 |
5221495136 ps |
| T331 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345824567 |
|
|
May 26 04:21:20 PM PDT 24 |
May 26 04:27:42 PM PDT 24 |
3307309704 ps |
| T332 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3561320877 |
|
|
May 26 04:16:49 PM PDT 24 |
May 26 04:25:25 PM PDT 24 |
4532243156 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2313098889 |
|
|
May 26 03:57:55 PM PDT 24 |
May 26 04:01:47 PM PDT 24 |
3303045287 ps |
| T334 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.295900350 |
|
|
May 26 04:12:45 PM PDT 24 |
May 26 04:23:58 PM PDT 24 |
4462406300 ps |
| T264 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3672230017 |
|
|
May 26 03:53:37 PM PDT 24 |
May 26 04:07:45 PM PDT 24 |
5194019992 ps |
| T286 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1182312696 |
|
|
May 26 04:20:38 PM PDT 24 |
May 26 04:31:02 PM PDT 24 |
4977629140 ps |
| T295 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2888356709 |
|
|
May 26 04:10:46 PM PDT 24 |
May 26 04:14:36 PM PDT 24 |
2950003840 ps |
| T931 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3997150053 |
|
|
May 26 04:07:25 PM PDT 24 |
May 26 04:50:30 PM PDT 24 |
11493205001 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3354848284 |
|
|
May 26 03:49:31 PM PDT 24 |
May 26 04:30:27 PM PDT 24 |
13541732792 ps |
| T932 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1873050518 |
|
|
May 26 04:04:10 PM PDT 24 |
May 26 04:11:31 PM PDT 24 |
3436821620 ps |
| T933 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.4117115375 |
|
|
May 26 03:50:45 PM PDT 24 |
May 26 03:53:34 PM PDT 24 |
2124606744 ps |
| T827 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1909206605 |
|
|
May 26 04:15:30 PM PDT 24 |
May 26 04:24:29 PM PDT 24 |
5251743162 ps |
| T389 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.611085089 |
|
|
May 26 03:57:37 PM PDT 24 |
May 26 04:02:12 PM PDT 24 |
2705831992 ps |
| T466 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4071121462 |
|
|
May 26 04:03:57 PM PDT 24 |
May 26 05:01:10 PM PDT 24 |
24890065053 ps |
| T934 |
/workspace/coverage/default/0.rom_keymgr_functest.3627334854 |
|
|
May 26 03:52:49 PM PDT 24 |
May 26 04:02:02 PM PDT 24 |
3953454072 ps |
| T301 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.1823161629 |
|
|
May 26 04:18:14 PM PDT 24 |
May 26 04:29:42 PM PDT 24 |
6234050200 ps |
| T935 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3301578197 |
|
|
May 26 04:16:15 PM PDT 24 |
May 26 05:07:46 PM PDT 24 |
14567132938 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2490590316 |
|
|
May 26 04:08:20 PM PDT 24 |
May 26 05:15:27 PM PDT 24 |
18157206186 ps |
| T937 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1239398651 |
|
|
May 26 04:17:27 PM PDT 24 |
May 26 04:52:11 PM PDT 24 |
10700267128 ps |
| T938 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.939640224 |
|
|
May 26 03:54:20 PM PDT 24 |
May 26 04:04:43 PM PDT 24 |
4108299402 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.1238592744 |
|
|
May 26 03:53:40 PM PDT 24 |
May 26 03:57:12 PM PDT 24 |
3116140968 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2747280786 |
|
|
May 26 04:09:52 PM PDT 24 |
May 26 04:14:46 PM PDT 24 |
3085521819 ps |
| T716 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1390736600 |
|
|
May 26 04:21:59 PM PDT 24 |
May 26 04:32:47 PM PDT 24 |
5074087254 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.35315516 |
|
|
May 26 03:54:56 PM PDT 24 |
May 26 04:06:57 PM PDT 24 |
4539696616 ps |
| T315 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351355758 |
|
|
May 26 04:22:18 PM PDT 24 |
May 26 04:28:11 PM PDT 24 |
4119637706 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2195617464 |
|
|
May 26 04:02:30 PM PDT 24 |
May 26 04:07:51 PM PDT 24 |
3192138874 ps |
| T360 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206098094 |
|
|
May 26 04:25:27 PM PDT 24 |
May 26 04:31:36 PM PDT 24 |
3688277336 ps |
| T220 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1667577482 |
|
|
May 26 04:09:24 PM PDT 24 |
May 26 04:15:34 PM PDT 24 |
3048219592 ps |
| T361 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.55888283 |
|
|
May 26 04:11:17 PM PDT 24 |
May 26 04:19:46 PM PDT 24 |
3227369496 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.645261332 |
|
|
May 26 04:09:33 PM PDT 24 |
May 26 04:14:42 PM PDT 24 |
2960239650 ps |
| T363 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1153053810 |
|
|
May 26 03:48:48 PM PDT 24 |
May 26 03:58:29 PM PDT 24 |
7970271416 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_gpio.1572847085 |
|
|
May 26 03:55:07 PM PDT 24 |
May 26 04:01:43 PM PDT 24 |
3880255484 ps |
| T364 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1699701509 |
|
|
May 26 04:09:18 PM PDT 24 |
May 26 04:23:37 PM PDT 24 |
5033882128 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2070128122 |
|
|
May 26 03:46:27 PM PDT 24 |
May 26 03:54:47 PM PDT 24 |
3981548888 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2906061282 |
|
|
May 26 03:49:50 PM PDT 24 |
May 26 03:52:59 PM PDT 24 |
2663491336 ps |
| T942 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2945867094 |
|
|
May 26 03:47:28 PM PDT 24 |
May 26 03:59:29 PM PDT 24 |
4975500688 ps |
| T943 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.4121565748 |
|
|
May 26 04:00:28 PM PDT 24 |
May 26 04:19:32 PM PDT 24 |
6522477768 ps |
| T287 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2093740438 |
|
|
May 26 04:19:54 PM PDT 24 |
May 26 04:32:16 PM PDT 24 |
5547633316 ps |
| T152 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2383411021 |
|
|
May 26 03:54:50 PM PDT 24 |
May 26 03:59:21 PM PDT 24 |
2583521656 ps |
| T406 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.745514637 |
|
|
May 26 04:28:04 PM PDT 24 |
May 26 04:39:35 PM PDT 24 |
5320851968 ps |
| T407 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3877839049 |
|
|
May 26 04:07:23 PM PDT 24 |
May 26 04:19:21 PM PDT 24 |
9313655258 ps |
| T408 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3378711410 |
|
|
May 26 04:25:12 PM PDT 24 |
May 26 04:38:15 PM PDT 24 |
5115213672 ps |
| T409 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.138979481 |
|
|
May 26 04:17:49 PM PDT 24 |
May 26 05:37:25 PM PDT 24 |
22703398836 ps |
| T410 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.318009389 |
|
|
May 26 04:06:09 PM PDT 24 |
May 26 04:14:13 PM PDT 24 |
4787359152 ps |
| T153 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1928998583 |
|
|
May 26 04:02:21 PM PDT 24 |
May 26 04:08:28 PM PDT 24 |
3230657901 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3651225416 |
|
|
May 26 03:56:11 PM PDT 24 |
May 26 04:06:31 PM PDT 24 |
5681918672 ps |
| T411 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672919651 |
|
|
May 26 04:23:59 PM PDT 24 |
May 26 04:30:58 PM PDT 24 |
3573962422 ps |
| T45 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1409623394 |
|
|
May 26 03:50:12 PM PDT 24 |
May 26 04:14:53 PM PDT 24 |
11683756948 ps |
| T944 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3395693113 |
|
|
May 26 04:00:29 PM PDT 24 |
May 26 05:08:09 PM PDT 24 |
14485550080 ps |
| T945 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3990680118 |
|
|
May 26 03:58:27 PM PDT 24 |
May 26 04:58:09 PM PDT 24 |
14623467816 ps |
| T8 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2153661394 |
|
|
May 26 04:10:54 PM PDT 24 |
May 26 04:17:29 PM PDT 24 |
5298403736 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3749250484 |
|
|
May 26 03:58:52 PM PDT 24 |
May 26 04:24:55 PM PDT 24 |
10066528321 ps |
| T454 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2598269693 |
|
|
May 26 04:15:11 PM PDT 24 |
May 26 04:25:22 PM PDT 24 |
5030671600 ps |
| T455 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3510239261 |
|
|
May 26 04:12:54 PM PDT 24 |
May 26 04:17:00 PM PDT 24 |
2434652634 ps |
| T79 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.4187477143 |
|
|
May 26 03:49:07 PM PDT 24 |
May 26 04:18:28 PM PDT 24 |
21564803548 ps |
| T456 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.125469492 |
|
|
May 26 04:23:45 PM PDT 24 |
May 26 04:33:27 PM PDT 24 |
4920653208 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.2861150376 |
|
|
May 26 03:47:27 PM PDT 24 |
May 26 05:31:34 PM PDT 24 |
31545942072 ps |
| T457 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2845084836 |
|
|
May 26 03:56:33 PM PDT 24 |
May 26 04:01:28 PM PDT 24 |
2933087272 ps |
| T458 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1351734067 |
|
|
May 26 03:50:40 PM PDT 24 |
May 26 03:54:52 PM PDT 24 |
2844765512 ps |
| T459 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2246314365 |
|
|
May 26 03:57:44 PM PDT 24 |
May 26 04:07:23 PM PDT 24 |
4696475304 ps |
| T172 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3967546527 |
|
|
May 26 04:13:22 PM PDT 24 |
May 26 04:25:16 PM PDT 24 |
5102615464 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2060681264 |
|
|
May 26 03:48:09 PM PDT 24 |
May 26 04:35:02 PM PDT 24 |
25268898441 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2980956018 |
|
|
May 26 03:46:26 PM PDT 24 |
May 26 03:50:44 PM PDT 24 |
2349966664 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2595485484 |
|
|
May 26 04:13:02 PM PDT 24 |
May 26 04:21:41 PM PDT 24 |
3409630840 ps |
| T93 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2105749479 |
|
|
May 26 04:07:00 PM PDT 24 |
May 26 04:15:32 PM PDT 24 |
4817717074 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3578157483 |
|
|
May 26 03:52:31 PM PDT 24 |
May 26 04:02:49 PM PDT 24 |
4305569480 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4288358963 |
|
|
May 26 03:51:03 PM PDT 24 |
May 26 03:55:42 PM PDT 24 |
2602475324 ps |
| T255 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1394937546 |
|
|
May 26 03:53:24 PM PDT 24 |
May 26 04:07:59 PM PDT 24 |
4190289966 ps |
| T139 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2229664605 |
|
|
May 26 04:03:04 PM PDT 24 |
May 26 04:12:11 PM PDT 24 |
3922482230 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3280109483 |
|
|
May 26 03:57:06 PM PDT 24 |
May 26 04:02:23 PM PDT 24 |
2964738132 ps |
| T776 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3847674261 |
|
|
May 26 04:23:07 PM PDT 24 |
May 26 04:31:28 PM PDT 24 |
5134735030 ps |
| T67 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3744490981 |
|
|
May 26 04:00:09 PM PDT 24 |
May 26 04:10:34 PM PDT 24 |
7760167786 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1945310883 |
|
|
May 26 04:00:02 PM PDT 24 |
May 26 04:50:07 PM PDT 24 |
14222631208 ps |
| T3 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4166043260 |
|
|
May 26 03:54:21 PM PDT 24 |
May 26 04:13:58 PM PDT 24 |
19136692774 ps |
| T437 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.121213764 |
|
|
May 26 04:02:51 PM PDT 24 |
May 26 04:05:49 PM PDT 24 |
2363262968 ps |
| T438 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3004076589 |
|
|
May 26 04:18:59 PM PDT 24 |
May 26 04:30:53 PM PDT 24 |
4977654030 ps |
| T439 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4199767753 |
|
|
May 26 03:55:14 PM PDT 24 |
May 26 04:19:17 PM PDT 24 |
7724478940 ps |
| T440 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.910675595 |
|
|
May 26 03:47:58 PM PDT 24 |
May 26 04:05:34 PM PDT 24 |
5313098587 ps |
| T441 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.4261757785 |
|
|
May 26 04:18:23 PM PDT 24 |
May 26 04:26:31 PM PDT 24 |
3892154208 ps |
| T442 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1582939979 |
|
|
May 26 04:13:48 PM PDT 24 |
May 26 04:23:31 PM PDT 24 |
4303803576 ps |
| T443 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.25708159 |
|
|
May 26 03:54:39 PM PDT 24 |
May 26 04:14:28 PM PDT 24 |
7654344160 ps |
| T444 |
/workspace/coverage/default/0.chip_sw_example_flash.4219383841 |
|
|
May 26 03:49:58 PM PDT 24 |
May 26 03:54:06 PM PDT 24 |
3366970956 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.212810747 |
|
|
May 26 04:11:25 PM PDT 24 |
May 26 04:21:42 PM PDT 24 |
5224700312 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2043145737 |
|
|
May 26 03:54:25 PM PDT 24 |
May 26 03:58:35 PM PDT 24 |
3355024920 ps |
| T196 |
/workspace/coverage/default/3.chip_tap_straps_prod.3916975786 |
|
|
May 26 04:14:14 PM PDT 24 |
May 26 04:27:25 PM PDT 24 |
7065214713 ps |
| T303 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.583470050 |
|
|
May 26 04:07:28 PM PDT 24 |
May 26 04:32:06 PM PDT 24 |
10757797179 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3366523698 |
|
|
May 26 04:09:13 PM PDT 24 |
May 26 04:12:57 PM PDT 24 |
2482257984 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.734762242 |
|
|
May 26 03:46:38 PM PDT 24 |
May 26 03:55:08 PM PDT 24 |
3791968320 ps |
| T223 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3041607195 |
|
|
May 26 03:59:49 PM PDT 24 |
May 26 04:16:53 PM PDT 24 |
7084288192 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2550393858 |
|
|
May 26 03:58:51 PM PDT 24 |
May 26 04:25:01 PM PDT 24 |
17985795613 ps |
| T954 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3478101165 |
|
|
May 26 04:14:38 PM PDT 24 |
May 26 04:27:24 PM PDT 24 |
3764788720 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1262917802 |
|
|
May 26 04:05:17 PM PDT 24 |
May 26 04:16:35 PM PDT 24 |
3968753032 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2382696465 |
|
|
May 26 04:06:21 PM PDT 24 |
May 26 04:18:52 PM PDT 24 |
4665091720 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.2529129934 |
|
|
May 26 04:12:24 PM PDT 24 |
May 26 04:15:27 PM PDT 24 |
3318149022 ps |
| T958 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2834317955 |
|
|
May 26 04:09:14 PM PDT 24 |
May 26 04:20:04 PM PDT 24 |
4408750416 ps |
| T959 |
/workspace/coverage/default/1.chip_sw_aes_idle.1321561490 |
|
|
May 26 03:57:32 PM PDT 24 |
May 26 04:00:49 PM PDT 24 |
2941656234 ps |
| T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3764565395 |
|
|
May 26 03:49:37 PM PDT 24 |
May 26 03:56:12 PM PDT 24 |
4218730190 ps |
| T760 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3445947804 |
|
|
May 26 04:16:36 PM PDT 24 |
May 26 04:26:17 PM PDT 24 |
4956700700 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2789147229 |
|
|
May 26 04:08:21 PM PDT 24 |
May 26 04:20:53 PM PDT 24 |
4794606864 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2926455433 |
|
|
May 26 04:12:42 PM PDT 24 |
May 26 04:43:36 PM PDT 24 |
24781332094 ps |
| T961 |
/workspace/coverage/default/0.chip_sival_flash_info_access.4089915069 |
|
|
May 26 03:46:30 PM PDT 24 |
May 26 03:51:52 PM PDT 24 |
3748873992 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2128844084 |
|
|
May 26 04:06:11 PM PDT 24 |
May 26 04:17:53 PM PDT 24 |
6722073100 ps |
| T816 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3202436044 |
|
|
May 26 04:23:07 PM PDT 24 |
May 26 04:33:08 PM PDT 24 |
5449782670 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.21193872 |
|
|
May 26 04:07:06 PM PDT 24 |
May 26 04:17:18 PM PDT 24 |
4976331752 ps |
| T390 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3778107144 |
|
|
May 26 03:47:32 PM PDT 24 |
May 26 03:56:52 PM PDT 24 |
4786131702 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1857966798 |
|
|
May 26 04:05:46 PM PDT 24 |
May 26 04:26:28 PM PDT 24 |
7654463650 ps |
| T29 |
/workspace/coverage/default/2.chip_jtag_mem_access.616126812 |
|
|
May 26 04:02:53 PM PDT 24 |
May 26 04:26:20 PM PDT 24 |
13693470255 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.637821757 |
|
|
May 26 03:56:23 PM PDT 24 |
May 26 04:58:54 PM PDT 24 |
17145015280 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2703632527 |
|
|
May 26 03:58:46 PM PDT 24 |
May 26 04:03:14 PM PDT 24 |
2819587200 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1010467882 |
|
|
May 26 03:53:17 PM PDT 24 |
May 26 03:58:56 PM PDT 24 |
3742204792 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1678095089 |
|
|
May 26 04:12:36 PM PDT 24 |
May 26 04:18:29 PM PDT 24 |
3410896563 ps |
| T697 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3714510317 |
|
|
May 26 04:14:28 PM PDT 24 |
May 26 04:24:07 PM PDT 24 |
3952671728 ps |
| T30 |
/workspace/coverage/default/1.chip_jtag_mem_access.240595802 |
|
|
May 26 03:54:01 PM PDT 24 |
May 26 04:21:51 PM PDT 24 |
13309332074 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.972192522 |
|
|
May 26 03:59:01 PM PDT 24 |
May 26 04:13:18 PM PDT 24 |
8292231378 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2527437207 |
|
|
May 26 03:49:34 PM PDT 24 |
May 26 03:56:43 PM PDT 24 |
3223232492 ps |
| T747 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2305368127 |
|
|
May 26 04:16:36 PM PDT 24 |
May 26 04:25:51 PM PDT 24 |
4776440280 ps |
| T80 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1325119888 |
|
|
May 26 03:47:37 PM PDT 24 |
May 26 03:57:45 PM PDT 24 |
3760804566 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3667840295 |
|
|
May 26 04:03:50 PM PDT 24 |
May 26 04:33:06 PM PDT 24 |
10154963820 ps |
| T392 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2279873444 |
|
|
May 26 03:56:52 PM PDT 24 |
May 26 05:25:00 PM PDT 24 |
23140173788 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.618080613 |
|
|
May 26 03:51:27 PM PDT 24 |
May 26 04:08:45 PM PDT 24 |
5498575748 ps |
| T9 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.358429858 |
|
|
May 26 04:01:43 PM PDT 24 |
May 26 04:08:55 PM PDT 24 |
4284139000 ps |
| T722 |
/workspace/coverage/default/4.chip_tap_straps_prod.3596075200 |
|
|
May 26 04:14:41 PM PDT 24 |
May 26 04:17:49 PM PDT 24 |
2978651102 ps |
| T316 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2105082437 |
|
|
May 26 04:20:34 PM PDT 24 |
May 26 04:27:45 PM PDT 24 |
3257992096 ps |
| T723 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2458479842 |
|
|
May 26 04:21:24 PM PDT 24 |
May 26 04:30:59 PM PDT 24 |
4299300058 ps |
| T312 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.4255388823 |
|
|
May 26 04:25:15 PM PDT 24 |
May 26 04:39:20 PM PDT 24 |
5129134720 ps |
| T49 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1325394887 |
|
|
May 26 04:20:56 PM PDT 24 |
May 26 04:26:12 PM PDT 24 |
3416994192 ps |
| T724 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3390805455 |
|
|
May 26 04:20:39 PM PDT 24 |
May 26 04:27:26 PM PDT 24 |
3931276140 ps |
| T725 |
/workspace/coverage/default/1.chip_tap_straps_prod.1430678484 |
|
|
May 26 04:00:22 PM PDT 24 |
May 26 04:14:44 PM PDT 24 |
7451893193 ps |
| T291 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2463909591 |
|
|
May 26 03:52:30 PM PDT 24 |
May 26 03:56:43 PM PDT 24 |
3048951140 ps |
| T209 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1274484743 |
|
|
May 26 03:53:57 PM PDT 24 |
May 26 04:15:13 PM PDT 24 |
12029586630 ps |
| T807 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813873906 |
|
|
May 26 03:52:08 PM PDT 24 |
May 26 03:59:05 PM PDT 24 |
3486685300 ps |
| T415 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1631931879 |
|
|
May 26 04:09:33 PM PDT 24 |
May 26 04:19:27 PM PDT 24 |
8248046992 ps |
| T763 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2349758354 |
|
|
May 26 04:20:34 PM PDT 24 |
May 26 04:27:01 PM PDT 24 |
3058371496 ps |
| T777 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3625961334 |
|
|
May 26 04:23:28 PM PDT 24 |
May 26 04:33:32 PM PDT 24 |
5156208200 ps |
| T292 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1528687751 |
|
|
May 26 04:02:03 PM PDT 24 |
May 26 04:13:07 PM PDT 24 |
4876157945 ps |
| T804 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4103892120 |
|
|
May 26 04:17:17 PM PDT 24 |
May 26 04:25:54 PM PDT 24 |
3362965124 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.4034225874 |
|
|
May 26 03:49:37 PM PDT 24 |
May 26 03:53:44 PM PDT 24 |
2673459750 ps |
| T46 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2850389143 |
|
|
May 26 03:49:10 PM PDT 24 |
May 26 03:53:37 PM PDT 24 |
3749974112 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3068524427 |
|
|
May 26 03:56:50 PM PDT 24 |
May 26 04:00:21 PM PDT 24 |
3367979966 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.214344125 |
|
|
May 26 03:51:02 PM PDT 24 |
May 26 03:59:46 PM PDT 24 |
5406975810 ps |
| T974 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.262423139 |
|
|
May 26 03:50:35 PM PDT 24 |
May 26 04:03:37 PM PDT 24 |
5489289002 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_aes_enc.102318449 |
|
|
May 26 03:57:28 PM PDT 24 |
May 26 04:04:29 PM PDT 24 |
3731588790 ps |
| T821 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845790061 |
|
|
May 26 04:21:27 PM PDT 24 |
May 26 04:30:16 PM PDT 24 |
3962985760 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.751505898 |
|
|
May 26 04:08:47 PM PDT 24 |
May 26 04:20:01 PM PDT 24 |
7723317400 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1069514979 |
|
|
May 26 04:11:17 PM PDT 24 |
May 26 04:24:09 PM PDT 24 |
3913790070 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.221964604 |
|
|
May 26 04:03:31 PM PDT 24 |
May 26 04:08:03 PM PDT 24 |
2324392400 ps |
| T748 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3578654823 |
|
|
May 26 04:17:13 PM PDT 24 |
May 26 04:28:04 PM PDT 24 |
4578044060 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.4176941972 |
|
|
May 26 04:10:45 PM PDT 24 |
May 26 04:41:40 PM PDT 24 |
10710170928 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2410577488 |
|
|
May 26 04:05:02 PM PDT 24 |
May 26 07:10:22 PM PDT 24 |
63364679396 ps |
| T979 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1193192856 |
|
|
May 26 04:00:40 PM PDT 24 |
May 26 05:13:46 PM PDT 24 |
14272812364 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1308762353 |
|
|
May 26 03:52:52 PM PDT 24 |
May 26 04:03:51 PM PDT 24 |
4235419400 ps |
| T751 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4167531735 |
|
|
May 26 04:22:12 PM PDT 24 |
May 26 04:28:59 PM PDT 24 |
3477243694 ps |
| T548 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.937319887 |
|
|
May 26 04:08:55 PM PDT 24 |
May 26 04:20:12 PM PDT 24 |
4637081316 ps |
| T113 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3306563095 |
|
|
May 26 04:21:46 PM PDT 24 |
May 26 04:31:37 PM PDT 24 |
5301652924 ps |
| T468 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.608380489 |
|
|
May 26 04:18:19 PM PDT 24 |
May 26 06:01:58 PM PDT 24 |
25776803644 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4124188306 |
|
|
May 26 04:07:56 PM PDT 24 |
May 26 04:11:43 PM PDT 24 |
2366363074 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1617097524 |
|
|
May 26 04:04:22 PM PDT 24 |
May 26 04:17:43 PM PDT 24 |
4268881598 ps |
| T983 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.866013588 |
|
|
May 26 04:14:05 PM PDT 24 |
May 26 05:29:49 PM PDT 24 |
20942947134 ps |
| T764 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.552210182 |
|
|
May 26 04:21:23 PM PDT 24 |
May 26 04:27:47 PM PDT 24 |
3284242994 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1598897588 |
|
|
May 26 03:51:38 PM PDT 24 |
May 26 03:57:58 PM PDT 24 |
7032284550 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2199046935 |
|
|
May 26 04:04:15 PM PDT 24 |
May 26 04:16:03 PM PDT 24 |
3774790429 ps |
| T788 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.904949211 |
|
|
May 26 04:22:05 PM PDT 24 |
May 26 04:26:41 PM PDT 24 |
3502082712 ps |
| T793 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017484796 |
|
|
May 26 04:16:23 PM PDT 24 |
May 26 04:22:41 PM PDT 24 |
3181117800 ps |
| T984 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2829765224 |
|
|
May 26 04:15:48 PM PDT 24 |
May 26 04:34:23 PM PDT 24 |
7870928552 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1352689524 |
|
|
May 26 03:53:40 PM PDT 24 |
May 26 04:00:43 PM PDT 24 |
3175412496 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2338327386 |
|
|
May 26 04:07:10 PM PDT 24 |
May 26 04:21:27 PM PDT 24 |
5035640722 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2526528650 |
|
|
May 26 03:52:15 PM PDT 24 |
May 26 06:55:01 PM PDT 24 |
64843458194 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.373552848 |
|
|
May 26 04:10:42 PM PDT 24 |
May 26 04:22:11 PM PDT 24 |
4440064812 ps |
| T103 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2869997174 |
|
|
May 26 03:51:44 PM PDT 24 |
May 26 03:55:01 PM PDT 24 |
2813361663 ps |
| T988 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2406415042 |
|
|
May 26 04:16:26 PM PDT 24 |
May 26 05:30:32 PM PDT 24 |
17548322960 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.726174064 |
|
|
May 26 04:09:07 PM PDT 24 |
May 26 04:13:07 PM PDT 24 |
2434793534 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.157639803 |
|
|
May 26 03:56:09 PM PDT 24 |
May 26 04:05:02 PM PDT 24 |
6704065688 ps |
| T469 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3583330910 |
|
|
May 26 04:16:18 PM PDT 24 |
May 26 06:30:26 PM PDT 24 |
34322290680 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.68126314 |
|
|
May 26 04:10:34 PM PDT 24 |
May 26 04:24:09 PM PDT 24 |
8018877000 ps |
| T758 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4101834543 |
|
|
May 26 04:23:28 PM PDT 24 |
May 26 04:28:22 PM PDT 24 |
3273403240 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2487456716 |
|
|
May 26 03:55:37 PM PDT 24 |
May 26 04:06:55 PM PDT 24 |
4209204010 ps |
| T820 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3931730535 |
|
|
May 26 04:15:22 PM PDT 24 |
May 26 04:21:58 PM PDT 24 |
3257126596 ps |
| T779 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3869552812 |
|
|
May 26 04:16:05 PM PDT 24 |
May 26 04:25:47 PM PDT 24 |
5259314252 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1296793125 |
|
|
May 26 04:02:12 PM PDT 24 |
May 26 04:05:16 PM PDT 24 |
2831599212 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1621956112 |
|
|
May 26 03:59:17 PM PDT 24 |
May 26 04:19:21 PM PDT 24 |
6316639820 ps |
| T994 |
/workspace/coverage/default/2.rom_keymgr_functest.1122145962 |
|
|
May 26 04:13:33 PM PDT 24 |
May 26 04:23:18 PM PDT 24 |
4290182642 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2089795690 |
|
|
May 26 03:49:26 PM PDT 24 |
May 26 04:26:32 PM PDT 24 |
8506579968 ps |
| T775 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2678029335 |
|
|
May 26 04:18:08 PM PDT 24 |
May 26 04:23:38 PM PDT 24 |
3601542536 ps |
| T54 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1161958718 |
|
|
May 26 04:24:59 PM PDT 24 |
May 26 04:34:04 PM PDT 24 |
6406702840 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4097630319 |
|
|
May 26 04:00:55 PM PDT 24 |
May 26 04:07:29 PM PDT 24 |
2764672990 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_alert_test.2295999449 |
|
|
May 26 04:09:01 PM PDT 24 |
May 26 04:13:21 PM PDT 24 |
2909568970 ps |
| T997 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2949692449 |
|
|
May 26 04:17:22 PM PDT 24 |
May 26 04:31:01 PM PDT 24 |
5992172620 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3882250823 |
|
|
May 26 03:55:54 PM PDT 24 |
May 26 04:20:14 PM PDT 24 |
12750406403 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3862715491 |
|
|
May 26 04:09:12 PM PDT 24 |
May 26 04:15:47 PM PDT 24 |
5202984130 ps |
| T1000 |
/workspace/coverage/default/2.chip_tap_straps_prod.1157461212 |
|
|
May 26 04:09:31 PM PDT 24 |
May 26 04:12:02 PM PDT 24 |
3108974658 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4153550954 |
|
|
May 26 03:57:27 PM PDT 24 |
May 26 05:05:35 PM PDT 24 |
28362841000 ps |
| T1002 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3082249164 |
|
|
May 26 03:56:48 PM PDT 24 |
May 26 04:50:36 PM PDT 24 |
21630198973 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3493703458 |
|
|
May 26 03:47:04 PM PDT 24 |
May 26 03:52:57 PM PDT 24 |
3368108200 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1994374638 |
|
|
May 26 04:07:24 PM PDT 24 |
May 26 04:36:33 PM PDT 24 |
6703248836 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.515571198 |
|
|
May 26 04:08:53 PM PDT 24 |
May 26 04:17:11 PM PDT 24 |
6500054792 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.266666757 |
|
|
May 26 03:52:07 PM PDT 24 |
May 26 03:55:30 PM PDT 24 |
2936111848 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.756309374 |
|
|
May 26 03:49:18 PM PDT 24 |
May 26 03:53:58 PM PDT 24 |
3208937982 ps |
| T140 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1426372040 |
|
|
May 26 03:52:17 PM PDT 24 |
May 26 04:02:17 PM PDT 24 |
4128300916 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3387296109 |
|
|
May 26 03:51:40 PM PDT 24 |
May 26 04:08:12 PM PDT 24 |
12333674878 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.425055329 |
|
|
May 26 04:01:57 PM PDT 24 |
May 26 04:12:32 PM PDT 24 |
7849306124 ps |
| T781 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.4040916230 |
|
|
May 26 04:18:39 PM PDT 24 |
May 26 04:26:49 PM PDT 24 |
4366024390 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.332024773 |
|
|
May 26 04:10:52 PM PDT 24 |
May 26 07:33:35 PM PDT 24 |
255410370302 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1198901805 |
|
|
May 26 03:59:06 PM PDT 24 |
May 26 04:15:13 PM PDT 24 |
5744692808 ps |
| T274 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2026342008 |
|
|
May 26 04:02:32 PM PDT 24 |
May 26 04:14:38 PM PDT 24 |
4771774132 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.81178316 |
|
|
May 26 04:09:55 PM PDT 24 |
May 26 04:14:22 PM PDT 24 |
2654016334 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1027752123 |
|
|
May 26 04:05:48 PM PDT 24 |
May 26 04:38:57 PM PDT 24 |
8286749406 ps |
| T1011 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3753173719 |
|
|
May 26 03:59:28 PM PDT 24 |
May 26 04:45:55 PM PDT 24 |
11212657303 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4119868080 |
|
|
May 26 04:07:04 PM PDT 24 |
May 26 04:29:49 PM PDT 24 |
8488145516 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.391381849 |
|
|
May 26 04:02:44 PM PDT 24 |
May 26 04:16:49 PM PDT 24 |
4856973114 ps |
| T1014 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1981211725 |
|
|
May 26 03:56:06 PM PDT 24 |
May 26 04:52:06 PM PDT 24 |
14601894116 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1247140008 |
|
|
May 26 04:07:31 PM PDT 24 |
May 26 04:15:41 PM PDT 24 |
4155819248 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3619954284 |
|
|
May 26 03:54:08 PM PDT 24 |
May 26 04:27:38 PM PDT 24 |
8876969963 ps |
| T1017 |
/workspace/coverage/default/2.chip_sival_flash_info_access.617318223 |
|
|
May 26 04:04:43 PM PDT 24 |
May 26 04:10:03 PM PDT 24 |
2561131202 ps |
| T1018 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2681271090 |
|
|
May 26 03:54:08 PM PDT 24 |
May 26 04:14:12 PM PDT 24 |
8117216472 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1588882662 |
|
|
May 26 04:05:56 PM PDT 24 |
May 26 04:20:01 PM PDT 24 |
7684253601 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2967057137 |
|
|
May 26 03:58:23 PM PDT 24 |
May 26 04:24:30 PM PDT 24 |
6816237860 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2596105067 |
|
|
May 26 03:54:42 PM PDT 24 |
May 26 04:31:59 PM PDT 24 |
10321865976 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_example_rom.4279082434 |
|
|
May 26 04:07:46 PM PDT 24 |
May 26 04:10:02 PM PDT 24 |
2119902632 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1144918709 |
|
|
May 26 04:08:16 PM PDT 24 |
May 26 04:13:28 PM PDT 24 |
3387495096 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2927186112 |
|
|
May 26 03:48:45 PM PDT 24 |
May 26 04:55:04 PM PDT 24 |
34409139110 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.399828503 |
|
|
May 26 03:49:17 PM PDT 24 |
May 26 04:58:59 PM PDT 24 |
24889623019 ps |
| T114 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.360506965 |
|
|
May 26 04:18:48 PM PDT 24 |
May 26 04:27:11 PM PDT 24 |
4834107564 ps |
| T394 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3198765657 |
|
|
May 26 03:52:51 PM PDT 24 |
May 26 03:55:05 PM PDT 24 |
2346767490 ps |
| T366 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3806338651 |
|
|
May 26 04:08:29 PM PDT 24 |
May 26 04:19:44 PM PDT 24 |
6082158790 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3007060160 |
|
|
May 26 03:48:26 PM PDT 24 |
May 26 03:57:20 PM PDT 24 |
3550812128 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1621030138 |
|
|
May 26 04:03:16 PM PDT 24 |
May 26 04:06:26 PM PDT 24 |
2578716160 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4094800752 |
|
|
May 26 04:00:20 PM PDT 24 |
May 26 04:11:45 PM PDT 24 |
6541202886 ps |
| T1026 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2899238629 |
|
|
May 26 04:23:31 PM PDT 24 |
May 26 04:47:11 PM PDT 24 |
8182514456 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3699824108 |
|
|
May 26 03:50:19 PM PDT 24 |
May 26 05:20:24 PM PDT 24 |
23611733592 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3260637209 |
|
|
May 26 03:53:46 PM PDT 24 |
May 26 04:06:07 PM PDT 24 |
4369252594 ps |
| T267 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.655940428 |
|
|
May 26 04:11:35 PM PDT 24 |
May 26 04:25:50 PM PDT 24 |
6115726932 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1832428088 |
|
|
May 26 03:55:44 PM PDT 24 |
May 26 04:15:12 PM PDT 24 |
6230049741 ps |
| T1030 |
/workspace/coverage/default/1.rom_e2e_smoke.2257929063 |
|
|
May 26 04:09:14 PM PDT 24 |
May 26 05:06:11 PM PDT 24 |
13605103826 ps |
| T180 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.866349621 |
|
|
May 26 04:01:41 PM PDT 24 |
May 26 04:07:42 PM PDT 24 |
3435245220 ps |
| T778 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3258383326 |
|
|
May 26 03:59:26 PM PDT 24 |
May 26 04:08:02 PM PDT 24 |
3407330248 ps |
| T761 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.891659371 |
|
|
May 26 04:18:08 PM PDT 24 |
May 26 04:25:01 PM PDT 24 |
3358031486 ps |
| T81 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3815215493 |
|
|
May 26 03:47:04 PM PDT 24 |
May 26 04:16:29 PM PDT 24 |
8176922900 ps |
| T745 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3459195982 |
|
|
May 26 04:22:46 PM PDT 24 |
May 26 04:33:04 PM PDT 24 |
6017849344 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3539094776 |
|
|
May 26 04:00:04 PM PDT 24 |
May 26 04:07:09 PM PDT 24 |
3918057300 ps |
| T1032 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1485997075 |
|
|
May 26 04:23:41 PM PDT 24 |
May 26 04:32:25 PM PDT 24 |
4659853502 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3260094975 |
|
|
May 26 04:11:32 PM PDT 24 |
May 26 04:29:28 PM PDT 24 |
7175151676 ps |
| T317 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.560273246 |
|
|
May 26 04:18:53 PM PDT 24 |
May 26 04:29:42 PM PDT 24 |
4941975890 ps |
| T265 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2440871598 |
|
|
May 26 03:54:53 PM PDT 24 |
May 26 04:08:51 PM PDT 24 |
3992285226 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2144129691 |
|
|
May 26 03:48:40 PM PDT 24 |
May 26 03:52:47 PM PDT 24 |
2693558120 ps |
| T1035 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.24103133 |
|
|
May 26 03:51:56 PM PDT 24 |
May 26 03:56:00 PM PDT 24 |
2516531144 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3851282689 |
|
|
May 26 03:48:35 PM PDT 24 |
May 26 03:52:21 PM PDT 24 |
2702170107 ps |
| T10 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1373143628 |
|
|
May 26 03:49:20 PM PDT 24 |
May 26 03:55:59 PM PDT 24 |
4045604428 ps |