| T1176 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3131756241 |
|
|
May 26 04:11:09 PM PDT 24 |
May 26 04:22:29 PM PDT 24 |
4877900344 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3437293708 |
|
|
May 26 03:53:55 PM PDT 24 |
May 26 04:36:25 PM PDT 24 |
25291868267 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3432931189 |
|
|
May 26 04:04:38 PM PDT 24 |
May 26 04:08:47 PM PDT 24 |
3676356666 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_aes_enc.4161536860 |
|
|
May 26 04:07:55 PM PDT 24 |
May 26 04:11:53 PM PDT 24 |
2634085530 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.948022121 |
|
|
May 26 03:49:59 PM PDT 24 |
May 26 03:59:53 PM PDT 24 |
4804322864 ps |
| T270 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1048994938 |
|
|
May 26 03:50:04 PM PDT 24 |
May 26 04:02:38 PM PDT 24 |
4452534664 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.392258843 |
|
|
May 26 04:01:07 PM PDT 24 |
May 26 04:06:19 PM PDT 24 |
2442847472 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.762256122 |
|
|
May 26 03:54:45 PM PDT 24 |
May 26 04:22:10 PM PDT 24 |
8320011600 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2825564901 |
|
|
May 26 03:47:32 PM PDT 24 |
May 26 03:55:00 PM PDT 24 |
4107754047 ps |
| T1181 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3729562099 |
|
|
May 26 04:00:38 PM PDT 24 |
May 26 04:07:21 PM PDT 24 |
5085405752 ps |
| T749 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3973193499 |
|
|
May 26 03:47:55 PM PDT 24 |
May 26 04:00:05 PM PDT 24 |
5670962544 ps |
| T1182 |
/workspace/coverage/default/3.chip_tap_straps_rma.2469644091 |
|
|
May 26 04:13:22 PM PDT 24 |
May 26 04:19:51 PM PDT 24 |
5274176188 ps |
| T1183 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3006696037 |
|
|
May 26 03:53:12 PM PDT 24 |
May 26 03:56:43 PM PDT 24 |
3214528057 ps |
| T1184 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1029995730 |
|
|
May 26 04:08:34 PM PDT 24 |
May 26 05:01:13 PM PDT 24 |
14108096560 ps |
| T1185 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.461678664 |
|
|
May 26 04:18:17 PM PDT 24 |
May 26 04:22:51 PM PDT 24 |
2364851244 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.660196861 |
|
|
May 26 03:51:36 PM PDT 24 |
May 26 04:01:00 PM PDT 24 |
4811576220 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_aes_idle.4136722154 |
|
|
May 26 04:08:21 PM PDT 24 |
May 26 04:13:14 PM PDT 24 |
2907472536 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1601252340 |
|
|
May 26 04:08:38 PM PDT 24 |
May 26 04:20:29 PM PDT 24 |
5886152200 ps |
| T97 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1179970229 |
|
|
May 26 03:54:33 PM PDT 24 |
May 26 04:01:57 PM PDT 24 |
3362681716 ps |
| T435 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.401952104 |
|
|
May 26 04:11:08 PM PDT 24 |
May 26 04:42:49 PM PDT 24 |
22555611328 ps |
| T825 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883224177 |
|
|
May 26 04:22:02 PM PDT 24 |
May 26 04:28:42 PM PDT 24 |
4134260088 ps |
| T1189 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2816539221 |
|
|
May 26 04:21:19 PM PDT 24 |
May 26 04:47:48 PM PDT 24 |
8982982538 ps |
| T1190 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1868997427 |
|
|
May 26 04:17:35 PM PDT 24 |
May 26 04:45:15 PM PDT 24 |
8551989208 ps |
| T782 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.295450357 |
|
|
May 26 04:22:24 PM PDT 24 |
May 26 04:27:45 PM PDT 24 |
3056279200 ps |
| T806 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.702682576 |
|
|
May 26 04:17:19 PM PDT 24 |
May 26 04:28:13 PM PDT 24 |
5394323090 ps |
| T1191 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1827574959 |
|
|
May 26 04:02:22 PM PDT 24 |
May 26 05:08:27 PM PDT 24 |
14451001730 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1496176266 |
|
|
May 26 03:57:20 PM PDT 24 |
May 26 04:12:32 PM PDT 24 |
5023633364 ps |
| T1193 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2943362598 |
|
|
May 26 04:21:20 PM PDT 24 |
May 26 04:27:57 PM PDT 24 |
3763788188 ps |
| T1194 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1516885653 |
|
|
May 26 03:49:13 PM PDT 24 |
May 26 04:09:07 PM PDT 24 |
12339213240 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3220133298 |
|
|
May 26 03:50:27 PM PDT 24 |
May 26 03:55:05 PM PDT 24 |
2806661065 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3904010399 |
|
|
May 26 03:55:38 PM PDT 24 |
May 26 04:02:49 PM PDT 24 |
4952187632 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.362068680 |
|
|
May 26 04:07:42 PM PDT 24 |
May 26 04:20:02 PM PDT 24 |
4634813287 ps |
| T741 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3923753056 |
|
|
May 26 04:17:31 PM PDT 24 |
May 26 04:24:28 PM PDT 24 |
3804702952 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_edn_kat.3542048823 |
|
|
May 26 03:51:03 PM PDT 24 |
May 26 04:02:41 PM PDT 24 |
3095688490 ps |
| T830 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3045127151 |
|
|
May 26 04:23:25 PM PDT 24 |
May 26 04:34:28 PM PDT 24 |
5094780328 ps |
| T1198 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3117075068 |
|
|
May 26 04:17:03 PM PDT 24 |
May 26 05:29:02 PM PDT 24 |
14097043400 ps |
| T1199 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3864971735 |
|
|
May 26 03:53:36 PM PDT 24 |
May 26 04:14:42 PM PDT 24 |
8279427169 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4242729662 |
|
|
May 26 04:00:55 PM PDT 24 |
May 26 04:37:08 PM PDT 24 |
10951649972 ps |
| T306 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1095909135 |
|
|
May 26 03:52:09 PM PDT 24 |
May 26 03:57:33 PM PDT 24 |
3059557020 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4230620465 |
|
|
May 26 04:06:14 PM PDT 24 |
May 26 04:40:00 PM PDT 24 |
17662482011 ps |
| T1202 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1714462692 |
|
|
May 26 04:08:31 PM PDT 24 |
May 26 05:05:46 PM PDT 24 |
18320066345 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1363533485 |
|
|
May 26 04:07:44 PM PDT 24 |
May 26 04:14:51 PM PDT 24 |
2963234880 ps |
| T309 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2930648801 |
|
|
May 26 04:11:53 PM PDT 24 |
May 26 04:17:03 PM PDT 24 |
2603843804 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.3869134118 |
|
|
May 26 04:03:25 PM PDT 24 |
May 26 04:08:14 PM PDT 24 |
2916142344 ps |
| T1205 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2605857863 |
|
|
May 26 04:11:21 PM PDT 24 |
May 26 04:22:27 PM PDT 24 |
4941303376 ps |
| T1206 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1618894835 |
|
|
May 26 04:21:12 PM PDT 24 |
May 26 04:32:17 PM PDT 24 |
5337204780 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3852783330 |
|
|
May 26 04:01:41 PM PDT 24 |
May 26 04:09:49 PM PDT 24 |
5609112344 ps |
| T1208 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3774534951 |
|
|
May 26 04:16:20 PM PDT 24 |
May 26 04:25:26 PM PDT 24 |
3593600276 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_alert_test.570452306 |
|
|
May 26 03:58:27 PM PDT 24 |
May 26 04:02:31 PM PDT 24 |
2842775496 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3186462737 |
|
|
May 26 03:50:10 PM PDT 24 |
May 26 04:05:28 PM PDT 24 |
7379359904 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_flash_init.924530801 |
|
|
May 26 03:54:56 PM PDT 24 |
May 26 04:30:57 PM PDT 24 |
25486335068 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1698138867 |
|
|
May 26 03:50:08 PM PDT 24 |
May 26 04:08:28 PM PDT 24 |
6493790610 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1132197701 |
|
|
May 26 03:56:59 PM PDT 24 |
May 26 04:04:38 PM PDT 24 |
7299760700 ps |
| T1211 |
/workspace/coverage/default/2.chip_tap_straps_rma.2006492981 |
|
|
May 26 04:10:09 PM PDT 24 |
May 26 04:23:35 PM PDT 24 |
8210639063 ps |
| T1212 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3023782686 |
|
|
May 26 04:23:48 PM PDT 24 |
May 26 04:48:04 PM PDT 24 |
7450272120 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.305966682 |
|
|
May 26 04:08:41 PM PDT 24 |
May 26 04:39:21 PM PDT 24 |
8196210036 ps |
| T1214 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2713103386 |
|
|
May 26 04:01:13 PM PDT 24 |
May 26 04:15:01 PM PDT 24 |
5547690646 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_gpio.1920592031 |
|
|
May 26 04:05:30 PM PDT 24 |
May 26 04:14:46 PM PDT 24 |
4464823632 ps |
| T470 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.336824364 |
|
|
May 26 04:10:24 PM PDT 24 |
May 26 04:21:09 PM PDT 24 |
3379915422 ps |
| T104 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1474238704 |
|
|
May 26 04:13:38 PM PDT 24 |
May 26 04:16:12 PM PDT 24 |
2688093529 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1558969710 |
|
|
May 26 04:05:33 PM PDT 24 |
May 26 04:09:35 PM PDT 24 |
2277224997 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1559368366 |
|
|
May 26 04:06:15 PM PDT 24 |
May 26 04:10:43 PM PDT 24 |
2545270588 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2903685659 |
|
|
May 26 03:51:07 PM PDT 24 |
May 26 04:31:21 PM PDT 24 |
17625893864 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3014492202 |
|
|
May 26 04:12:53 PM PDT 24 |
May 26 04:18:28 PM PDT 24 |
5955283992 ps |
| T1218 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3572734092 |
|
|
May 26 04:14:41 PM PDT 24 |
May 26 04:24:04 PM PDT 24 |
7685256280 ps |
| T1219 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4033963586 |
|
|
May 26 04:17:34 PM PDT 24 |
May 26 05:16:51 PM PDT 24 |
14353502897 ps |
| T766 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.867714653 |
|
|
May 26 04:22:10 PM PDT 24 |
May 26 04:27:54 PM PDT 24 |
3622792896 ps |
| T1220 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.193166597 |
|
|
May 26 04:10:35 PM PDT 24 |
May 26 04:15:02 PM PDT 24 |
2595179340 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2066907578 |
|
|
May 26 04:09:10 PM PDT 24 |
May 26 04:26:00 PM PDT 24 |
12438154122 ps |
| T1222 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2695482046 |
|
|
May 26 04:16:21 PM PDT 24 |
May 26 04:28:51 PM PDT 24 |
4330891928 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3500479334 |
|
|
May 26 03:53:05 PM PDT 24 |
May 26 04:03:07 PM PDT 24 |
5327238390 ps |
| T811 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1766510469 |
|
|
May 26 04:19:37 PM PDT 24 |
May 26 04:30:58 PM PDT 24 |
4846524950 ps |
| T1224 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3398474099 |
|
|
May 26 04:13:36 PM PDT 24 |
May 26 04:24:26 PM PDT 24 |
5870642144 ps |
| T814 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.110911921 |
|
|
May 26 04:18:41 PM PDT 24 |
May 26 04:26:54 PM PDT 24 |
3472087100 ps |
| T271 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2146376752 |
|
|
May 26 04:05:44 PM PDT 24 |
May 26 04:18:35 PM PDT 24 |
4466204060 ps |
| T1225 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.130236035 |
|
|
May 26 04:07:30 PM PDT 24 |
May 26 04:17:13 PM PDT 24 |
5768792632 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.4072496292 |
|
|
May 26 04:15:42 PM PDT 24 |
May 26 04:18:34 PM PDT 24 |
2326284276 ps |
| T1227 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4097349801 |
|
|
May 26 04:18:01 PM PDT 24 |
May 26 04:27:00 PM PDT 24 |
4071943195 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.457522987 |
|
|
May 26 03:46:55 PM PDT 24 |
May 26 03:51:13 PM PDT 24 |
2352750220 ps |
| T1228 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3051160905 |
|
|
May 26 04:14:22 PM PDT 24 |
May 26 04:28:49 PM PDT 24 |
5366095000 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3794908960 |
|
|
May 26 03:52:56 PM PDT 24 |
May 26 03:56:34 PM PDT 24 |
2320824660 ps |
| T1230 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3204290240 |
|
|
May 26 04:00:42 PM PDT 24 |
May 26 05:25:35 PM PDT 24 |
17841540984 ps |
| T711 |
/workspace/coverage/default/0.chip_tap_straps_dev.2264645747 |
|
|
May 26 03:48:16 PM PDT 24 |
May 26 04:25:42 PM PDT 24 |
18570559098 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1170761272 |
|
|
May 26 04:08:48 PM PDT 24 |
May 26 04:21:06 PM PDT 24 |
5555169996 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2664909927 |
|
|
May 26 04:08:11 PM PDT 24 |
May 26 04:44:27 PM PDT 24 |
11613578372 ps |
| T1233 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.851651354 |
|
|
May 26 04:18:02 PM PDT 24 |
May 26 04:22:41 PM PDT 24 |
3527611476 ps |
| T774 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2818150933 |
|
|
May 26 04:19:10 PM PDT 24 |
May 26 04:29:39 PM PDT 24 |
4647306020 ps |
| T212 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3141989983 |
|
|
May 26 03:49:40 PM PDT 24 |
May 26 05:00:48 PM PDT 24 |
19333027530 ps |
| T802 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3575170720 |
|
|
May 26 04:22:51 PM PDT 24 |
May 26 04:33:19 PM PDT 24 |
4775833180 ps |
| T833 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950435971 |
|
|
May 26 04:18:39 PM PDT 24 |
May 26 04:24:48 PM PDT 24 |
3817853420 ps |
| T800 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.845320497 |
|
|
May 26 04:17:53 PM PDT 24 |
May 26 04:24:33 PM PDT 24 |
3803722020 ps |
| T1234 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.81558705 |
|
|
May 26 04:06:11 PM PDT 24 |
May 26 04:27:47 PM PDT 24 |
12547154506 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2930126603 |
|
|
May 26 03:50:36 PM PDT 24 |
May 26 03:54:10 PM PDT 24 |
3325221438 ps |
| T105 |
/workspace/coverage/default/0.chip_tap_straps_rma.3040477823 |
|
|
May 26 03:47:25 PM PDT 24 |
May 26 03:53:25 PM PDT 24 |
5373433179 ps |
| T1236 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3719016779 |
|
|
May 26 03:50:25 PM PDT 24 |
May 26 04:08:53 PM PDT 24 |
7517025144 ps |
| T14 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1225450602 |
|
|
May 26 03:46:37 PM PDT 24 |
May 26 03:50:57 PM PDT 24 |
3296630874 ps |
| T803 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860926167 |
|
|
May 26 04:19:19 PM PDT 24 |
May 26 04:26:13 PM PDT 24 |
3787459928 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2102104692 |
|
|
May 26 03:51:22 PM PDT 24 |
May 26 03:54:38 PM PDT 24 |
3136110375 ps |
| T783 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.16766708 |
|
|
May 26 04:20:49 PM PDT 24 |
May 26 04:26:27 PM PDT 24 |
3027841374 ps |
| T1238 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776556925 |
|
|
May 26 04:20:33 PM PDT 24 |
May 26 04:26:59 PM PDT 24 |
3553790672 ps |
| T780 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3112812211 |
|
|
May 26 04:18:34 PM PDT 24 |
May 26 04:25:30 PM PDT 24 |
3267037720 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1355827098 |
|
|
May 26 04:08:19 PM PDT 24 |
May 26 04:27:17 PM PDT 24 |
6217907874 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1162731446 |
|
|
May 26 04:05:19 PM PDT 24 |
May 26 04:16:57 PM PDT 24 |
4759067376 ps |
| T1240 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.434609296 |
|
|
May 26 04:02:22 PM PDT 24 |
May 26 05:17:27 PM PDT 24 |
13909759660 ps |
| T210 |
/workspace/coverage/default/0.chip_jtag_mem_access.142056955 |
|
|
May 26 03:41:42 PM PDT 24 |
May 26 04:04:35 PM PDT 24 |
13080583088 ps |
| T1241 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3816916239 |
|
|
May 26 04:14:55 PM PDT 24 |
May 26 04:25:30 PM PDT 24 |
3817434744 ps |
| T1242 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3530717296 |
|
|
May 26 04:16:47 PM PDT 24 |
May 26 04:26:36 PM PDT 24 |
5489964440 ps |
| T473 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2899474934 |
|
|
May 26 03:48:50 PM PDT 24 |
May 26 03:57:29 PM PDT 24 |
3423584570 ps |
| T1243 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4185474576 |
|
|
May 26 04:18:34 PM PDT 24 |
May 26 04:28:54 PM PDT 24 |
5133316296 ps |
| T1244 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1959066089 |
|
|
May 26 03:47:41 PM PDT 24 |
May 26 06:56:40 PM PDT 24 |
64196541265 ps |
| T1245 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.4025092844 |
|
|
May 26 03:47:20 PM PDT 24 |
May 26 03:56:56 PM PDT 24 |
4156990436 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1987413990 |
|
|
May 26 03:57:31 PM PDT 24 |
May 26 04:55:39 PM PDT 24 |
18635374045 ps |
| T1247 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2907891848 |
|
|
May 26 04:07:23 PM PDT 24 |
May 26 04:33:49 PM PDT 24 |
22698052852 ps |
| T742 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1156540669 |
|
|
May 26 04:22:10 PM PDT 24 |
May 26 04:27:10 PM PDT 24 |
3429393230 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2968156903 |
|
|
May 26 03:53:11 PM PDT 24 |
May 26 04:31:20 PM PDT 24 |
10608347728 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1402927266 |
|
|
May 26 04:13:05 PM PDT 24 |
May 26 04:42:24 PM PDT 24 |
23220054773 ps |
| T1248 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3110832900 |
|
|
May 26 04:21:49 PM PDT 24 |
May 26 04:29:33 PM PDT 24 |
4514106694 ps |
| T263 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3454561405 |
|
|
May 26 04:00:26 PM PDT 24 |
May 26 04:21:43 PM PDT 24 |
5795397700 ps |
| T175 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2820965569 |
|
|
May 26 04:10:18 PM PDT 24 |
May 26 04:20:48 PM PDT 24 |
4976035896 ps |
| T773 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.187405929 |
|
|
May 26 04:22:54 PM PDT 24 |
May 26 04:29:22 PM PDT 24 |
4422419098 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.384154753 |
|
|
May 26 04:04:26 PM PDT 24 |
May 26 04:11:48 PM PDT 24 |
4437000266 ps |
| T678 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.382404901 |
|
|
May 26 04:01:36 PM PDT 24 |
May 26 04:13:10 PM PDT 24 |
5656485346 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.994598267 |
|
|
May 26 03:53:44 PM PDT 24 |
May 26 03:58:45 PM PDT 24 |
3211625944 ps |
| T710 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2008744761 |
|
|
May 26 03:50:38 PM PDT 24 |
May 26 03:58:07 PM PDT 24 |
4387097100 ps |
| T768 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3138573815 |
|
|
May 26 04:21:21 PM PDT 24 |
May 26 04:31:23 PM PDT 24 |
6311416992 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2179212716 |
|
|
May 26 03:50:02 PM PDT 24 |
May 26 03:59:28 PM PDT 24 |
4797576120 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_example_rom.413677690 |
|
|
May 26 03:52:41 PM PDT 24 |
May 26 03:54:27 PM PDT 24 |
2708125592 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1258411395 |
|
|
May 26 04:00:42 PM PDT 24 |
May 26 04:34:36 PM PDT 24 |
19351592760 ps |
| T708 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.73817756 |
|
|
May 26 04:12:30 PM PDT 24 |
May 26 04:19:39 PM PDT 24 |
4209505568 ps |
| T200 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3988386835 |
|
|
May 26 04:05:30 PM PDT 24 |
May 26 04:16:19 PM PDT 24 |
4378735382 ps |
| T1254 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3836609600 |
|
|
May 26 04:14:52 PM PDT 24 |
May 26 04:41:36 PM PDT 24 |
8286254882 ps |
| T1255 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2095116294 |
|
|
May 26 03:51:37 PM PDT 24 |
May 26 03:54:58 PM PDT 24 |
2845141357 ps |
| T327 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1996838614 |
|
|
May 26 04:23:35 PM PDT 24 |
May 26 04:35:15 PM PDT 24 |
6167741544 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4079367806 |
|
|
May 26 04:04:43 PM PDT 24 |
May 26 04:10:11 PM PDT 24 |
4078092212 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2187691764 |
|
|
May 26 04:05:51 PM PDT 24 |
May 26 04:12:14 PM PDT 24 |
3053509638 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1186748442 |
|
|
May 26 04:01:02 PM PDT 24 |
May 26 04:12:13 PM PDT 24 |
3424631674 ps |
| T1259 |
/workspace/coverage/default/0.rom_e2e_smoke.3769105289 |
|
|
May 26 03:56:52 PM PDT 24 |
May 26 04:52:09 PM PDT 24 |
14441676690 ps |
| T70 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.268077977 |
|
|
May 26 04:05:18 PM PDT 24 |
May 26 04:09:57 PM PDT 24 |
3175418492 ps |
| T832 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.454137795 |
|
|
May 26 04:21:18 PM PDT 24 |
May 26 04:28:36 PM PDT 24 |
3901180308 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1133392960 |
|
|
May 26 03:50:07 PM PDT 24 |
May 26 03:59:33 PM PDT 24 |
5393289194 ps |
| T1261 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1751300541 |
|
|
May 26 04:01:07 PM PDT 24 |
May 26 04:07:02 PM PDT 24 |
3922444974 ps |
| T1262 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.795881268 |
|
|
May 26 04:12:43 PM PDT 24 |
May 26 04:25:09 PM PDT 24 |
8273220931 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2690623366 |
|
|
May 26 03:53:21 PM PDT 24 |
May 26 04:03:22 PM PDT 24 |
5386294318 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.723219797 |
|
|
May 26 03:52:10 PM PDT 24 |
May 26 03:57:55 PM PDT 24 |
2932550256 ps |
| T1265 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3278381970 |
|
|
May 26 03:57:14 PM PDT 24 |
May 26 04:56:49 PM PDT 24 |
13403654058 ps |
| T784 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214533234 |
|
|
May 26 04:17:07 PM PDT 24 |
May 26 04:23:08 PM PDT 24 |
3682889528 ps |
| T358 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1326878672 |
|
|
May 26 04:16:40 PM PDT 24 |
May 26 04:26:59 PM PDT 24 |
5852308780 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1453859682 |
|
|
May 26 03:51:56 PM PDT 24 |
May 26 04:08:13 PM PDT 24 |
7370911436 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_alert_test.2439364172 |
|
|
May 26 03:51:37 PM PDT 24 |
May 26 03:57:16 PM PDT 24 |
2895596092 ps |
| T1267 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.767201443 |
|
|
May 26 04:17:30 PM PDT 24 |
May 26 05:09:38 PM PDT 24 |
14001587251 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.843484981 |
|
|
May 26 04:09:26 PM PDT 24 |
May 26 04:18:51 PM PDT 24 |
5414152840 ps |
| T771 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3161163269 |
|
|
May 26 04:20:59 PM PDT 24 |
May 26 04:28:02 PM PDT 24 |
5333289036 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3701854175 |
|
|
May 26 03:51:42 PM PDT 24 |
May 26 03:58:24 PM PDT 24 |
3520247200 ps |
| T328 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2929398560 |
|
|
May 26 04:06:03 PM PDT 24 |
May 26 04:17:19 PM PDT 24 |
5042300440 ps |
| T819 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1405148915 |
|
|
May 26 04:18:55 PM PDT 24 |
May 26 04:24:21 PM PDT 24 |
4383652000 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1551013818 |
|
|
May 26 04:13:49 PM PDT 24 |
May 26 04:17:44 PM PDT 24 |
2869720611 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1107699318 |
|
|
May 26 04:00:56 PM PDT 24 |
May 26 04:11:25 PM PDT 24 |
4733321946 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.14114657 |
|
|
May 26 03:49:22 PM PDT 24 |
May 26 03:53:26 PM PDT 24 |
2196067594 ps |
| T796 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.406987498 |
|
|
May 26 04:17:28 PM PDT 24 |
May 26 04:26:08 PM PDT 24 |
5236100812 ps |
| T1273 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.932969922 |
|
|
May 26 04:18:06 PM PDT 24 |
May 26 04:24:47 PM PDT 24 |
3074426280 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4102905406 |
|
|
May 26 04:11:34 PM PDT 24 |
May 26 04:43:38 PM PDT 24 |
18102264320 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2166615875 |
|
|
May 26 03:46:35 PM PDT 24 |
May 26 03:49:06 PM PDT 24 |
2255319064 ps |
| T436 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1509188946 |
|
|
May 26 04:09:51 PM PDT 24 |
May 26 04:35:00 PM PDT 24 |
20797207240 ps |
| T1275 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1317784863 |
|
|
May 26 03:49:22 PM PDT 24 |
May 26 03:56:13 PM PDT 24 |
8988147123 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2381454969 |
|
|
May 26 03:48:54 PM PDT 24 |
May 26 04:42:09 PM PDT 24 |
11511772622 ps |
| T266 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.2333480735 |
|
|
May 26 03:50:24 PM PDT 24 |
May 26 04:10:49 PM PDT 24 |
6000490308 ps |
| T23 |
/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1903443326 |
|
|
May 26 03:18:50 PM PDT 24 |
May 26 03:22:57 PM PDT 24 |
450885848 ps |
| T24 |
/workspace/coverage/cover_reg_top/56.xbar_same_source.4090101210 |
|
|
May 26 03:31:59 PM PDT 24 |
May 26 03:32:40 PM PDT 24 |
521492720 ps |
| T25 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.823218527 |
|
|
May 26 03:33:58 PM PDT 24 |
May 26 03:35:07 PM PDT 24 |
343314973 ps |
| T137 |
/workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3428182968 |
|
|
May 26 03:30:34 PM PDT 24 |
May 26 03:43:28 PM PDT 24 |
77206272538 ps |
| T535 |
/workspace/coverage/cover_reg_top/88.xbar_same_source.1906468071 |
|
|
May 26 03:37:34 PM PDT 24 |
May 26 03:37:46 PM PDT 24 |
137515920 ps |
| T318 |
/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2793434262 |
|
|
May 26 03:33:44 PM PDT 24 |
May 26 04:13:16 PM PDT 24 |
130558639814 ps |
| T451 |
/workspace/coverage/cover_reg_top/20.xbar_random.4229069131 |
|
|
May 26 03:24:43 PM PDT 24 |
May 26 03:25:43 PM PDT 24 |
1748963208 ps |
| T319 |
/workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1796102099 |
|
|
May 26 03:34:44 PM PDT 24 |
May 26 03:35:07 PM PDT 24 |
229672061 ps |
| T550 |
/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3209371382 |
|
|
May 26 03:20:04 PM PDT 24 |
May 26 03:49:17 PM PDT 24 |
96847891157 ps |
| T561 |
/workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.4270553117 |
|
|
May 26 03:34:21 PM PDT 24 |
May 26 03:35:57 PM PDT 24 |
8956345599 ps |
| T320 |
/workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2096666428 |
|
|
May 26 03:20:15 PM PDT 24 |
May 26 03:21:38 PM PDT 24 |
4942862478 ps |
| T553 |
/workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1853534605 |
|
|
May 26 03:37:47 PM PDT 24 |
May 26 03:48:21 PM PDT 24 |
58496760477 ps |
| T474 |
/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.642982770 |
|
|
May 26 03:30:07 PM PDT 24 |
May 26 03:34:21 PM PDT 24 |
5194808859 ps |
| T425 |
/workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4251296424 |
|
|
May 26 03:33:26 PM PDT 24 |
May 26 03:34:16 PM PDT 24 |
648123110 ps |
| T507 |
/workspace/coverage/cover_reg_top/38.xbar_random.215971592 |
|
|
May 26 03:28:30 PM PDT 24 |
May 26 03:28:52 PM PDT 24 |
211278919 ps |
| T552 |
/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3714490085 |
|
|
May 26 03:31:28 PM PDT 24 |
May 26 03:37:05 PM PDT 24 |
34951167228 ps |
| T556 |
/workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.523086846 |
|
|
May 26 03:33:41 PM PDT 24 |
May 26 03:33:55 PM PDT 24 |
140438128 ps |
| T527 |
/workspace/coverage/cover_reg_top/46.xbar_same_source.1010806446 |
|
|
May 26 03:30:03 PM PDT 24 |
May 26 03:31:01 PM PDT 24 |
1865818156 ps |
| T475 |
/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1073833249 |
|
|
May 26 03:37:27 PM PDT 24 |
May 26 03:42:49 PM PDT 24 |
4919214237 ps |
| T635 |
/workspace/coverage/cover_reg_top/74.xbar_smoke.1340242382 |
|
|
May 26 03:35:01 PM PDT 24 |
May 26 03:35:08 PM PDT 24 |
36386056 ps |
| T560 |
/workspace/coverage/cover_reg_top/22.xbar_smoke.1887303448 |
|
|
May 26 03:25:08 PM PDT 24 |
May 26 03:25:16 PM PDT 24 |
158846764 ps |
| T854 |
/workspace/coverage/cover_reg_top/79.xbar_access_same_device.303219606 |
|
|
May 26 03:35:58 PM PDT 24 |
May 26 03:36:42 PM PDT 24 |
989343685 ps |
| T476 |
/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2603802009 |
|
|
May 26 03:31:31 PM PDT 24 |
May 26 03:33:32 PM PDT 24 |
1475543353 ps |
| T757 |
/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3776194895 |
|
|
May 26 03:30:45 PM PDT 24 |
May 26 03:31:44 PM PDT 24 |
219170208 ps |
| T559 |
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1667821646 |
|
|
May 26 03:22:41 PM PDT 24 |
May 26 03:38:38 PM PDT 24 |
93826337071 ps |
| T464 |
/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1878149466 |
|
|
May 26 03:35:07 PM PDT 24 |
May 26 04:08:25 PM PDT 24 |
104140985641 ps |
| T529 |
/workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2847861934 |
|
|
May 26 03:29:55 PM PDT 24 |
May 26 03:30:23 PM PDT 24 |
239226796 ps |
| T1276 |
/workspace/coverage/cover_reg_top/3.xbar_random.719243166 |
|
|
May 26 03:19:03 PM PDT 24 |
May 26 03:19:30 PM PDT 24 |
711575738 ps |
| T1277 |
/workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.522534644 |
|
|
May 26 03:27:11 PM PDT 24 |
May 26 03:27:19 PM PDT 24 |
48885800 ps |
| T450 |
/workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.754241012 |
|
|
May 26 03:28:45 PM PDT 24 |
May 26 03:40:53 PM PDT 24 |
43991361780 ps |
| T558 |
/workspace/coverage/cover_reg_top/8.xbar_access_same_device.2614083298 |
|
|
May 26 03:21:05 PM PDT 24 |
May 26 03:22:12 PM PDT 24 |
1392943619 ps |
| T446 |
/workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3764105374 |
|
|
May 26 03:19:08 PM PDT 24 |
May 26 03:33:21 PM PDT 24 |
79540271618 ps |
| T551 |
/workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1700181446 |
|
|
May 26 03:35:39 PM PDT 24 |
May 26 03:36:08 PM PDT 24 |
297739382 ps |
| T546 |
/workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3715577198 |
|
|
May 26 03:33:43 PM PDT 24 |
May 26 03:51:16 PM PDT 24 |
59492110342 ps |
| T462 |
/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2552519793 |
|
|
May 26 03:19:43 PM PDT 24 |
May 26 03:29:47 PM PDT 24 |
8170150135 ps |
| T557 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.409550241 |
|
|
May 26 03:32:14 PM PDT 24 |
May 26 03:34:43 PM PDT 24 |
434439029 ps |
| T1278 |
/workspace/coverage/cover_reg_top/65.xbar_error_random.3291155397 |
|
|
May 26 03:33:33 PM PDT 24 |
May 26 03:33:54 PM PDT 24 |
546038928 ps |
| T554 |
/workspace/coverage/cover_reg_top/44.xbar_access_same_device.288482229 |
|
|
May 26 03:29:44 PM PDT 24 |
May 26 03:31:13 PM PDT 24 |
2276791365 ps |
| T576 |
/workspace/coverage/cover_reg_top/10.xbar_same_source.334952510 |
|
|
May 26 03:21:45 PM PDT 24 |
May 26 03:22:22 PM PDT 24 |
472427682 ps |
| T840 |
/workspace/coverage/cover_reg_top/53.xbar_error_random.3423542699 |
|
|
May 26 03:31:24 PM PDT 24 |
May 26 03:32:09 PM PDT 24 |
1177089456 ps |
| T566 |
/workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2634955760 |
|
|
May 26 03:35:28 PM PDT 24 |
May 26 03:36:17 PM PDT 24 |
1176646210 ps |
| T385 |
/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1736645591 |
|
|
May 26 03:18:23 PM PDT 24 |
May 26 03:34:08 PM PDT 24 |
11119667322 ps |
| T642 |
/workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3423283616 |
|
|
May 26 03:28:38 PM PDT 24 |
May 26 03:28:52 PM PDT 24 |
98856034 ps |
| T555 |
/workspace/coverage/cover_reg_top/95.xbar_random.2924378208 |
|
|
May 26 03:38:49 PM PDT 24 |
May 26 03:39:24 PM PDT 24 |
442137739 ps |
| T562 |
/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1305508574 |
|
|
May 26 03:29:27 PM PDT 24 |
May 26 03:34:13 PM PDT 24 |
4072671420 ps |
| T696 |
/workspace/coverage/cover_reg_top/72.xbar_access_same_device.817852174 |
|
|
May 26 03:34:44 PM PDT 24 |
May 26 03:35:18 PM PDT 24 |
584255125 ps |
| T683 |
/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.3893847443 |
|
|
May 26 03:32:40 PM PDT 24 |
May 26 03:36:33 PM PDT 24 |
3327335057 ps |
| T625 |
/workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3126627531 |
|
|
May 26 03:20:04 PM PDT 24 |
May 26 03:20:30 PM PDT 24 |
604553471 ps |
| T1279 |
/workspace/coverage/cover_reg_top/62.xbar_error_random.22933839 |
|
|
May 26 03:33:02 PM PDT 24 |
May 26 03:33:24 PM PDT 24 |
222784513 ps |
| T530 |
/workspace/coverage/cover_reg_top/78.xbar_same_source.102114150 |
|
|
May 26 03:35:47 PM PDT 24 |
May 26 03:36:35 PM PDT 24 |
1576435006 ps |
| T853 |
/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.53414060 |
|
|
May 26 03:33:53 PM PDT 24 |
May 26 03:35:09 PM PDT 24 |
261067986 ps |
| T615 |
/workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.560496378 |
|
|
May 26 03:27:07 PM PDT 24 |
May 26 03:27:23 PM PDT 24 |
253325614 ps |
| T463 |
/workspace/coverage/cover_reg_top/81.xbar_stress_all.2568495265 |
|
|
May 26 03:36:23 PM PDT 24 |
May 26 03:44:48 PM PDT 24 |
12578672120 ps |
| T597 |
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2285403564 |
|
|
May 26 03:18:00 PM PDT 24 |
May 26 03:20:40 PM PDT 24 |
476296459 ps |
| T1280 |
/workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3441840429 |
|
|
May 26 03:34:33 PM PDT 24 |
May 26 03:35:45 PM PDT 24 |
4627959276 ps |
| T1281 |
/workspace/coverage/cover_reg_top/71.xbar_smoke.436043650 |
|
|
May 26 03:34:33 PM PDT 24 |
May 26 03:34:40 PM PDT 24 |
147024992 ps |
| T650 |
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.871281525 |
|
|
May 26 03:23:32 PM PDT 24 |
May 26 03:29:15 PM PDT 24 |
9289818726 ps |
| T1282 |
/workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4233952708 |
|
|
May 26 03:30:05 PM PDT 24 |
May 26 03:30:11 PM PDT 24 |
18699656 ps |
| T638 |
/workspace/coverage/cover_reg_top/35.xbar_smoke.3571151072 |
|
|
May 26 03:28:03 PM PDT 24 |
May 26 03:28:13 PM PDT 24 |
186122530 ps |
| T838 |
/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2660375953 |
|
|
May 26 03:36:30 PM PDT 24 |
May 26 03:51:29 PM PDT 24 |
44928695068 ps |
| T839 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3314589357 |
|
|
May 26 03:22:43 PM PDT 24 |
May 26 03:34:21 PM PDT 24 |
37629631566 ps |
| T532 |
/workspace/coverage/cover_reg_top/29.xbar_same_source.4191301026 |
|
|
May 26 03:26:58 PM PDT 24 |
May 26 03:27:21 PM PDT 24 |
289663898 ps |
| T593 |
/workspace/coverage/cover_reg_top/15.xbar_random.1463070263 |
|
|
May 26 03:23:08 PM PDT 24 |
May 26 03:24:17 PM PDT 24 |
1690330820 ps |
| T483 |
/workspace/coverage/cover_reg_top/84.xbar_random_large_delays.2604790871 |
|
|
May 26 03:36:54 PM PDT 24 |
May 26 03:47:59 PM PDT 24 |
57586942019 ps |
| T489 |
/workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2822086735 |
|
|
May 26 03:20:41 PM PDT 24 |
May 26 03:22:15 PM PDT 24 |
8327829117 ps |
| T850 |
/workspace/coverage/cover_reg_top/85.xbar_access_same_device.3634656706 |
|
|
May 26 03:37:02 PM PDT 24 |
May 26 03:38:21 PM PDT 24 |
1100979431 ps |
| T619 |
/workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2714447126 |
|
|
May 26 03:39:28 PM PDT 24 |
May 26 03:39:58 PM PDT 24 |
646195267 ps |
| T512 |
/workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1447333441 |
|
|
May 26 03:27:39 PM PDT 24 |
May 26 03:29:15 PM PDT 24 |
8966093815 ps |
| T1283 |
/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1870520983 |
|
|
May 26 03:31:21 PM PDT 24 |
May 26 03:31:32 PM PDT 24 |
168238573 ps |
| T528 |
/workspace/coverage/cover_reg_top/48.xbar_random.2346579310 |
|
|
May 26 03:30:19 PM PDT 24 |
May 26 03:31:18 PM PDT 24 |
600327017 ps |
| T1284 |
/workspace/coverage/cover_reg_top/78.xbar_smoke.2881893838 |
|
|
May 26 03:35:45 PM PDT 24 |
May 26 03:35:55 PM PDT 24 |
218164790 ps |
| T622 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1526323666 |
|
|
May 26 03:22:39 PM PDT 24 |
May 26 03:24:13 PM PDT 24 |
5303669501 ps |
| T594 |
/workspace/coverage/cover_reg_top/48.xbar_same_source.26538708 |
|
|
May 26 03:30:23 PM PDT 24 |
May 26 03:31:06 PM PDT 24 |
1443094600 ps |
| T628 |
/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3805638853 |
|
|
May 26 03:34:33 PM PDT 24 |
May 26 03:42:07 PM PDT 24 |
12778201449 ps |
| T659 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2068898129 |
|
|
May 26 03:23:02 PM PDT 24 |
May 26 03:23:09 PM PDT 24 |
57560071 ps |
| T445 |
/workspace/coverage/cover_reg_top/95.xbar_same_source.1632748840 |
|
|
May 26 03:38:45 PM PDT 24 |
May 26 03:39:56 PM PDT 24 |
2412994740 ps |
| T452 |
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.4112083646 |
|
|
May 26 03:23:42 PM PDT 24 |
May 26 03:25:14 PM PDT 24 |
8564438592 ps |
| T846 |
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4004298722 |
|
|
May 26 03:18:22 PM PDT 24 |
May 26 03:34:50 PM PDT 24 |
21900101163 ps |
| T599 |
/workspace/coverage/cover_reg_top/61.xbar_smoke.2547942484 |
|
|
May 26 03:32:42 PM PDT 24 |
May 26 03:32:49 PM PDT 24 |
54710007 ps |
| T547 |
/workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2896366341 |
|
|
May 26 03:33:06 PM PDT 24 |
May 26 03:46:17 PM PDT 24 |
78083095052 ps |
| T626 |
/workspace/coverage/cover_reg_top/23.xbar_same_source.2913580992 |
|
|
May 26 03:25:24 PM PDT 24 |
May 26 03:25:51 PM PDT 24 |
898868646 ps |
| T665 |
/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1728379006 |
|
|
May 26 03:29:38 PM PDT 24 |
May 26 03:31:05 PM PDT 24 |
4768773275 ps |
| T1285 |
/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1724944961 |
|
|
May 26 03:28:06 PM PDT 24 |
May 26 03:28:59 PM PDT 24 |
31401634 ps |
| T1286 |
/workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1881945134 |
|
|
May 26 03:27:33 PM PDT 24 |
May 26 03:28:04 PM PDT 24 |
268512917 ps |