| T1037 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2915970688 |
|
|
May 26 04:01:10 PM PDT 24 |
May 26 04:06:59 PM PDT 24 |
2622516340 ps |
| T743 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1673782918 |
|
|
May 26 04:14:20 PM PDT 24 |
May 26 04:20:19 PM PDT 24 |
3856852472 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3446049887 |
|
|
May 26 04:08:35 PM PDT 24 |
May 26 04:18:15 PM PDT 24 |
4314828090 ps |
| T831 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3556300621 |
|
|
May 26 04:18:59 PM PDT 24 |
May 26 04:26:13 PM PDT 24 |
3622165900 ps |
| T370 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.173984865 |
|
|
May 26 04:11:26 PM PDT 24 |
May 26 04:18:48 PM PDT 24 |
4691868482 ps |
| T1039 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2963759460 |
|
|
May 26 04:04:34 PM PDT 24 |
May 26 04:08:33 PM PDT 24 |
2824955034 ps |
| T817 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.679597700 |
|
|
May 26 04:22:10 PM PDT 24 |
May 26 04:29:09 PM PDT 24 |
4086266560 ps |
| T1040 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.226556721 |
|
|
May 26 04:07:29 PM PDT 24 |
May 26 04:11:57 PM PDT 24 |
2925170864 ps |
| T368 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2003252716 |
|
|
May 26 03:50:00 PM PDT 24 |
May 26 07:23:12 PM PDT 24 |
76551040910 ps |
| T1041 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.255833279 |
|
|
May 26 04:18:00 PM PDT 24 |
May 26 04:24:52 PM PDT 24 |
3555923180 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.165801531 |
|
|
May 26 04:08:17 PM PDT 24 |
May 26 04:37:11 PM PDT 24 |
10482714988 ps |
| T1043 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2473947771 |
|
|
May 26 03:55:40 PM PDT 24 |
May 26 05:32:28 PM PDT 24 |
21640731295 ps |
| T824 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2637493540 |
|
|
May 26 04:20:00 PM PDT 24 |
May 26 04:24:23 PM PDT 24 |
3579853844 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1304262202 |
|
|
May 26 03:46:10 PM PDT 24 |
May 26 03:50:11 PM PDT 24 |
2234811268 ps |
| T13 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2059673355 |
|
|
May 26 04:04:20 PM PDT 24 |
May 26 04:09:11 PM PDT 24 |
3734616600 ps |
| T427 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2201220355 |
|
|
May 26 04:13:22 PM PDT 24 |
May 26 04:17:50 PM PDT 24 |
2917167860 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1293087215 |
|
|
May 26 03:49:46 PM PDT 24 |
May 26 03:54:29 PM PDT 24 |
3157527158 ps |
| T429 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.779892131 |
|
|
May 26 04:00:05 PM PDT 24 |
May 26 06:03:32 PM PDT 24 |
33947806768 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4209017368 |
|
|
May 26 04:00:50 PM PDT 24 |
May 26 04:27:14 PM PDT 24 |
8230637800 ps |
| T430 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3073627941 |
|
|
May 26 04:08:34 PM PDT 24 |
May 26 04:14:17 PM PDT 24 |
2644613888 ps |
| T431 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.873319571 |
|
|
May 26 03:50:06 PM PDT 24 |
May 26 04:04:34 PM PDT 24 |
3923389008 ps |
| T432 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2409965075 |
|
|
May 26 04:03:08 PM PDT 24 |
May 26 04:09:41 PM PDT 24 |
3052559732 ps |
| T433 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128497299 |
|
|
May 26 04:21:58 PM PDT 24 |
May 26 04:28:22 PM PDT 24 |
3372786206 ps |
| T434 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2396547060 |
|
|
May 26 03:59:04 PM PDT 24 |
May 26 04:02:35 PM PDT 24 |
3155039336 ps |
| T549 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.915589475 |
|
|
May 26 03:48:39 PM PDT 24 |
May 26 04:00:00 PM PDT 24 |
4568218232 ps |
| T1045 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2756491979 |
|
|
May 26 03:50:31 PM PDT 24 |
May 26 03:57:47 PM PDT 24 |
7343287880 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.4172456696 |
|
|
May 26 04:12:34 PM PDT 24 |
May 26 04:17:57 PM PDT 24 |
3166675512 ps |
| T829 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.77108476 |
|
|
May 26 04:27:49 PM PDT 24 |
May 26 04:34:07 PM PDT 24 |
3608182808 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3401265032 |
|
|
May 26 04:03:07 PM PDT 24 |
May 26 04:14:00 PM PDT 24 |
4084122470 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1802987686 |
|
|
May 26 03:53:01 PM PDT 24 |
May 26 03:58:23 PM PDT 24 |
3051746658 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2916279564 |
|
|
May 26 03:59:34 PM PDT 24 |
May 26 04:03:21 PM PDT 24 |
2703359248 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.17736282 |
|
|
May 26 04:09:55 PM PDT 24 |
May 26 04:14:52 PM PDT 24 |
2737972127 ps |
| T769 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2803106747 |
|
|
May 26 04:19:28 PM PDT 24 |
May 26 04:29:11 PM PDT 24 |
5389229808 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4251160896 |
|
|
May 26 03:49:13 PM PDT 24 |
May 26 04:01:05 PM PDT 24 |
4191824318 ps |
| T750 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3048507924 |
|
|
May 26 03:49:31 PM PDT 24 |
May 26 04:02:56 PM PDT 24 |
4769344646 ps |
| T1051 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3502647319 |
|
|
May 26 03:59:41 PM PDT 24 |
May 26 04:25:10 PM PDT 24 |
8270257144 ps |
| T1052 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2200233497 |
|
|
May 26 03:58:26 PM PDT 24 |
May 26 04:03:44 PM PDT 24 |
2670424949 ps |
| T1053 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.4107630771 |
|
|
May 26 04:01:49 PM PDT 24 |
May 26 04:06:13 PM PDT 24 |
3056906784 ps |
| T11 |
/workspace/coverage/default/2.chip_jtag_csr_rw.4229608512 |
|
|
May 26 04:02:38 PM PDT 24 |
May 26 04:25:34 PM PDT 24 |
12129379572 ps |
| T416 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.117759499 |
|
|
May 26 04:06:50 PM PDT 24 |
May 26 04:13:59 PM PDT 24 |
6229919864 ps |
| T417 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1525886965 |
|
|
May 26 04:18:27 PM PDT 24 |
May 26 04:29:18 PM PDT 24 |
4793175090 ps |
| T257 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.728537318 |
|
|
May 26 04:09:33 PM PDT 24 |
May 26 04:23:30 PM PDT 24 |
6040972504 ps |
| T418 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1327754848 |
|
|
May 26 03:50:02 PM PDT 24 |
May 26 03:54:26 PM PDT 24 |
3397270606 ps |
| T109 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.681559249 |
|
|
May 26 04:04:11 PM PDT 24 |
May 26 04:11:36 PM PDT 24 |
5423947894 ps |
| T419 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1323149839 |
|
|
May 26 03:59:48 PM PDT 24 |
May 26 04:09:22 PM PDT 24 |
2903129948 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.295571542 |
|
|
May 26 03:48:47 PM PDT 24 |
May 26 04:07:39 PM PDT 24 |
6635185341 ps |
| T421 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1235306281 |
|
|
May 26 04:18:11 PM PDT 24 |
May 26 04:23:50 PM PDT 24 |
3583227872 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1275497637 |
|
|
May 26 04:06:27 PM PDT 24 |
May 26 04:13:47 PM PDT 24 |
3831360590 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1586094849 |
|
|
May 26 03:49:43 PM PDT 24 |
May 26 04:22:58 PM PDT 24 |
8878239210 ps |
| T1055 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.821993896 |
|
|
May 26 04:01:09 PM PDT 24 |
May 26 05:13:54 PM PDT 24 |
14435510680 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1989776259 |
|
|
May 26 03:48:47 PM PDT 24 |
May 26 04:07:54 PM PDT 24 |
8298654900 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.259487322 |
|
|
May 26 04:04:29 PM PDT 24 |
May 26 04:19:09 PM PDT 24 |
5758254434 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2685806975 |
|
|
May 26 04:05:32 PM PDT 24 |
May 26 04:20:23 PM PDT 24 |
5436993560 ps |
| T1057 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2738802319 |
|
|
May 26 04:11:51 PM PDT 24 |
May 26 04:18:08 PM PDT 24 |
2800283354 ps |
| T818 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418224490 |
|
|
May 26 04:18:42 PM PDT 24 |
May 26 04:24:52 PM PDT 24 |
3744578716 ps |
| T347 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2562182935 |
|
|
May 26 04:15:09 PM PDT 24 |
May 26 04:29:08 PM PDT 24 |
5052475900 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2287778030 |
|
|
May 26 03:57:53 PM PDT 24 |
May 26 04:14:39 PM PDT 24 |
6001965336 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1132962261 |
|
|
May 26 03:59:41 PM PDT 24 |
May 26 04:04:32 PM PDT 24 |
3193322688 ps |
| T1060 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1529565311 |
|
|
May 26 04:04:03 PM PDT 24 |
May 26 04:15:29 PM PDT 24 |
4146923404 ps |
| T1061 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2205552325 |
|
|
May 26 04:08:38 PM PDT 24 |
May 26 04:20:28 PM PDT 24 |
9500148860 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3076821841 |
|
|
May 26 03:50:50 PM PDT 24 |
May 26 04:18:09 PM PDT 24 |
16477149859 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2539910797 |
|
|
May 26 03:51:38 PM PDT 24 |
May 26 04:12:38 PM PDT 24 |
7013961560 ps |
| T1064 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.613246199 |
|
|
May 26 04:15:36 PM PDT 24 |
May 26 04:20:05 PM PDT 24 |
3432329130 ps |
| T1065 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.6804983 |
|
|
May 26 03:58:20 PM PDT 24 |
May 26 04:07:00 PM PDT 24 |
4221458550 ps |
| T393 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2436990110 |
|
|
May 26 03:57:34 PM PDT 24 |
May 26 05:39:19 PM PDT 24 |
21963538426 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1616568013 |
|
|
May 26 03:59:41 PM PDT 24 |
May 26 04:03:13 PM PDT 24 |
2127173870 ps |
| T1067 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1455867857 |
|
|
May 26 04:11:22 PM PDT 24 |
May 26 04:15:43 PM PDT 24 |
3198450320 ps |
| T815 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2393057705 |
|
|
May 26 04:23:20 PM PDT 24 |
May 26 04:31:45 PM PDT 24 |
5219154480 ps |
| T1068 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.342705719 |
|
|
May 26 03:49:40 PM PDT 24 |
May 26 03:59:59 PM PDT 24 |
5107441800 ps |
| T798 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2165958287 |
|
|
May 26 04:18:37 PM PDT 24 |
May 26 04:24:01 PM PDT 24 |
4015455400 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.359591984 |
|
|
May 26 03:57:54 PM PDT 24 |
May 26 04:02:45 PM PDT 24 |
3202027301 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2007407838 |
|
|
May 26 04:05:59 PM PDT 24 |
May 26 04:27:05 PM PDT 24 |
5802573098 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2923277357 |
|
|
May 26 03:51:46 PM PDT 24 |
May 26 04:02:00 PM PDT 24 |
4931583958 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3008926751 |
|
|
May 26 04:07:56 PM PDT 24 |
May 26 04:24:11 PM PDT 24 |
6486405544 ps |
| T791 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1279558743 |
|
|
May 26 04:21:05 PM PDT 24 |
May 26 04:31:44 PM PDT 24 |
6502923300 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3908805643 |
|
|
May 26 03:51:04 PM PDT 24 |
May 26 04:25:25 PM PDT 24 |
11602894225 ps |
| T1072 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.245835763 |
|
|
May 26 04:15:48 PM PDT 24 |
May 26 04:22:21 PM PDT 24 |
3493947936 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4257004205 |
|
|
May 26 03:56:51 PM PDT 24 |
May 26 04:05:37 PM PDT 24 |
5844911547 ps |
| T805 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2941455936 |
|
|
May 26 04:16:55 PM PDT 24 |
May 26 04:27:28 PM PDT 24 |
5620628620 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4106016343 |
|
|
May 26 03:48:04 PM PDT 24 |
May 26 03:57:39 PM PDT 24 |
5711136456 ps |
| T61 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2861143682 |
|
|
May 26 03:57:45 PM PDT 24 |
May 26 05:00:28 PM PDT 24 |
14243109519 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.3750222923 |
|
|
May 26 04:04:08 PM PDT 24 |
May 26 04:08:37 PM PDT 24 |
3413306600 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1365127139 |
|
|
May 26 03:56:07 PM PDT 24 |
May 26 04:00:37 PM PDT 24 |
3128967056 ps |
| T252 |
/workspace/coverage/default/0.chip_sw_flash_init.3305989533 |
|
|
May 26 03:48:25 PM PDT 24 |
May 26 04:27:26 PM PDT 24 |
21353443652 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.908523416 |
|
|
May 26 03:54:54 PM PDT 24 |
May 26 04:00:40 PM PDT 24 |
3277461304 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4128040398 |
|
|
May 26 04:01:35 PM PDT 24 |
May 26 04:39:13 PM PDT 24 |
11297614994 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.3654391834 |
|
|
May 26 04:04:56 PM PDT 24 |
May 26 04:14:42 PM PDT 24 |
4676127650 ps |
| T1080 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.941551825 |
|
|
May 26 04:03:33 PM PDT 24 |
May 26 04:22:01 PM PDT 24 |
7406973959 ps |
| T752 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2584576192 |
|
|
May 26 04:21:48 PM PDT 24 |
May 26 04:32:26 PM PDT 24 |
5539915320 ps |
| T1081 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.659978221 |
|
|
May 26 04:08:56 PM PDT 24 |
May 26 05:00:52 PM PDT 24 |
13826412298 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.846606491 |
|
|
May 26 03:54:28 PM PDT 24 |
May 26 04:17:43 PM PDT 24 |
6364865126 ps |
| T1082 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1275169986 |
|
|
May 26 04:17:57 PM PDT 24 |
May 26 04:28:05 PM PDT 24 |
4430245180 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3215559398 |
|
|
May 26 04:08:43 PM PDT 24 |
May 26 04:14:25 PM PDT 24 |
2924823888 ps |
| T1084 |
/workspace/coverage/default/2.chip_sw_hmac_enc.2394137021 |
|
|
May 26 04:08:56 PM PDT 24 |
May 26 04:13:36 PM PDT 24 |
3386131240 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4096161362 |
|
|
May 26 03:49:56 PM PDT 24 |
May 26 07:27:32 PM PDT 24 |
255679971000 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_gpio.658347372 |
|
|
May 26 03:47:21 PM PDT 24 |
May 26 03:54:46 PM PDT 24 |
3547770075 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_power_idle_load.2475085373 |
|
|
May 26 03:50:24 PM PDT 24 |
May 26 04:00:11 PM PDT 24 |
3651748920 ps |
| T1087 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2584373293 |
|
|
May 26 04:18:47 PM PDT 24 |
May 26 05:14:03 PM PDT 24 |
13701311168 ps |
| T744 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1727227737 |
|
|
May 26 04:21:45 PM PDT 24 |
May 26 04:32:48 PM PDT 24 |
4683172608 ps |
| T822 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1701538481 |
|
|
May 26 04:22:50 PM PDT 24 |
May 26 04:32:17 PM PDT 24 |
6053623694 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.993868965 |
|
|
May 26 04:02:58 PM PDT 24 |
May 26 04:12:02 PM PDT 24 |
6056244170 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2379403966 |
|
|
May 26 03:51:42 PM PDT 24 |
May 26 03:56:43 PM PDT 24 |
2990967806 ps |
| T313 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.344946089 |
|
|
May 26 04:24:36 PM PDT 24 |
May 26 04:31:04 PM PDT 24 |
4659130884 ps |
| T1090 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.536704563 |
|
|
May 26 04:19:37 PM PDT 24 |
May 26 04:27:55 PM PDT 24 |
5536673628 ps |
| T1091 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3655669194 |
|
|
May 26 04:13:42 PM PDT 24 |
May 26 04:22:27 PM PDT 24 |
4677864823 ps |
| T1092 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.414010343 |
|
|
May 26 04:08:22 PM PDT 24 |
May 26 05:01:37 PM PDT 24 |
14443142546 ps |
| T348 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.510164862 |
|
|
May 26 04:00:08 PM PDT 24 |
May 26 04:10:09 PM PDT 24 |
4974271793 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.547999986 |
|
|
May 26 04:12:11 PM PDT 24 |
May 26 04:15:22 PM PDT 24 |
2453175368 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1653318685 |
|
|
May 26 03:53:16 PM PDT 24 |
May 26 07:35:27 PM PDT 24 |
77683054416 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1713610190 |
|
|
May 26 04:08:49 PM PDT 24 |
May 26 04:19:42 PM PDT 24 |
4448627946 ps |
| T1096 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.82534595 |
|
|
May 26 04:15:45 PM PDT 24 |
May 26 04:37:07 PM PDT 24 |
8288488024 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2695561993 |
|
|
May 26 03:54:01 PM PDT 24 |
May 26 04:07:38 PM PDT 24 |
4937155800 ps |
| T1098 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1983390922 |
|
|
May 26 03:49:10 PM PDT 24 |
May 26 04:07:22 PM PDT 24 |
5595727280 ps |
| T1099 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1714128211 |
|
|
May 26 03:58:25 PM PDT 24 |
May 26 04:02:25 PM PDT 24 |
2452912855 ps |
| T1100 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1013528014 |
|
|
May 26 03:51:34 PM PDT 24 |
May 26 05:03:57 PM PDT 24 |
18345359874 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2168282635 |
|
|
May 26 04:11:15 PM PDT 24 |
May 26 04:15:48 PM PDT 24 |
2724911602 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.399843407 |
|
|
May 26 03:50:04 PM PDT 24 |
May 26 03:56:27 PM PDT 24 |
4834261118 ps |
| T1102 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2327804979 |
|
|
May 26 04:23:34 PM PDT 24 |
May 26 04:31:48 PM PDT 24 |
6251699128 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2652127403 |
|
|
May 26 03:52:45 PM PDT 24 |
May 26 04:00:57 PM PDT 24 |
5820242106 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3604494308 |
|
|
May 26 04:09:22 PM PDT 24 |
May 26 04:13:02 PM PDT 24 |
2460841936 ps |
| T1104 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1932475748 |
|
|
May 26 03:49:23 PM PDT 24 |
May 26 04:00:11 PM PDT 24 |
5412029718 ps |
| T1105 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3814444593 |
|
|
May 26 04:19:49 PM PDT 24 |
May 26 04:26:27 PM PDT 24 |
3530246080 ps |
| T795 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2053270333 |
|
|
May 26 04:20:24 PM PDT 24 |
May 26 04:31:55 PM PDT 24 |
4826477450 ps |
| T1106 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.782232925 |
|
|
May 26 04:16:49 PM PDT 24 |
May 26 05:04:39 PM PDT 24 |
14270251924 ps |
| T412 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.756831303 |
|
|
May 26 03:52:08 PM PDT 24 |
May 26 03:56:39 PM PDT 24 |
3632815132 ps |
| T1107 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.514818102 |
|
|
May 26 04:00:25 PM PDT 24 |
May 26 04:06:16 PM PDT 24 |
4107770472 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.343088067 |
|
|
May 26 04:01:33 PM PDT 24 |
May 26 04:06:39 PM PDT 24 |
3014222999 ps |
| T1109 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2493793368 |
|
|
May 26 03:59:13 PM PDT 24 |
May 26 04:17:53 PM PDT 24 |
4794068094 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3646024575 |
|
|
May 26 03:49:22 PM PDT 24 |
May 26 03:59:22 PM PDT 24 |
3523872804 ps |
| T308 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1244770389 |
|
|
May 26 04:03:27 PM PDT 24 |
May 26 04:08:14 PM PDT 24 |
2700522490 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2960289868 |
|
|
May 26 04:00:12 PM PDT 24 |
May 26 04:10:47 PM PDT 24 |
3738693480 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1414773348 |
|
|
May 26 04:06:51 PM PDT 24 |
May 26 04:12:14 PM PDT 24 |
2666168360 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3369478532 |
|
|
May 26 03:58:23 PM PDT 24 |
May 26 04:05:44 PM PDT 24 |
3703359464 ps |
| T1113 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1516934056 |
|
|
May 26 04:17:50 PM PDT 24 |
May 26 04:43:56 PM PDT 24 |
8011166076 ps |
| T1114 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3102949983 |
|
|
May 26 04:18:39 PM PDT 24 |
May 26 04:23:26 PM PDT 24 |
3742035160 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2213621988 |
|
|
May 26 03:53:37 PM PDT 24 |
May 26 04:00:03 PM PDT 24 |
5404173398 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3689852648 |
|
|
May 26 03:58:14 PM PDT 24 |
May 26 04:13:31 PM PDT 24 |
6578341352 ps |
| T240 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3575440967 |
|
|
May 26 04:02:51 PM PDT 24 |
May 26 04:08:45 PM PDT 24 |
3421926450 ps |
| T234 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2383794723 |
|
|
May 26 03:52:32 PM PDT 24 |
May 26 04:43:51 PM PDT 24 |
20094950437 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3020308725 |
|
|
May 26 03:46:58 PM PDT 24 |
May 26 03:59:38 PM PDT 24 |
6153886058 ps |
| T198 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1867401200 |
|
|
May 26 03:46:19 PM PDT 24 |
May 26 03:58:44 PM PDT 24 |
7074298267 ps |
| T339 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510798497 |
|
|
May 26 04:23:15 PM PDT 24 |
May 26 04:29:11 PM PDT 24 |
4136578100 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1911195876 |
|
|
May 26 04:02:36 PM PDT 24 |
May 26 04:06:06 PM PDT 24 |
2625481865 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4035400778 |
|
|
May 26 04:07:40 PM PDT 24 |
May 26 04:25:04 PM PDT 24 |
5476564058 ps |
| T341 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2566468908 |
|
|
May 26 04:22:17 PM PDT 24 |
May 26 04:31:52 PM PDT 24 |
5596845456 ps |
| T342 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.499586212 |
|
|
May 26 04:19:24 PM PDT 24 |
May 26 04:29:43 PM PDT 24 |
4697571160 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1072291285 |
|
|
May 26 04:05:55 PM PDT 24 |
May 26 04:12:34 PM PDT 24 |
3496714381 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1925597910 |
|
|
May 26 03:54:11 PM PDT 24 |
May 26 04:05:35 PM PDT 24 |
4223118696 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.661359345 |
|
|
May 26 03:57:55 PM PDT 24 |
May 26 04:08:08 PM PDT 24 |
3317995706 ps |
| T1117 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.953671148 |
|
|
May 26 04:15:34 PM PDT 24 |
May 26 04:25:36 PM PDT 24 |
7524819066 ps |
| T1118 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.534197395 |
|
|
May 26 04:05:04 PM PDT 24 |
May 26 04:08:07 PM PDT 24 |
2996954148 ps |
| T1119 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.268839591 |
|
|
May 26 04:16:34 PM PDT 24 |
May 26 04:27:01 PM PDT 24 |
3721652052 ps |
| T371 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1120385500 |
|
|
May 26 03:50:35 PM PDT 24 |
May 26 04:00:22 PM PDT 24 |
5831368528 ps |
| T1120 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3046692654 |
|
|
May 26 04:21:25 PM PDT 24 |
May 26 04:30:35 PM PDT 24 |
4311996790 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.1044790035 |
|
|
May 26 03:51:46 PM PDT 24 |
May 26 03:56:49 PM PDT 24 |
2799962918 ps |
| T1121 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2768532899 |
|
|
May 26 03:47:40 PM PDT 24 |
May 26 04:08:45 PM PDT 24 |
8757936475 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.556197585 |
|
|
May 26 04:08:11 PM PDT 24 |
May 26 04:22:53 PM PDT 24 |
6450692560 ps |
| T1123 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1926607055 |
|
|
May 26 04:07:58 PM PDT 24 |
May 26 05:09:27 PM PDT 24 |
15072846216 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1936410912 |
|
|
May 26 03:57:28 PM PDT 24 |
May 26 04:01:55 PM PDT 24 |
2639571010 ps |
| T1125 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.177650407 |
|
|
May 26 03:52:50 PM PDT 24 |
May 26 04:05:03 PM PDT 24 |
4867941854 ps |
| T356 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3623690625 |
|
|
May 26 04:20:38 PM PDT 24 |
May 26 04:26:13 PM PDT 24 |
3478255340 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2470822331 |
|
|
May 26 04:09:32 PM PDT 24 |
May 26 04:13:57 PM PDT 24 |
3111946640 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1600744685 |
|
|
May 26 03:50:47 PM PDT 24 |
May 26 04:00:43 PM PDT 24 |
6297018768 ps |
| T1127 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1627772898 |
|
|
May 26 03:50:58 PM PDT 24 |
May 26 04:01:10 PM PDT 24 |
5971171730 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3620008450 |
|
|
May 26 04:14:19 PM PDT 24 |
May 26 05:03:53 PM PDT 24 |
24851262667 ps |
| T799 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.316350312 |
|
|
May 26 04:20:22 PM PDT 24 |
May 26 04:26:18 PM PDT 24 |
3584394400 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.586638316 |
|
|
May 26 03:57:58 PM PDT 24 |
May 26 04:56:24 PM PDT 24 |
20099198523 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1400466423 |
|
|
May 26 03:52:48 PM PDT 24 |
May 26 03:58:54 PM PDT 24 |
3348528728 ps |
| T1131 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2604992242 |
|
|
May 26 04:17:46 PM PDT 24 |
May 26 04:40:47 PM PDT 24 |
7992708104 ps |
| T1132 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2144100337 |
|
|
May 26 03:47:25 PM PDT 24 |
May 26 03:57:11 PM PDT 24 |
4342656920 ps |
| T1133 |
/workspace/coverage/default/4.chip_tap_straps_dev.531714893 |
|
|
May 26 04:15:36 PM PDT 24 |
May 26 04:28:57 PM PDT 24 |
8392249659 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3407296364 |
|
|
May 26 04:08:48 PM PDT 24 |
May 26 04:33:26 PM PDT 24 |
8291213094 ps |
| T709 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.923630585 |
|
|
May 26 04:11:38 PM PDT 24 |
May 26 04:18:00 PM PDT 24 |
5131134467 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2187694389 |
|
|
May 26 04:01:11 PM PDT 24 |
May 26 04:09:41 PM PDT 24 |
4299506316 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_edn_kat.2779732140 |
|
|
May 26 04:08:46 PM PDT 24 |
May 26 04:19:45 PM PDT 24 |
3469387700 ps |
| T374 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2522151820 |
|
|
May 26 04:21:05 PM PDT 24 |
May 26 04:27:25 PM PDT 24 |
3776590472 ps |
| T96 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.302995239 |
|
|
May 26 03:49:57 PM PDT 24 |
May 26 03:54:56 PM PDT 24 |
2720448339 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2450567475 |
|
|
May 26 04:01:56 PM PDT 24 |
May 26 04:24:16 PM PDT 24 |
19049177688 ps |
| T808 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1962564550 |
|
|
May 26 04:23:26 PM PDT 24 |
May 26 04:33:27 PM PDT 24 |
4139825188 ps |
| T1137 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1880475558 |
|
|
May 26 03:55:45 PM PDT 24 |
May 26 04:51:36 PM PDT 24 |
14634400592 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.927660935 |
|
|
May 26 03:53:19 PM PDT 24 |
May 26 03:58:29 PM PDT 24 |
3258341984 ps |
| T813 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825982822 |
|
|
May 26 04:22:23 PM PDT 24 |
May 26 04:28:36 PM PDT 24 |
4190896040 ps |
| T1139 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2771358081 |
|
|
May 26 04:01:01 PM PDT 24 |
May 26 04:07:01 PM PDT 24 |
3478829646 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1715323917 |
|
|
May 26 04:13:25 PM PDT 24 |
May 26 04:24:36 PM PDT 24 |
4871129242 ps |
| T786 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.732496761 |
|
|
May 26 04:20:59 PM PDT 24 |
May 26 04:27:08 PM PDT 24 |
3490794372 ps |
| T94 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1862595668 |
|
|
May 26 03:48:36 PM PDT 24 |
May 26 03:56:48 PM PDT 24 |
6544984700 ps |
| T797 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305866556 |
|
|
May 26 04:16:36 PM PDT 24 |
May 26 04:22:31 PM PDT 24 |
3478257926 ps |
| T1141 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1842777675 |
|
|
May 26 04:10:40 PM PDT 24 |
May 26 04:20:13 PM PDT 24 |
4686306874 ps |
| T1142 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1826010357 |
|
|
May 26 03:56:22 PM PDT 24 |
May 26 05:31:16 PM PDT 24 |
22378350352 ps |
| T349 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2893733887 |
|
|
May 26 04:11:14 PM PDT 24 |
May 26 04:20:32 PM PDT 24 |
5145957275 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1673221066 |
|
|
May 26 04:08:38 PM PDT 24 |
May 26 04:13:03 PM PDT 24 |
3407451436 ps |
| T350 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3704788383 |
|
|
May 26 04:00:32 PM PDT 24 |
May 26 04:07:01 PM PDT 24 |
3217525776 ps |
| T772 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599745999 |
|
|
May 26 04:18:59 PM PDT 24 |
May 26 04:26:16 PM PDT 24 |
4423434322 ps |
| T106 |
/workspace/coverage/default/1.chip_tap_straps_rma.3736767805 |
|
|
May 26 04:01:51 PM PDT 24 |
May 26 04:07:48 PM PDT 24 |
4430738072 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1672728727 |
|
|
May 26 04:07:40 PM PDT 24 |
May 26 04:16:46 PM PDT 24 |
7834395026 ps |
| T351 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2508547194 |
|
|
May 26 04:09:23 PM PDT 24 |
May 26 04:22:22 PM PDT 24 |
4368197437 ps |
| T1144 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183830414 |
|
|
May 26 04:18:24 PM PDT 24 |
May 26 04:23:56 PM PDT 24 |
3611074168 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1667269545 |
|
|
May 26 04:04:13 PM PDT 24 |
May 26 04:09:12 PM PDT 24 |
2836534430 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.504393130 |
|
|
May 26 03:55:43 PM PDT 24 |
May 26 04:01:50 PM PDT 24 |
4709270864 ps |
| T1147 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2806547719 |
|
|
May 26 04:00:35 PM PDT 24 |
May 26 05:14:10 PM PDT 24 |
14293498068 ps |
| T785 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.687296465 |
|
|
May 26 04:20:26 PM PDT 24 |
May 26 04:27:04 PM PDT 24 |
4124638766 ps |
| T1148 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.807519491 |
|
|
May 26 04:04:39 PM PDT 24 |
May 26 04:08:44 PM PDT 24 |
2743021598 ps |
| T1149 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3764568690 |
|
|
May 26 04:09:20 PM PDT 24 |
May 26 05:03:49 PM PDT 24 |
14055636038 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2969551328 |
|
|
May 26 04:03:19 PM PDT 24 |
May 26 04:39:24 PM PDT 24 |
10835345992 ps |
| T1151 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2954534125 |
|
|
May 26 04:01:08 PM PDT 24 |
May 26 05:57:02 PM PDT 24 |
21158331670 ps |
| T141 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1063083852 |
|
|
May 26 04:09:54 PM PDT 24 |
May 26 04:21:03 PM PDT 24 |
4327960596 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1786905012 |
|
|
May 26 04:07:44 PM PDT 24 |
May 26 04:53:48 PM PDT 24 |
34968131986 ps |
| T787 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941885095 |
|
|
May 26 04:21:59 PM PDT 24 |
May 26 04:26:47 PM PDT 24 |
3492525392 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.609751733 |
|
|
May 26 03:52:57 PM PDT 24 |
May 26 03:56:41 PM PDT 24 |
2415126024 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.216859926 |
|
|
May 26 03:48:01 PM PDT 24 |
May 26 03:51:15 PM PDT 24 |
2313829038 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1166238477 |
|
|
May 26 03:49:34 PM PDT 24 |
May 26 03:57:11 PM PDT 24 |
5314142472 ps |
| T1155 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2676365226 |
|
|
May 26 03:48:43 PM PDT 24 |
May 26 03:56:58 PM PDT 24 |
6534404974 ps |
| T269 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2470855695 |
|
|
May 26 03:53:55 PM PDT 24 |
May 26 04:08:31 PM PDT 24 |
5048544096 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2032369451 |
|
|
May 26 03:52:56 PM PDT 24 |
May 26 04:05:42 PM PDT 24 |
7714259424 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_aes_idle.1828060369 |
|
|
May 26 03:50:09 PM PDT 24 |
May 26 03:53:25 PM PDT 24 |
2343593560 ps |
| T156 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2849568200 |
|
|
May 26 04:11:37 PM PDT 24 |
May 26 05:21:36 PM PDT 24 |
28941125905 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1306449324 |
|
|
May 26 03:56:37 PM PDT 24 |
May 26 04:06:07 PM PDT 24 |
4295769528 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.65499182 |
|
|
May 26 03:47:02 PM PDT 24 |
May 26 03:50:17 PM PDT 24 |
2600141864 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3512827167 |
|
|
May 26 04:01:38 PM PDT 24 |
May 26 04:31:04 PM PDT 24 |
22043095560 ps |
| T124 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1674307038 |
|
|
May 26 04:01:42 PM PDT 24 |
May 26 04:08:47 PM PDT 24 |
7143112840 ps |
| T1159 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.87651367 |
|
|
May 26 04:05:32 PM PDT 24 |
May 26 04:17:06 PM PDT 24 |
5942958206 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.411657213 |
|
|
May 26 03:47:31 PM PDT 24 |
May 26 04:02:09 PM PDT 24 |
5527557618 ps |
| T1160 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.254171815 |
|
|
May 26 04:02:06 PM PDT 24 |
May 26 04:14:27 PM PDT 24 |
8266235307 ps |
| T1161 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1604854988 |
|
|
May 26 04:07:23 PM PDT 24 |
May 26 04:13:35 PM PDT 24 |
3261700470 ps |
| T125 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3231102134 |
|
|
May 26 03:49:46 PM PDT 24 |
May 26 04:23:49 PM PDT 24 |
21516957008 ps |
| T754 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3545272721 |
|
|
May 26 03:58:30 PM PDT 24 |
May 26 07:24:49 PM PDT 24 |
255656547720 ps |
| T823 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2270404470 |
|
|
May 26 04:17:44 PM PDT 24 |
May 26 04:25:18 PM PDT 24 |
4116180438 ps |
| T1162 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.821463150 |
|
|
May 26 04:20:08 PM PDT 24 |
May 26 04:29:55 PM PDT 24 |
5564079550 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4039747649 |
|
|
May 26 04:13:14 PM PDT 24 |
May 26 04:17:36 PM PDT 24 |
3300556056 ps |
| T762 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.610144783 |
|
|
May 26 04:16:24 PM PDT 24 |
May 26 04:28:42 PM PDT 24 |
4604572274 ps |
| T794 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2942050440 |
|
|
May 26 04:21:58 PM PDT 24 |
May 26 04:32:16 PM PDT 24 |
5558084536 ps |
| T759 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2171026848 |
|
|
May 26 04:20:07 PM PDT 24 |
May 26 04:32:41 PM PDT 24 |
5081851102 ps |
| T357 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1465540156 |
|
|
May 26 04:21:45 PM PDT 24 |
May 26 04:29:04 PM PDT 24 |
4343553800 ps |
| T90 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4266628797 |
|
|
May 26 04:05:18 PM PDT 24 |
May 26 04:10:23 PM PDT 24 |
2633767936 ps |
| T1164 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3540831935 |
|
|
May 26 03:55:12 PM PDT 24 |
May 26 04:49:09 PM PDT 24 |
13384050000 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.587134488 |
|
|
May 26 04:08:04 PM PDT 24 |
May 26 04:32:20 PM PDT 24 |
12344075154 ps |
| T1166 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3945153031 |
|
|
May 26 03:57:32 PM PDT 24 |
May 26 05:13:55 PM PDT 24 |
22516138040 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2603780612 |
|
|
May 26 04:04:25 PM PDT 24 |
May 26 04:21:28 PM PDT 24 |
5820890500 ps |
| T1168 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1220167191 |
|
|
May 26 03:55:23 PM PDT 24 |
May 26 04:43:36 PM PDT 24 |
13556583635 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.528780567 |
|
|
May 26 03:50:33 PM PDT 24 |
May 26 03:54:56 PM PDT 24 |
2413317116 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.1819835692 |
|
|
May 26 04:15:45 PM PDT 24 |
May 26 04:28:09 PM PDT 24 |
4267000296 ps |
| T1171 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2237633122 |
|
|
May 26 03:59:48 PM PDT 24 |
May 26 04:04:13 PM PDT 24 |
3490881750 ps |
| T739 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.416364164 |
|
|
May 26 03:59:16 PM PDT 24 |
May 26 04:14:28 PM PDT 24 |
4944719852 ps |
| T789 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190342054 |
|
|
May 26 04:18:57 PM PDT 24 |
May 26 04:24:58 PM PDT 24 |
3889080784 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3199737284 |
|
|
May 26 03:49:45 PM PDT 24 |
May 26 04:24:16 PM PDT 24 |
10253196588 ps |
| T746 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.649978649 |
|
|
May 26 04:22:21 PM PDT 24 |
May 26 04:32:57 PM PDT 24 |
4876546972 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.778105751 |
|
|
May 26 03:49:44 PM PDT 24 |
May 26 03:54:49 PM PDT 24 |
3329495928 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1735352564 |
|
|
May 26 03:51:05 PM PDT 24 |
May 26 04:15:34 PM PDT 24 |
6794956336 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4235278264 |
|
|
May 26 03:53:26 PM PDT 24 |
May 26 03:59:36 PM PDT 24 |
3920764856 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3935715176 |
|
|
May 26 03:52:45 PM PDT 24 |
May 26 03:57:22 PM PDT 24 |
2777925208 ps |