Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.66			80.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_device	90.00			90.00

---

Module Instance : tb.dut.top_earlgrey.u_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	61	42	68.85
Total Bits	424	342	80.66
Total Bits 0->1	212	171	80.66
Total Bits 1->0	212	171	80.66

Ports	61	42	68.85
Port Bits	424	342	80.66
Port Bits 0->1	212	171	80.66
Port Bits 1->0	212	171	80.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[12:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	INPUT
tl_o.a_ready	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T124,T96,T97	Yes	T95,T30,T124	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T30,T124	Yes	T95,T124,T96	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T95,*T124,*T96	Yes	T95,T30,T124	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T124,T96,T97	Yes	T95,T30,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T30,*T124	Yes	T95,T124,T96	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T166,T43,T30	Yes	T166,T43,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T166,T43,T30	Yes	T166,T43,T30	OUTPUT
cio_sck_i	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_csb_i	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_sd_o[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T96,T97,T202	Yes	T96,T97,T202	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_tpm_csb_i	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T96,T97,T180	Yes	T95,T96,T97	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T96,T97,T78	Yes	T96,T97,T78	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T78,T79,T119	Yes	T78,T79,T119	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
sck_monitor_o	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_device

	Total	Covered	Percent
Totals	51	42	82.35
Total Bits	380	342	90.00
Total Bits 0->1	190	171	90.00
Total Bits 1->0	190	171	90.00

Ports	51	42	82.35
Port Bits	380	342	90.00
Port Bits 0->1	190	171	90.00
Port Bits 1->0	190	171	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[12:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:13]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	INPUT
tl_o.a_ready	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T124,T96,T97	Yes	T95,T30,T124	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T30,T124	Yes	T95,T124,T96	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T95,*T124,*T96	Yes	T95,T30,T124	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T124,T96,T97	Yes	T95,T30,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T30,*T124	Yes	T95,T124,T96	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T95,T30,T124	Yes	T95,T30,T124	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T166,T43,T30	Yes	T166,T43,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T166,T43,T30	Yes	T166,T43,T30	OUTPUT
cio_sck_i	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_csb_i	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_sd_o[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T96,T97,T202	Yes	T96,T97,T202	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
cio_tpm_csb_i	Yes	Yes	T119,T120,T121	Yes	T119,T120,T121	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.csb_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.csb	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.sck_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off.
passthrough_o.sck	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T96,T97,T180	Yes	T95,T96,T97	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T96,T97,T78	Yes	T96,T97,T78	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T78,T79,T119	Yes	T78,T79,T119	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
sck_monitor_o	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range