Unified Coverage Report :: Module :: ibex_top

Module : ibex_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.04			94.04

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ibex_ibex_top_0.1/rtl/ibex_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_core	96.38			96.38

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.38			96.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.38			96.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.31	96.47	89.29	87.59		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : ibex_top

	Total	Covered	Percent
Totals	40	33	82.50
Total Bits	822	773	94.04
Total Bits 0->1	411	387	94.16
Total Bits 1->0	411	386	93.92

Ports	40	33	82.50
Port Bits	822	773	94.04
Port Bits 0->1	411	387	94.16
Port Bits 1->0	411	386	93.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
instr_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T280,T281,T282	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	T18,*T63,*T173	Yes	T18,T63,T173	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_err_i	Yes	Yes	T18,T63,T175	Yes	T18,T63,T175	INPUT
data_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_we_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_be_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_err_i	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
irq_software_i	Yes	Yes	T134,T263,T270	Yes	T134,T263,T270	INPUT
irq_timer_i	Yes	Yes	T283,T78,T284	Yes	T283,T78,T284	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T4,T6,T48	Yes	T4,T6,T48	INPUT
scramble_key_valid_i	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
scramble_key_i[127:0]	Yes	Yes	T4,T5,T67	Yes	T4,T5,T18	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T6,T68,T18	Yes	T6,T67,T68	INPUT
scramble_req_o	Yes	Yes	T18,T89,T90	Yes	T18,T89,T90	OUTPUT
debug_req_i	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T274,T275,T276	Yes	T274,T275,T276	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T4,T6,T67	Yes	T4,T5,T6	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	Yes	Yes	T392,T393,T394	Yes	T392,T393,T394	OUTPUT
alert_major_bus_o	Yes	Yes	T62,T173,T87	Yes	T62,T173,T87	OUTPUT
core_sleep_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_core

	Total	Covered	Percent
Totals	36	33	91.67
Total Bits	802	773	96.38
Total Bits 0->1	401	387	96.51
Total Bits 1->0	401	386	96.26

Ports	36	33	91.67
Port Bits	802	773	96.38
Port Bits 0->1	401	387	96.51
Port Bits 1->0	401	386	96.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
test_en_i	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
instr_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
instr_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
instr_addr_o[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
instr_addr_o[18:17]	No	No		No		OUTPUT
instr_addr_o[19]	No	No		Yes	T280,T281,T282	OUTPUT
instr_addr_o[27:20]	No	No		No		OUTPUT
instr_addr_o[29:28]	Yes	Yes	T18,*T63,*T173	Yes	T18,T63,T173	OUTPUT
instr_addr_o[31:30]	No	No		No		OUTPUT
instr_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
instr_err_i	Yes	Yes	T18,T63,T175	Yes	T18,T63,T175	INPUT
data_req_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_gnt_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rvalid_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_we_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_be_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_addr_o[1:0]	Unreachable	Unreachable		Unreachable		OUTPUT
data_addr_o[31:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_o[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_wdata_intg_o[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
data_rdata_i[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_rdata_intg_i[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
data_err_i	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
irq_software_i	Yes	Yes	T134,T263,T270	Yes	T134,T263,T270	INPUT
irq_timer_i	Yes	Yes	T283,T78,T284	Yes	T283,T78,T284	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_fast_i[14:0]	Unreachable	Unreachable		Unreachable		INPUT
irq_nm_i	Yes	Yes	T4,T6,T48	Yes	T4,T6,T48	INPUT
scramble_key_valid_i	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
scramble_key_i[127:0]	Yes	Yes	T4,T5,T67	Yes	T4,T5,T18	INPUT
scramble_nonce_i[63:0]	Yes	Yes	T6,T68,T18	Yes	T6,T67,T68	INPUT
scramble_req_o	Yes	Yes	T18,T89,T90	Yes	T18,T89,T90	OUTPUT
debug_req_i	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	INPUT
crash_dump_o.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
double_fault_seen_o	Yes	Yes	T274,T275,T276	Yes	T274,T275,T276	OUTPUT
fetch_enable_i[3:0]	Yes	Yes	T4,T6,T67	Yes	T4,T5,T6	INPUT
alert_minor_o	No	No		No		OUTPUT
alert_major_internal_o	Yes	Yes	T392,T393,T394	Yes	T392,T393,T394	OUTPUT
alert_major_bus_o	Yes	Yes	T62,T173,T87	Yes	T62,T173,T87	OUTPUT
core_sleep_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range