Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.09	96.47	89.29	86.51		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	88.31	96.47	89.29	87.59		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.31	96.47	89.29	87.59		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.49	96.43	81.43	90.70		96.77	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.38			96.38
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	93.21	96.39	79.83			96.64	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T62,T173,T87
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T274,T275,T276
1	0	Covered	T54,T168,T63

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T168,T63

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T30,T31

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T155
1	0	Covered	T4,T5,T6
1	1	Covered	T81,T82,T1

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T30,T31,T155

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T30,T31

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T54,T168,T63
0	1	0	Covered	T62,T173,T87
1	0	0	Covered	T277,T278,T279

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	91	75.21
Total Bits	1624	1405	86.51
Total Bits 0->1	812	703	86.58
Total Bits 1->0	812	702	86.45

Ports	121	91	75.21
Port Bits	1624	1405	86.51
Port Bits 0->1	812	703	86.58
Port Bits 1->0	812	702	86.45

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T280,T281,T282	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T18,*T63,*T173	Yes	T18,T63,T173	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T18,T63,T175	Yes	T18,T63,T175	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T18,*T63,*T173	Yes	T18,T63,T173	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T21,T22,T1	Yes	T21,T22,T1	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T22,T1,T25	Yes	T22,T1,T25	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T22,T1,T25	Yes	T22,T1,T25	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T22,T1,T23	Yes	T22,T1,T23	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	T4,*T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T134,T263,T270	Yes	T134,T263,T270	INPUT
irq_timer_i	Yes	Yes	T283,T78,T284	Yes	T283,T78,T284	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	OUTPUT
nmi_wdog_i	Yes	Yes	T5,T81,T154	Yes	T5,T81,T154	INPUT
debug_req_i	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T6,T67	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T1	Yes	T1	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T136,T128,T137	Yes	T136,T139,T128	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T18,T89,T90	Yes	T18,T89,T90	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T6,T68,T18	Yes	T6,T67,T68	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T67	Yes	T4,T5,T18	INPUT
icache_otp_key_i.ack	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T81,T82,T1	Yes	T81,T82,T1	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T62,T274,T43	Yes	T62,T274,T43	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T43,T47,T44	Yes	T43,T47,T44	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T43,T47,T44	Yes	T43,T47,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T81,T82,T1	Yes	T81,T82,T1	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T62,T274,T43	Yes	T62,T274,T43	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T54,T168,T63
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T274,T275,T276
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	395372364	8	0	0
FpvSecCmIbexFetchEnable1_A	395372364	19581335	0	66
FpvSecCmIbexFetchEnable2_A	395372364	55785530	0	76
FpvSecCmIbexFetchEnable3Rev_A	395372364	335270706	0	1834
FpvSecCmIbexFetchEnable3_A	395372364	335272396	0	1755
FpvSecCmIbexInstrIntgErrCheck_A	395372364	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	395372364	588	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	395372364	0	0	0
FpvSecCmIbexPcMismatchCheck_A	395372364	0	0	0
FpvSecCmIbexRfEccErrCheck_A	395372364	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	395372364	0	0	0
FpvSecCmRegWeOnehotCheck_A	395372364	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	395372364	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	395372364	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	395372364	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	923	923	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	923	923	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	395372364	179	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	395372364	193	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	8	0	0
T59	495631	0	0	0
T82	704475	0	0	0
T123	107388	0	0	0
T138	574701	0	0	0
T193	75921	0	0	0
T213	357940	0	0	0
T257	152732	0	0	0
T274	203056	1	0	0
T275	0	1	0	0
T276	0	1	0	0
T285	0	1	0	0
T286	0	1	0	0
T287	0	1	0	0
T288	0	1	0	0
T289	0	1	0	0
T290	291148	0	0	0
T291	124608	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	19581335	0	66
T1	0	0	0	2
T4	261933	41108	0	0
T5	167368	9931	0	0
T6	234648	41124	0	0
T18	302611	39684	0	0
T19	97772	9919	0	0
T21	0	0	0	2
T22	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T62	231580	19850	0	0
T63	0	0	0	2
T67	166514	9931	0	0
T68	72021	9919	0	0
T69	916519	109209	0	0
T70	0	0	0	2
T72	157469	19858	0	0
T122	0	0	0	2
T241	0	0	0	2
T292	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	55785530	0	76
T1	0	0	0	2
T4	261933	69555	0	0
T5	167368	34775	0	0
T6	234648	69555	0	0
T18	302611	139096	0	0
T19	97772	34775	0	0
T21	0	0	0	2
T22	0	0	0	2
T33	0	0	0	2
T56	0	0	0	2
T62	231580	69555	0	0
T63	0	0	0	2
T67	166514	38803	0	0
T68	72021	34775	0	0
T69	916519	382554	0	0
T72	157469	69555	0	0
T92	0	0	0	2
T93	0	0	0	2
T122	0	0	0	2
T241	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	335270706	0	1834
T4	261933	171002	0	2
T5	167368	132528	0	2
T6	234648	143706	0	2
T18	302611	163285	0	2
T19	97772	62943	0	2
T62	231580	161906	0	2
T67	166514	127648	0	2
T68	72021	37188	0	2
T69	916519	533312	0	2
T72	157469	87796	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	335272396	0	1755
T4	261933	171004	0	2
T5	167368	132529	0	2
T6	234648	143708	0	2
T18	302611	163288	0	2
T19	97772	62944	0	2
T62	231580	161908	0	2
T67	166514	127651	0	2
T68	72021	37189	0	2
T69	916519	533322	0	2
T72	157469	87798	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	76	0	0
T293	274154	76	0	0
T294	241224	0	0	0
T295	203847	0	0	0
T296	61854	0	0	0
T297	164132	0	0	0
T298	62216	0	0	0
T299	216653	0	0	0
T300	269744	0	0	0
T301	680699	0	0	0
T302	300246	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	588	0	0
T21	111382	0	0	0
T48	266854	0	0	0
T61	100361	0	0	0
T62	231580	32	0	0
T87	0	32	0	0
T88	0	32	0	0
T131	0	31	0	0
T173	0	1	0	0
T215	140471	0	0	0
T217	161847	0	0	0
T241	153904	0	0	0
T265	72568	0	0	0
T273	131281	0	0	0
T303	0	32	0	0
T304	0	1	0	0
T305	0	99	0	0
T306	0	1	0	0
T307	0	1	0	0
T308	157557	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	6	0	0
T46	518083	0	0	0
T73	343207	0	0	0
T84	135486	0	0	0
T277	234443	1	0	0
T278	0	1	0	0
T279	0	1	0	0
T309	0	1	0	0
T310	0	1	0	0
T311	0	1	0	0
T312	888909	0	0	0
T313	254522	0	0	0
T314	80590	0	0	0
T315	110063	0	0	0
T316	274449	0	0	0
T317	219548	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	179	0	0
T26	123997	0	0	0
T58	373244	0	0	0
T81	709030	0	0	0
T89	86624	20	0	0
T90	86887	33	0	0
T91	0	33	0	0
T136	180113	0	0	0
T139	347776	0	0	0
T214	221784	0	0	0
T223	42205	0	0	0
T242	265468	0	0	0
T318	0	35	0	0
T319	0	12	0	0
T320	0	46	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	193	0	0
T18	302611	16	0	0
T19	97772	0	0	0
T21	111382	0	0	0
T48	266854	0	0	0
T61	100361	0	0	0
T62	231580	0	0	0
T69	916519	0	0	0
T72	157469	0	0	0
T73	0	16	0	0
T89	0	5	0	0
T90	0	42	0	0
T91	0	42	0	0
T201	0	16	0	0
T217	161847	0	0	0
T265	72568	0	0	0
T318	0	42	0	0
T319	0	3	0	0
T320	0	11	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T62,T173,T87
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T274,T275,T276
1	0	Covered	T54,T168,T63

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T54,T168,T63

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T30,T31

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T31,T155
1	0	Covered	T4,T5,T6
1	1	Covered	T81,T82,T1

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T30,T31,T155

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T81,T82,T30
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T30,T31

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T54,T168,T63
0	1	0	Covered	T62,T173,T87
1	0	0	Covered	T277,T278,T279

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	91	77.78
Total Bits	1604	1405	87.59
Total Bits 0->1	802	703	87.66
Total Bits 1->0	802	702	87.53

Ports	117	91	77.78
Port Bits	1604	1405	87.59
Port Bits 0->1	802	703	87.66
Port Bits 1->0	802	702	87.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T280,T281,T282	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	T18,*T63,*T173	Yes	T18,T63,T173	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T18,T63,T175	Yes	T18,T63,T175	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T18,*T63,*T173	Yes	T18,T63,T173	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T21,T22,T1	Yes	T21,T22,T1	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T22,T1,T25	Yes	T22,T1,T25	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T22,T1,T25	Yes	T22,T1,T25	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T22,T1,T23	Yes	T22,T1,T23	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	T4,*T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T134,T263,T270	Yes	T134,T263,T270	INPUT
irq_timer_i	Yes	Yes	T283,T78,T284	Yes	T283,T78,T284	INPUT
irq_external_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T6,T67	Yes	T4,T6,T67	OUTPUT
nmi_wdog_i	Yes	Yes	T5,T81,T154	Yes	T5,T81,T154	INPUT
debug_req_i	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T6,T67	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T1	Yes	T1	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T136,T128,T137	Yes	T136,T139,T128	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T18,T89,T90	Yes	T18,T89,T90	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T6,T68,T18	Yes	T6,T67,T68	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T67	Yes	T4,T5,T18	INPUT
icache_otp_key_i.ack	Yes	Yes	T89,T90,T91	Yes	T89,T90,T91	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T81,T82,T1	Yes	T81,T82,T1	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T62,T274,T43	Yes	T62,T274,T43	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T43,T47,T44	Yes	T43,T47,T44	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T43,T47,T44	Yes	T43,T47,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T81,T82,T1	Yes	T81,T82,T1	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T62,T274,T43	Yes	T62,T274,T43	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T1,T43,T30	Yes	T1,T43,T30	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T54,T168,T63
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T274,T275,T276
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	395372364	8	0	0
FpvSecCmIbexFetchEnable1_A	395372364	19581335	0	66
FpvSecCmIbexFetchEnable2_A	395372364	55785530	0	76
FpvSecCmIbexFetchEnable3Rev_A	395372364	335270706	0	1834
FpvSecCmIbexFetchEnable3_A	395372364	335272396	0	1755
FpvSecCmIbexInstrIntgErrCheck_A	395372364	76	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	395372364	588	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	395372364	0	0	0
FpvSecCmIbexPcMismatchCheck_A	395372364	0	0	0
FpvSecCmIbexRfEccErrCheck_A	395372364	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	395372364	0	0	0
FpvSecCmRegWeOnehotCheck_A	395372364	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	395372364	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	395372364	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	395372364	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	923	923	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	923	923	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	923	923	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	395372364	179	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	395372364	193	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	8	0	0
T59	495631	0	0	0
T82	704475	0	0	0
T123	107388	0	0	0
T138	574701	0	0	0
T193	75921	0	0	0
T213	357940	0	0	0
T257	152732	0	0	0
T274	203056	1	0	0
T275	0	1	0	0
T276	0	1	0	0
T285	0	1	0	0
T286	0	1	0	0
T287	0	1	0	0
T288	0	1	0	0
T289	0	1	0	0
T290	291148	0	0	0
T291	124608	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	19581335	0	66
T1	0	0	0	2
T4	261933	41108	0	0
T5	167368	9931	0	0
T6	234648	41124	0	0
T18	302611	39684	0	0
T19	97772	9919	0	0
T21	0	0	0	2
T22	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T62	231580	19850	0	0
T63	0	0	0	2
T67	166514	9931	0	0
T68	72021	9919	0	0
T69	916519	109209	0	0
T70	0	0	0	2
T72	157469	19858	0	0
T122	0	0	0	2
T241	0	0	0	2
T292	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	55785530	0	76
T1	0	0	0	2
T4	261933	69555	0	0
T5	167368	34775	0	0
T6	234648	69555	0	0
T18	302611	139096	0	0
T19	97772	34775	0	0
T21	0	0	0	2
T22	0	0	0	2
T33	0	0	0	2
T56	0	0	0	2
T62	231580	69555	0	0
T63	0	0	0	2
T67	166514	38803	0	0
T68	72021	34775	0	0
T69	916519	382554	0	0
T72	157469	69555	0	0
T92	0	0	0	2
T93	0	0	0	2
T122	0	0	0	2
T241	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	335270706	0	1834
T4	261933	171002	0	2
T5	167368	132528	0	2
T6	234648	143706	0	2
T18	302611	163285	0	2
T19	97772	62943	0	2
T62	231580	161906	0	2
T67	166514	127648	0	2
T68	72021	37188	0	2
T69	916519	533312	0	2
T72	157469	87796	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	335272396	0	1755
T4	261933	171004	0	2
T5	167368	132529	0	2
T6	234648	143708	0	2
T18	302611	163288	0	2
T19	97772	62944	0	2
T62	231580	161908	0	2
T67	166514	127651	0	2
T68	72021	37189	0	2
T69	916519	533322	0	2
T72	157469	87798	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	76	0	0
T293	274154	76	0	0
T294	241224	0	0	0
T295	203847	0	0	0
T296	61854	0	0	0
T297	164132	0	0	0
T298	62216	0	0	0
T299	216653	0	0	0
T300	269744	0	0	0
T301	680699	0	0	0
T302	300246	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	588	0	0
T21	111382	0	0	0
T48	266854	0	0	0
T61	100361	0	0	0
T62	231580	32	0	0
T87	0	32	0	0
T88	0	32	0	0
T131	0	31	0	0
T173	0	1	0	0
T215	140471	0	0	0
T217	161847	0	0	0
T241	153904	0	0	0
T265	72568	0	0	0
T273	131281	0	0	0
T303	0	32	0	0
T304	0	1	0	0
T305	0	99	0	0
T306	0	1	0	0
T307	0	1	0	0
T308	157557	0	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	6	0	0
T46	518083	0	0	0
T73	343207	0	0	0
T84	135486	0	0	0
T277	234443	1	0	0
T278	0	1	0	0
T279	0	1	0	0
T309	0	1	0	0
T310	0	1	0	0
T311	0	1	0	0
T312	888909	0	0	0
T313	254522	0	0	0
T314	80590	0	0	0
T315	110063	0	0	0
T316	274449	0	0	0
T317	219548	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923	923	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T62	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T72	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	179	0	0
T26	123997	0	0	0
T58	373244	0	0	0
T81	709030	0	0	0
T89	86624	20	0	0
T90	86887	33	0	0
T91	0	33	0	0
T136	180113	0	0	0
T139	347776	0	0	0
T214	221784	0	0	0
T223	42205	0	0	0
T242	265468	0	0	0
T318	0	35	0	0
T319	0	12	0	0
T320	0	46	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395372364	193	0	0
T18	302611	16	0	0
T19	97772	0	0	0
T21	111382	0	0	0
T48	266854	0	0	0
T61	100361	0	0	0
T62	231580	0	0	0
T69	916519	0	0	0
T72	157469	0	0	0
T73	0	16	0	0
T89	0	5	0	0
T90	0	42	0	0
T91	0	42	0	0
T201	0	16	0	0
T217	161847	0	0	0
T265	72568	0	0	0
T318	0	42	0	0
T319	0	3	0	0
T320	0	11	0	0