Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.24			83.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host1	67.28			67.28
tb.dut.top_earlgrey.u_spi_host0	83.52			83.52

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.28			67.28

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.28			67.28

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	32	69.57
Total Bits	358	298	83.24
Total Bits 0->1	179	149	83.24
Total Bits 1->0	179	149	83.24

Ports	46	32	69.57
Port Bits	358	298	83.24
Port Bits 0->1	179	149	83.24
Port Bits 1->0	179	149	83.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T30,*T181,*T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T81,*T95,*T96	Yes	T81,T95,T96	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T96,*T97,*T180	Yes	T96,T97,T180	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i.a_valid	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_o.a_ready	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,*T82,T96	Yes	T81,T95,T82	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T81,*T95,*T96	Yes	T81,T95,T96	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T82,T96	Yes	T81,T95,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T215,T81	Yes	T48,T215,T81	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T49,T216	Yes	T43,T49,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T49,T44	Yes	T43,T49,T216	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T215,T81	Yes	T48,T215,T81	OUTPUT
cio_sck_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sck_en_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_csb_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_csb_en_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.passthrough_en	Yes	Yes	T96,T97,T180	Yes	T95,T96,T97	INPUT
passthrough_o.s[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	OUTPUT
intr_error_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_spi_event_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	21	55.26
Total Bits	324	218	67.28
Total Bits 0->1	162	109	67.28
Total Bits 1->0	162	109	67.28

Ports	38	21	55.26
Port Bits	324	218	67.28
Port Bits 0->1	162	109	67.28
Port Bits 1->0	162	109	67.28

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T31,T78	Yes	T30,T31,T78	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T30,*T181,*T182	Yes	T30,T181,T182	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T31,T78	Yes	T30,T31,T78	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[4:2]	Yes	Yes	*T30,*T181,*T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[5]	No	No		No		INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T30,*T181,*T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T30,*T181,*T182	Yes	T30,T181,T182	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T181,*T182,*T183	Yes	T181,T182,T183	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	INPUT
tl_i.a_valid	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	INPUT
tl_o.a_ready	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T184	Yes	T78,T79,T184	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T181,T182,T183	Yes	T30,T181,T182	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T181,T182,T183	Yes	T30,T181,T182	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[6:0]	Yes	Yes	*T78,*T79,T184	Yes	T78,T79,T184	OUTPUT
tl_o.d_data[17:7]	No	No		No		OUTPUT
tl_o.d_data[18]	Yes	Yes	*T184,*T185,*T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_data[19]	No	No		No		OUTPUT
tl_o.d_data[20]	Yes	Yes	*T184,*T185,*T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_data[21]	No	No		No		OUTPUT
tl_o.d_data[22]	Yes	Yes	*T184,*T185,*T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_data[23]	No	No		No		OUTPUT
tl_o.d_data[26:24]	Yes	Yes	T184,T185,T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_data[27]	No	No		No		OUTPUT
tl_o.d_data[28]	Yes	Yes	*T184,*T185,*T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_data[30:29]	No	No		No		OUTPUT
tl_o.d_data[31]	Yes	Yes	T184,T185,T186	Yes	T184,T185,T186	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T181,*T182,*T183	Yes	T181,T182,T183	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T181,T182,T183	Yes	T30,T181,T182	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T181,*T182,*T183	Yes	T181,T182,T183	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T30,T181,T182	Yes	T30,T181,T182	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T48,T215,T43	Yes	T48,T215,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T49,T44	Yes	T43,T49,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T49,T44	Yes	T43,T49,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T48,T215,T43	Yes	T48,T215,T43	OUTPUT
cio_sck_o	No	No		No		OUTPUT
cio_sck_en_o	No	No		No		OUTPUT
cio_csb_o	No	No		No		OUTPUT
cio_csb_en_o	No	No		No		OUTPUT
cio_sd_o[3:0]	No	No		No		OUTPUT
cio_sd_en_o[3:0]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T23,T24,T25	Yes	T113,T114,T115	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_spi_event_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	31	70.45
Total Bits	352	294	83.52
Total Bits 0->1	176	147	83.52
Total Bits 1->0	176	147	83.52

Ports	44	31	70.45
Port Bits	352	294	83.52
Port Bits 0->1	176	147	83.52
Port Bits 1->0	176	147	83.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T81,*T95,*T82	Yes	T81,T95,T82	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T81,*T95,*T96	Yes	T81,T95,T96	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T96,*T97,*T180	Yes	T96,T97,T180	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	INPUT
tl_i.a_valid	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	INPUT
tl_o.a_ready	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,*T82,T96	Yes	T81,T95,T82	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T81,*T95,*T96	Yes	T81,T95,T96	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T82,T96	Yes	T81,T95,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T95,T82	Yes	T81,T95,T82	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T49,T216	Yes	T43,T49,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T49,T44	Yes	T43,T49,T216	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_sck_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sck_en_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_csb_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_csb_en_o	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T95,*T96,*T97	Yes	T95,T96,T97	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T95,T124,T96	Yes	T95,T124,T96	INPUT
passthrough_i.passthrough_en	Yes	Yes	T96,T97,T180	Yes	T95,T96,T97	INPUT
passthrough_o.s[3:0]	Yes	Yes	T95,T96,T97	Yes	T95,T96,T93	OUTPUT
intr_error_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
intr_spi_event_o	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT

*Tests covering at least one bit in the range