Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_49

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_50

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_51

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_52

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_53

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_54

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_55

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_56

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_57

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_58

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_59

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_60

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_61

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_62

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_63

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_64

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_65

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_66

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_67

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_68

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_69

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_70

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_71

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_72

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_73

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_74

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_75

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_76

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_77

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_78

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_79

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_80

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.88	90.18	60.26			97.06	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_49

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_49

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_49

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_50

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_50

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_50

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_51

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_51

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_51

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_52

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_52

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_52

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_53

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_53

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_53

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_54

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_54

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_54

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_55

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_55

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_55

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_56

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_56

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_56

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_57

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_57

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_57

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_58

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_58

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_58

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_59

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_59

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_59

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_60

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_60

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_60

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_61

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_61

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_61

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_62

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_62

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_62

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_63

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_63

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_1_p_63

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_64

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_64

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_64

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_65

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_65

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_65

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_66

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_66

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_66

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_67

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_67

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_67

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_68

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_68

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_68

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_69

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_69

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_69

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_70

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_70

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_70

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_71

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_71

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_71

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_72

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_72

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_72

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_73

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_73

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_73

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_74

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_74

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_74

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_75

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_75

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_75

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_76

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_76

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_76

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_77

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_77

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_77

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_78

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_78

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_78

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_79

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_79

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_79

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_80

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

Line No.	Covered	Statements
56	1	1
57	1	1
58	1	1
59	1	1
			==> MISSING_ELSE
64	1	1
65	0	1
72	1	1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_80

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_2_p_80

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67



	LineNo.	Expression
-1-:	64	(wr_en) ?

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Not Covered



	LineNo.	Expression
-1-:	56	if ((!rst_ni))
-2-:	58	if (wr_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Not Covered