Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : csrng
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.82 96.82

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_csrng 96.82 96.82



Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.82 96.82


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.82 96.82


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : csrng
TotalCoveredPercent
Totals 65 52 80.00
Total Bits 1790 1733 96.82
Total Bits 0->1 895 867 96.87
Total Bits 1->0 895 866 96.76

Ports 65 52 80.00
Port Bits 1790 1733 96.82
Port Bits 0->1 895 867 96.87
Port Bits 1->0 895 866 96.76

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[6] No No No INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T152,*T61,*T136 Yes T152,T61,T136 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T4,*T6,*T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T152,*T61,*T136 Yes T152,T61,T136 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
otp_en_csrng_sw_app_read_i[7:0] Yes Yes T4,T5,T6 Yes T4,T6,T69 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
entropy_src_hw_if_o.es_req Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
entropy_src_hw_if_i.es_fips Yes Yes T136,T27,T28 Yes T61,T136,T139 INPUT
entropy_src_hw_if_i.es_bits[383:0] Yes Yes T136,T128,T137 Yes T61,T136,T128 INPUT
entropy_src_hw_if_i.es_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cs_aes_halt_i.cs_aes_halt_req Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
cs_aes_halt_o.cs_aes_halt_ack Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
csrng_cmd_i[0].genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i[0].csrng_req_bus[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
csrng_cmd_i[0].csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i[1].genbits_ready Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
csrng_cmd_i[1].csrng_req_bus[31:0] Yes Yes T136,T128,T137 Yes T61,T136,T139 INPUT
csrng_cmd_i[1].csrng_req_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
csrng_cmd_o[0].genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o[0].genbits_fips Yes Yes T136,T399,T400 Yes T61,T136,T139 OUTPUT
csrng_cmd_o[0].genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o[0].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[0].csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o[0].csrng_req_ready Yes Yes T128,T197,T137 Yes T128,T197,T137 OUTPUT
csrng_cmd_o[1].genbits_bus[127:0] Yes Yes T136,T139,T128 Yes T61,T136,T128 OUTPUT
csrng_cmd_o[1].genbits_fips No No Yes T136,T399,T400 OUTPUT
csrng_cmd_o[1].genbits_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
csrng_cmd_o[1].csrng_rsp_sts[2:0] No No No OUTPUT
csrng_cmd_o[1].csrng_rsp_ack Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
csrng_cmd_o[1].csrng_req_ready Yes Yes T128,T137,T138 Yes T128,T137,T138 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T197,T43,T30 Yes T197,T43,T30 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T308,T43,T30 Yes T308,T43,T30 INPUT
alert_rx_i[1].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[1].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T197,T43,T30 Yes T197,T43,T30 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T308,T43,T30 Yes T308,T43,T30 OUTPUT
intr_cs_cmd_req_done_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT
intr_cs_entropy_req_o Yes Yes T352,T209,T210 Yes T352,T209,T210 OUTPUT
intr_cs_hw_inst_exc_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT
intr_cs_fatal_err_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%