Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.97 93.97

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 88.69 88.69
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.54 94.54


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.69 88.69


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.69 88.69


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.54 94.54


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.54 94.54


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 45 70.31
Total Bits 1160 1090 93.97
Total Bits 0->1 580 545 93.97
Total Bits 1->0 580 545 93.97

Ports 64 45 70.31
Port Bits 1160 1090 93.97
Port Bits 0->1 580 545 93.97
Port Bits 1->0 580 545 93.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T4,T6,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_o.a_ready Yes Yes T18,T62,T20 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T18,T62,T87 Yes T18,T62,T87 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T18,T62,*T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T18,*T62,*T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T18,*T62,*T87 Yes T18,T62,T87 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T18,T62,T20 Yes T18,T62,T20 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T30,T31 Yes T43,T30,T31 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T30,T31 Yes T43,T30,T31 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T4,T6,T48 Yes T4,T6,T48 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T4,T6,T18 INPUT
sram_otp_key_o.req Yes Yes T62,T20,T26 Yes T62,T20,T26 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T68,T18 Yes T6,T67,T68 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T67 Yes T4,T5,T18 INPUT
sram_otp_key_i.ack Yes Yes T62,T20,T26 Yes T62,T20,T26 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 39 65.00
Total Bits 1132 1004 88.69
Total Bits 0->1 566 502 88.69
Total Bits 1->0 566 502 88.69

Ports 60 39 65.00
Port Bits 1132 1004 88.69
Port Bits 0->1 566 502 88.69
Port Bits 1->0 566 502 88.69

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T4,T6,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T18,T62,T87 Yes T18,T62,T87 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[3:0] Yes Yes T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_data[31:4] No No No INPUT
regs_tl_i.a_mask[3:0] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[5] No No No INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[0] No No No INPUT
regs_tl_i.a_source[1] Yes Yes *T18,*T62,*T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T18,T62,T87 Yes T18,T62,T87 INPUT
regs_tl_i.a_valid Yes Yes T18,T62,T20 Yes T18,T62,T20 INPUT
regs_tl_o.a_ready Yes Yes T18,T62,T20 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T18,*T73,*T201 Yes T18,T73,T201 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes T18,T62,*T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T18,*T62,*T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T18,T62,T54 Yes T18,T62,T20 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T18,*T62,*T87 Yes T18,T62,T87 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T18,T62,T20 Yes T18,T62,T20 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T30,T31 Yes T43,T30,T31 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T30,T31 Yes T43,T30,T31 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T4,T6,T48 Yes T4,T6,T48 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T4,T5,T6 Yes T4,T6,T18 INPUT
sram_otp_key_o.req Yes Yes T62,T20,T26 Yes T62,T20,T26 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T68,T18 Yes T6,T67,T68 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T67 Yes T4,T5,T18 INPUT
sram_otp_key_i.ack Yes Yes T62,T20,T26 Yes T62,T20,T26 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 42 72.41
Total Bits 1098 1038 94.54
Total Bits 0->1 549 519 94.54
Total Bits 1->0 549 519 94.54

Ports 58 42 72.41
Port Bits 1098 1038 94.54
Port Bits 0->1 549 519 94.54
Port Bits 1->0 549 519 94.54

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
clk_otp_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_otp_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
ram_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T4,T6,T67 Yes T4,T6,T67 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ram_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_error Yes Yes T4,T5,T6 Yes T4,T6,T18 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T4,T6,T67 Yes T4,T6,T67 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T4,T6,T67 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T4,T6,T67 Yes T4,T6,T67 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T21,*T22,*T200 Yes T21,T22,T200 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T62,T20,T26 Yes T62,T20,T26 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T62,T20,T26 Yes T62,T20,T26 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
regs_tl_i.a_valid Yes Yes T62,T20,T26 Yes T62,T20,T26 INPUT
regs_tl_o.a_ready Yes Yes T62,T20,T26 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[5:0] Yes Yes *T62,*T87,*T88 Yes T62,T87,T88 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T62,T54,T63 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T54,*T63,*T122 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T62,T54,T63 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[0] No No No OUTPUT
regs_tl_o.d_source[1] Yes Yes *T62,*T54,*T63 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T54,T63,T122 Yes T62,T20,T26 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T62,*T87,*T88 Yes T62,T87,T88 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T62,T20,T26 Yes T62,T20,T26 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T30,T31 Yes T43,T30,T31 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T30,T31 Yes T43,T30,T31 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T4,T6,T48 Yes T4,T6,T48 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T62,T87,T88 Yes T62,T87,T88 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T6,T68,T18 Yes T6,T67,T68 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T5,T67 Yes T4,T5,T18 INPUT
sram_otp_key_i.ack Yes Yes T62,T87,T88 Yes T62,T87,T88 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
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