Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : aon_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.45 90.45

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_aon_timer_aon 90.45 90.45



Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.45 90.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.45 90.45


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : aon_timer
TotalCoveredPercent
Totals 38 30 78.95
Total Bits 314 284 90.45
Total Bits 0->1 157 142 90.45
Total Bits 1->0 157 142 90.45

Ports 38 30 78.95
Port Bits 314 284 90.45
Port Bits 0->1 157 142 90.45
Port Bits 1->0 157 142 90.45

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[5:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T23,T24,T25 Yes T23,T24,T25 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T21,*T22,*T1 Yes T21,T22,T1 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T4,T6,T69 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T152,*T4,*T5 Yes T152,T4,T5 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T4,T6,T69 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T30,T46 Yes T43,T30,T46 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T46,T47 Yes T43,T46,T47 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T46,T47 Yes T43,T46,T47 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T30,T46 Yes T43,T30,T46 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T4,T6,T48 Yes T4,T6,T48 INPUT
intr_wkup_timer_expired_o Yes Yes T5,T67,T69 Yes T5,T67,T69 OUTPUT
intr_wdog_timer_bark_o Yes Yes T5,T81,T154 Yes T5,T81,T154 OUTPUT
nmi_wdog_timer_bark_o Yes Yes T5,T81,T154 Yes T5,T81,T154 OUTPUT
wkup_req_o Yes Yes T67,T69,T217 Yes T5,T67,T69 OUTPUT
aon_timer_rst_req_o Yes Yes T81,T86,T168 Yes T81,T86,T168 OUTPUT
sleep_mode_i Yes Yes T4,T5,T6 Yes T67,T18,T69 INPUT

*Tests covering at least one bit in the range
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