Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.16			84.16

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_usbdev	84.16			84.16

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Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.16			84.16

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.16			84.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	75	60	80.00
Total Bits	404	340	84.16
Total Bits 0->1	202	170	84.16
Total Bits 1->0	202	170	84.16

Ports	75	60	80.00
Port Bits	404	340	84.16
Port Bits 0->1	202	170	84.16
Port Bits 1->0	202	170	84.16

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T2,*T30,*T187	Yes	T2,T30,T187	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T30,T188	Yes	T2,T30,T188	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[11:2]	Yes	Yes	*T30,*T187,*T188	Yes	T30,T187,T188	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T2,*T30,*T187	Yes	T2,T30,T187	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T30,*T187	Yes	T2,T30,T187	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[1:0]	Yes	Yes	*T152,*T189,*T2	Yes	T152,T189,T2	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T187,T188,T101	Yes	T187,T188,T101	INPUT
tl_i.a_valid	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	INPUT
tl_o.a_ready	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T187,T188,T181	Yes	T187,T188,T101	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T187,T188,*T101	Yes	T187,T188,T181	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T187,T181,T190	Yes	T2,T30,T187	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T30,T187	Yes	T187,T188,T181	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T187	Yes	T152,T189,T2	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T187,T181,T190	Yes	T2,T30,T187	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T30,*T187	Yes	T187,T188,T181	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T30,T187	Yes	T2,T30,T187	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T43,T30,T49	Yes	T43,T30,T49	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T49,T47	Yes	T43,T49,T47	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T49,T47	Yes	T43,T49,T47	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T43,T30,T49	Yes	T43,T30,T49	OUTPUT
cio_usb_dp_i	Yes	Yes	T101,T103,T151	Yes	T103,T151,T107	INPUT
cio_usb_dn_i	Yes	Yes	T103,T151,T107	Yes	T92,T93,T103	INPUT
usb_rx_d_i	Yes	Yes	T103,T151,T152	Yes	T103,T151,T152	INPUT
cio_usb_dp_o	Yes	Yes	T2,T101,T102	Yes	T102,T15,T103	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T103,T107,T108	Yes	T103,T107,T108	OUTPUT
cio_usb_dn_o	Yes	Yes	T103,T151,T152	Yes	T101,T218,T103	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T103,T107,T108	Yes	T103,T107,T108	OUTPUT
usb_tx_se0_o	Yes	Yes	T103,T107,T108	Yes	T103,T107,T108	OUTPUT
usb_tx_d_o	Yes	Yes	T2,T101,T102	Yes	T102,T15,T103	OUTPUT
cio_sense_i	Yes	Yes	T157,T23,T24	Yes	T101,T218,T103	INPUT
usb_dp_pullup_o	Yes	Yes	T102,T15,T103	Yes	T2,T102,T9	OUTPUT
usb_dn_pullup_o	Yes	Yes	T151,T157,T158	Yes	T151,T157,T158	OUTPUT
usb_rx_enable_o	Yes	Yes	T152,T157,T189	Yes	T103,T151,T152	OUTPUT
usb_tx_use_d_se0_o	No	No		No		OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T2,T102,T9	Yes	T2,T102,T9	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T2,T102,T9	Yes	T2,T102,T9	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T151	Yes	T151	INPUT
usb_aon_sense_lost_i	Yes	Yes	T2,T9,T15	Yes	T2,T102,T9	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T2,T9,T15	Yes	T2,T9,T15	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T2,T9,T15	Yes	T2,T102,T9	INPUT
usb_ref_val_o	Yes	Yes	T103,T107,T108	Yes	T103,T107,T108	OUTPUT
usb_ref_pulse_o	Yes	Yes	T103,T107,T108	Yes	T103,T107,T108	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_pkt_sent_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_powered_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_disconnected_o	Yes	Yes	T188,T219,T152	Yes	T188,T219,T152	OUTPUT
intr_host_lost_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_link_reset_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_link_suspend_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_link_resume_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_av_out_empty_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_full_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_av_overflow_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_link_in_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_link_out_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_frame_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range