Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.77	88.53		86.79			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T20,T26,T262	Yes	T20,T26,T262	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T20,T26,T262	Yes	T20,T26,T262	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	INPUT
tl_o.a_ready	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T262,T153,T54	Yes	T262,T153,T54	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T262,T153	Yes	T20,T26,T81	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,T54,T63	Yes	T20,T26,T81	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T262,T153	Yes	T20,T26,T81	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T20	Yes	T152,T189,T20	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T54,T63	Yes	T20,T26,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T262,*T153,*T54	Yes	T262,T153,T54	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T43,T46	Yes	T82,T43,T46	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T43,T46	Yes	T82,T43,T46	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_rx_i	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T262,T153,T54	Yes	T262,T153,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T262,T153,T123	Yes	T262,T153,T123	OUTPUT
intr_rx_watermark_o	Yes	Yes	T262,T153,T123	Yes	T262,T153,T123	OUTPUT
intr_tx_empty_o	Yes	Yes	T262,T153,T123	Yes	T262,T153,T123	OUTPUT
intr_rx_overflow_o	Yes	Yes	T262,T153,T123	Yes	T262,T153,T123	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_break_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_timeout_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T20,T26,T262	Yes	T20,T26,T262	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T20,T26,T262	Yes	T20,T26,T262	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	INPUT
tl_o.a_ready	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T262,T54,T63	Yes	T262,T54,T63	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T262,T54	Yes	T20,T26,T81	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,T54,T63	Yes	T20,T26,T81	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T262,T54	Yes	T20,T26,T81	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T20	Yes	T152,T189,T20	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T54,T63	Yes	T20,T26,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T262,*T54,*T63	Yes	T262,T54,T63	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T20,T26,T81	Yes	T20,T26,T81	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_rx_i	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T262,T54,T63	Yes	T262,T54,T63	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T262,T123,T188	Yes	T262,T123,T188	OUTPUT
intr_rx_watermark_o	Yes	Yes	T262,T123,T188	Yes	T262,T123,T188	OUTPUT
intr_tx_empty_o	Yes	Yes	T262,T123,T188	Yes	T262,T123,T188	OUTPUT
intr_rx_overflow_o	Yes	Yes	T262,T123,T188	Yes	T262,T123,T188	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_break_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_timeout_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T81,T82,T30	Yes	T81,T82,T30	INPUT
tl_o.a_ready	Yes	Yes	T81,T82,T30	Yes	T81,T82,T30	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T82,T264	Yes	T81,T82,T30	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,*T82,T152	Yes	T81,T82,T30	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T82,T264	Yes	T81,T82,T30	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T81	Yes	T152,T189,T81	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T82,T152	Yes	T81,T82,T30	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T264,*T132,*T188	Yes	T264,T132,T188	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T82,T30	Yes	T81,T82,T30	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T46,T44	Yes	T43,T46,T44	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_rx_i	Yes	Yes	T264,T132,T344	Yes	T264,T132,T92	INPUT
cio_tx_o	Yes	Yes	T264,T132,T344	Yes	T264,T132,T344	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	OUTPUT
intr_rx_watermark_o	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	OUTPUT
intr_tx_empty_o	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	OUTPUT
intr_rx_overflow_o	Yes	Yes	T264,T132,T188	Yes	T264,T132,T188	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_break_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_timeout_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T81,T153,T82	Yes	T81,T153,T82	INPUT
tl_o.a_ready	Yes	Yes	T81,T153,T82	Yes	T81,T153,T82	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T153,T82	Yes	T81,T153,T82	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,*T82,T152	Yes	T81,T153,T82	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T153,T82	Yes	T81,T153,T82	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T81	Yes	T152,T189,T81	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T82,T152	Yes	T81,T153,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T153,*T188,*T219	Yes	T153,T188,T219	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T153,T82	Yes	T81,T153,T82	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_rx_i	Yes	Yes	T153,T345,T346	Yes	T153,T345,T346	INPUT
cio_tx_o	Yes	Yes	T153,T345,T346	Yes	T153,T345,T346	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	OUTPUT
intr_rx_watermark_o	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	OUTPUT
intr_tx_empty_o	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	OUTPUT
intr_rx_overflow_o	Yes	Yes	T153,T188,T219	Yes	T153,T188,T219	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_break_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_timeout_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T21,*T22,*T1	Yes	T21,T22,T1	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T81,T82,T99	Yes	T81,T82,T99	INPUT
tl_o.a_ready	Yes	Yes	T81,T82,T99	Yes	T81,T82,T99	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T81,T82,T99	Yes	T81,T82,T99	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T81,*T82,T152	Yes	T81,T82,T99	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T81,T82,T99	Yes	T81,T82,T99	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T152,*T189,*T81	Yes	T152,T189,T81	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T81,T82,T152	Yes	T81,T82,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T99,*T100,*T321	Yes	T99,T100,T321	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T81,T82,T99	Yes	T81,T82,T99	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T43,T46	Yes	T82,T43,T46	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T43,T46	Yes	T82,T43,T46	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T82,T43	Yes	T81,T82,T43	OUTPUT
cio_rx_i	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	INPUT
cio_tx_o	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
intr_rx_watermark_o	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
intr_tx_empty_o	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
intr_rx_overflow_o	Yes	Yes	T99,T100,T321	Yes	T99,T100,T321	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_break_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_timeout_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T188,T219,T220	Yes	T188,T219,T220	OUTPUT

*Tests covering at least one bit in the range