Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.37 95.37

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.30 92.30
tb.dut.top_earlgrey.u_edn0 95.12 95.12


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.30 92.30


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.30 92.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.12 95.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.12 95.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.77 88.53 86.79 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 64 82.05
Total Bits 1210 1154 95.37
Total Bits 0->1 605 578 95.54
Total Bits 1->0 605 576 95.21

Ports 78 64 82.05
Port Bits 1210 1154 95.37
Port Bits 0->1 605 578 95.54
Port Bits 1->0 605 576 95.21

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T4,*T6,*T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T4,*T6,*T18 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T61,T136,T128 Yes T61,T136,T128 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T130,T224,T225 Yes T130,T224,T225 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T136,T128,T137 Yes T61,T136,T128 OUTPUT
edn_o[0].edn_fips Yes Yes T136,T128,T137 Yes T61,T136,T128 OUTPUT
edn_o[0].edn_ack Yes Yes T61,T136,T128 Yes T61,T136,T128 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T75,T76,T77 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T4,T6,T67 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_fips Yes Yes T128,T140 Yes T128,T75,T130 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T130,T224,T225 Yes T130,T224,T225 OUTPUT
edn_o[3].edn_fips No No Yes T130,T224,T225 OUTPUT
edn_o[3].edn_ack Yes Yes T130,T224,T225 Yes T130,T224,T225 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T18,T69,T136 Yes T67,T68,T18 OUTPUT
edn_o[4].edn_fips Yes Yes T395,T396 Yes T75,T397,T398 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T128,T137,T138 Yes T128,T137,T138 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T136,T128,T137 Yes T136,T128,T137 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_fips Yes Yes T136,T128,T137 Yes T136,T139,T128 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T136,T399,T400 Yes T61,T136,T139 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T128,T197,T137 Yes T128,T197,T137 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T197,T43,T30 Yes T197,T43,T30 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T47,T44 Yes T43,T47,T44 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T47,T44 Yes T43,T47,T44 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T81,T290,T43 Yes T81,T290,T43 INPUT
alert_rx_i[1].ping_n Yes Yes T81,T43,T47 Yes T81,T43,T47 INPUT
alert_rx_i[1].ping_p Yes Yes T81,T43,T47 Yes T81,T43,T47 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T197,T43,T30 Yes T197,T43,T30 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T81,T290,T43 Yes T81,T290,T43 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T352,T209,T210 Yes T352,T209,T210 OUTPUT
intr_edn_fatal_err_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 714 659 92.30
Total Bits 0->1 357 330 92.44
Total Bits 1->0 357 329 92.16

Ports 50 37 74.00
Port Bits 714 659 92.30
Port Bits 0->1 357 330 92.44
Port Bits 1->0 357 329 92.16

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_mask[3:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T61,T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_o.a_ready Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T27,*T28,*T29 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T27,T28,T29 Yes T61,T136,T139 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
edn_i[0].edn_req Yes Yes T136,T128,T137 Yes T136,T128,T137 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T136,T128,T137 Yes T136,T128,T137 OUTPUT
edn_o[0].edn_fips Yes Yes T136,T128,T137 Yes T136,T128,T137 OUTPUT
edn_o[0].edn_ack Yes Yes T136,T128,T137 Yes T136,T128,T137 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T136,T128,T137 Yes T61,T136,T139 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T136,T139,T128 Yes T61,T136,T128 INPUT
csrng_cmd_i.genbits_fips No No Yes T136,T399,T400 INPUT
csrng_cmd_i.genbits_valid Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T128,T137,T138 Yes T128,T137,T138 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T30,T31 Yes T43,T30,T31 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T47,T44 Yes T43,T47,T44 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T47,T44 Yes T43,T47,T44 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T81,T290,T43 Yes T81,T290,T43 INPUT
alert_rx_i[1].ping_n Yes Yes T81,T43,T47 Yes T81,T43,T47 INPUT
alert_rx_i[1].ping_p Yes Yes T81,T43,T47 Yes T81,T43,T47 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T30,T31 Yes T43,T30,T31 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T81,T290,T43 Yes T81,T290,T43 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T352,T209,T210 Yes T352,T209,T210 OUTPUT
intr_edn_fatal_err_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 62 79.49
Total Bits 1208 1149 95.12
Total Bits 0->1 604 576 95.36
Total Bits 1->0 604 573 94.87

Ports 78 62 79.49
Port Bits 1208 1149 95.12
Port Bits 0->1 604 576 95.36
Port Bits 1->0 604 573 94.87

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T6,T18 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[0] No No No INPUT
tl_i.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T61,T136,T139 Yes T61,T136,T139 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.data_intg[1] No No No OUTPUT
tl_o.d_user.data_intg[6:2] Yes Yes T61,T136,T139 Yes T61,T136,T139 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T4,*T6,*T18 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T4,*T6,*T18 Yes T4,T5,T6 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T61,*T136,*T139 Yes T61,T136,T139 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T61,T59,T60 Yes T61,T59,T60 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T130,T224,T225 Yes T130,T224,T225 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T59,T60,T222 Yes T61,T59,T60 OUTPUT
edn_o[0].edn_fips No No Yes T61,T221,T222 OUTPUT
edn_o[0].edn_ack Yes Yes T61,T59,T60 Yes T61,T59,T60 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T75,T76,T77 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T4,T6,T67 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_fips Yes Yes T128,T140 Yes T128,T75,T130 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T130,T224,T225 Yes T130,T224,T225 OUTPUT
edn_o[3].edn_fips No No Yes T130,T224,T225 OUTPUT
edn_o[3].edn_ack Yes Yes T130,T224,T225 Yes T130,T224,T225 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T18,T69,T136 Yes T67,T68,T18 OUTPUT
edn_o[4].edn_fips Yes Yes T395,T396 Yes T75,T397,T398 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T128,T137,T138 Yes T128,T137,T138 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T136,T128,T137 Yes T136,T128,T137 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_fips Yes Yes T136,T128,T137 Yes T136,T139,T128 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T6,T18 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T136,T399,T400 Yes T61,T136,T139 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T128,T197,T137 Yes T128,T197,T137 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T197,T43,T30 Yes T197,T43,T30 INPUT
alert_rx_i[0].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[0].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T43,T30,T401 Yes T43,T30,T401 INPUT
alert_rx_i[1].ping_n Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_rx_i[1].ping_p Yes Yes T43,T44,T45 Yes T43,T44,T45 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T197,T43,T30 Yes T197,T43,T30 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T43,T30,T401 Yes T43,T30,T401 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T352,T209,T210 Yes T352,T209,T210 OUTPUT
intr_edn_fatal_err_o Yes Yes T209,T210,T211 Yes T209,T210,T211 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%