Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13352 |
0 |
0 |
T1 |
1267 |
2 |
0 |
0 |
T2 |
31814 |
4 |
0 |
0 |
T3 |
134395 |
2 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
5 |
0 |
0 |
T14 |
0 |
5 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T50 |
780 |
0 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
596 |
0 |
0 |
0 |
T103 |
607 |
0 |
0 |
0 |
T104 |
1400 |
0 |
0 |
0 |
T105 |
421 |
0 |
0 |
0 |
T106 |
485 |
0 |
0 |
0 |
T107 |
861 |
0 |
0 |
0 |
T108 |
770 |
0 |
0 |
0 |
T109 |
599 |
0 |
0 |
0 |
T142 |
23590 |
0 |
0 |
0 |
T159 |
41281 |
0 |
0 |
0 |
T213 |
59438 |
0 |
0 |
0 |
T227 |
216816 |
0 |
0 |
0 |
T228 |
187294 |
0 |
0 |
0 |
T273 |
34100 |
0 |
0 |
0 |
T392 |
649018 |
85 |
0 |
0 |
T393 |
0 |
82 |
0 |
0 |
T394 |
0 |
448 |
0 |
0 |
T395 |
0 |
14 |
0 |
0 |
T396 |
0 |
7 |
0 |
0 |
T397 |
0 |
14 |
0 |
0 |
T415 |
0 |
36 |
0 |
0 |
T417 |
0 |
10 |
0 |
0 |
T422 |
0 |
2 |
0 |
0 |
T423 |
0 |
7 |
0 |
0 |
T424 |
0 |
4 |
0 |
0 |
T425 |
39025 |
0 |
0 |
0 |
T426 |
46929 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13361 |
0 |
0 |
T1 |
45289 |
2 |
0 |
0 |
T2 |
31814 |
5 |
0 |
0 |
T3 |
134395 |
2 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
4 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T13 |
0 |
6 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T16 |
0 |
2 |
0 |
0 |
T50 |
36724 |
0 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
53647 |
0 |
0 |
0 |
T103 |
46316 |
0 |
0 |
0 |
T104 |
120915 |
0 |
0 |
0 |
T105 |
26788 |
0 |
0 |
0 |
T106 |
29659 |
0 |
0 |
0 |
T107 |
56645 |
0 |
0 |
0 |
T108 |
69193 |
0 |
0 |
0 |
T109 |
34963 |
0 |
0 |
0 |
T142 |
23590 |
0 |
0 |
0 |
T159 |
41281 |
0 |
0 |
0 |
T213 |
59438 |
0 |
0 |
0 |
T227 |
216816 |
0 |
0 |
0 |
T228 |
187294 |
0 |
0 |
0 |
T273 |
34100 |
0 |
0 |
0 |
T392 |
5822 |
85 |
0 |
0 |
T393 |
0 |
82 |
0 |
0 |
T394 |
0 |
448 |
0 |
0 |
T395 |
0 |
14 |
0 |
0 |
T396 |
0 |
7 |
0 |
0 |
T397 |
0 |
14 |
0 |
0 |
T415 |
0 |
36 |
0 |
0 |
T417 |
0 |
10 |
0 |
0 |
T422 |
0 |
2 |
0 |
0 |
T423 |
0 |
7 |
0 |
0 |
T424 |
0 |
4 |
0 |
0 |
T425 |
39025 |
0 |
0 |
0 |
T426 |
46929 |
0 |
0 |
0 |