Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	50	50	100.00
Total Bits	334	334	100.00
Total Bits 0->1	167	167	100.00
Total Bits 1->0	167	167	100.00

Ports	50	50	100.00
Port Bits	334	334	100.00
Port Bits 0->1	167	167	100.00
Port Bits 1->0	167	167	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[7:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	INPUT
tl_o.a_ready	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T60,T1	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T177,T50,T186	Yes	T177,T60,T1	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T177,*T1,*T50	Yes	T177,T1,T50	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T80,T683	Yes	T60,T80,T683	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T158	Yes	T80,T82,T158	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T158	Yes	T80,T82,T158	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T80,T683	Yes	T60,T80,T683	OUTPUT
wkup_req_o	Yes	Yes	T177,T1,T223	Yes	T177,T1,T50	OUTPUT
rst_req_o	Yes	Yes	T177,T34,T665	Yes	T177,T34,T665	OUTPUT
intr_event_detected_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
cio_ac_present_i	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	INPUT
cio_ec_rst_l_i	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	INPUT
cio_key0_in_i	Yes	Yes	T177,T186,T34	Yes	T177,T186,T34	INPUT
cio_key1_in_i	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	INPUT
cio_key2_in_i	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	INPUT
cio_pwrb_in_i	Yes	Yes	T1,T186,T223	Yes	T1,T186,T223	INPUT
cio_lid_open_i	Yes	Yes	T50,T186,T34	Yes	T50,T186,T34	INPUT
cio_flash_wp_l_i	Yes	Yes	T34,T35,T36	Yes	T50,T186,T34	INPUT
cio_bat_disable_o	Yes	Yes	T177,T665,T372	Yes	T177,T665,T372	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T34,T35,T36	Yes	T50,T34,T35	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T34,T35,T36	Yes	T34,T35,T36	OUTPUT
cio_key0_out_o	Yes	Yes	T177,T186,T34	Yes	T177,T186,T34	OUTPUT
cio_key1_out_o	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	OUTPUT
cio_key2_out_o	Yes	Yes	T186,T34,T35	Yes	T186,T34,T35	OUTPUT
cio_pwrb_out_o	Yes	Yes	T1,T186,T223	Yes	T1,T186,T223	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T34,T35,T206	Yes	T50,T34,T35	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range