Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_o.a_ready	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T21,T118,T247	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T153,T76,T77	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T21,*T118,*T247	Yes	T21,T118,T247	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T63,T60,T80	Yes	T63,T60,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T244	Yes	T80,T82,T244	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T244	Yes	T80,T82,T244	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T63,T60,T80	Yes	T63,T60,T80	OUTPUT
cio_rx_i	Yes	Yes	T18,T46,T47	Yes	T4,T6,T18	INPUT
cio_tx_o	Yes	Yes	T21,T118,T211	Yes	T21,T118,T211	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T118,T247,T211	Yes	T118,T247,T211	OUTPUT
intr_rx_watermark_o	Yes	Yes	T118,T211,T217	Yes	T118,T211,T217	OUTPUT
intr_tx_empty_o	Yes	Yes	T118,T211,T217	Yes	T118,T211,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T118,T211,T217	Yes	T118,T211,T217	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_o.a_ready	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T21,T118,T247	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T76	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T21,*T118,*T247	Yes	T21,T118,T247	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T63,T60,T80	Yes	T63,T60,T80	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T63,T60,T80	Yes	T63,T60,T80	OUTPUT
cio_rx_i	Yes	Yes	T18,T46,T47	Yes	T4,T6,T18	INPUT
cio_tx_o	Yes	Yes	T21,T118,T32	Yes	T21,T118,T32	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T118,T247,T314	Yes	T118,T247,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T118,T314,T330	Yes	T118,T314,T330	OUTPUT
intr_tx_empty_o	Yes	Yes	T118,T314,T330	Yes	T118,T314,T330	OUTPUT
intr_rx_overflow_o	Yes	Yes	T118,T314,T330	Yes	T118,T314,T330	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_o.a_ready	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T248,T217	Yes	T60,T32,T248	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T248,T217	Yes	T60,T32,T248	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T32,*T217,*T330	Yes	T32,T217,T330	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T80,T99	Yes	T60,T80,T99	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T244	Yes	T80,T82,T244	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T244	Yes	T80,T82,T244	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T80,T99	Yes	T60,T80,T99	OUTPUT
cio_rx_i	Yes	Yes	T217,T218,T366	Yes	T217,T218,T24	INPUT
cio_tx_o	Yes	Yes	T217,T218,T37	Yes	T217,T218,T37	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T217,T330,T218	Yes	T217,T330,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T217,T330,T218	Yes	T217,T330,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T217,T330,T218	Yes	T217,T330,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T217,T330,T218	Yes	T217,T330,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	INPUT
tl_o.a_ready	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T211,T32,T248	Yes	T60,T211,T32	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T211,T32,T248	Yes	T60,T211,T32	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T76	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T211,*T32,*T212	Yes	T211,T32,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T80,T248	Yes	T60,T80,T248	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T80,T248	Yes	T60,T80,T248	OUTPUT
cio_rx_i	Yes	Yes	T211,T212,T344	Yes	T211,T212,T344	INPUT
cio_tx_o	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	OUTPUT
intr_rx_watermark_o	Yes	Yes	T211,T212,T330	Yes	T211,T212,T330	OUTPUT
intr_tx_empty_o	Yes	Yes	T211,T212,T330	Yes	T211,T212,T330	OUTPUT
intr_rx_overflow_o	Yes	Yes	T211,T212,T330	Yes	T211,T212,T330	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_i.a_valid	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	INPUT
tl_o.a_ready	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T32,T248	Yes	T60,T30,T32	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T32,T248	Yes	T60,T30,T32	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T153,T76,T77	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T32,*T31	Yes	T30,T32,T31	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T80,T248	Yes	T60,T80,T248	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T80,T82,T83	Yes	T80,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T80,T248	Yes	T60,T80,T248	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T332	Yes	T30,T31,T332	INPUT
cio_tx_o	Yes	Yes	T30,T31,T332	Yes	T30,T31,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T31,T330	Yes	T30,T31,T330	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T31,T330	Yes	T30,T31,T330	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T31,T330	Yes	T30,T31,T330	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T331,T345	Yes	T330,T331,T345	OUTPUT

*Tests covering at least one bit in the range