Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.60	90.68		90.10			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T18,T46,T47	Yes	T18,T46,T47	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_uart0_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T21,T118,T247	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T21,T118,T247	Yes	T5,T21,T58	INPUT
tl_uart0_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T32,*T37,*T76	Yes	T32,T37,T76	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T21,*T118,*T247	Yes	T21,T118,T247	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_uart1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T217,T330	Yes	T32,T217,T330	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T248,T217	Yes	T60,T32,T248	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T32,T248,T217	Yes	T60,T32,T248	INPUT
tl_uart1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T32,*T217,*T330	Yes	T32,T217,T330	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	INPUT
tl_uart2_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T211,T32,T212	Yes	T211,T32,T212	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T211,T32,T248	Yes	T60,T211,T32	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T211,T32,T248	Yes	T60,T211,T32	INPUT
tl_uart2_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T32,*T37,*T76	Yes	T32,T37,T76	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T211,*T32,*T212	Yes	T211,T32,T212	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T60,T211,T32	Yes	T60,T211,T32	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	INPUT
tl_uart3_i.d_error	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T30,T32,T31	Yes	T30,T32,T31	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T32,T248	Yes	T60,T30,T32	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T30,T32,T248	Yes	T60,T30,T32	INPUT
tl_uart3_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T153,T76,T77	Yes	T76,T77,T78	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T30,*T32,*T31	Yes	T30,T32,T31	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T60,T30,T32	Yes	T60,T30,T32	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T32,T215,T340	Yes	T32,T215,T340	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T32,T215,T340	Yes	T32,T215,T340	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_i2c0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T32,T215,T340	Yes	T32,T215,T340	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T248,T215	Yes	T60,T32,T248	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T32,T248,T215	Yes	T60,T32,T248	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T32,*T200,*T76	Yes	T32,T200,T76	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T32,*T215,*T340	Yes	T32,T215,T340	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T339,T405	Yes	T32,T339,T405	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T32,T339,T405	Yes	T32,T339,T405	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_i2c1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T339,T333	Yes	T32,T339,T333	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T248,T339	Yes	T60,T32,T248	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T32,T248,T339	Yes	T60,T32,T248	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T32,*T200,T76	Yes	T32,T200,T76	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T32,*T339,*T405	Yes	T32,T339,T405	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T60,T32,T248	Yes	T60,T32,T248	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T19,T32,T348	Yes	T19,T32,T348	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T19,T32,T348	Yes	T19,T32,T348	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T19,T60,T32	Yes	T19,T60,T32	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T19,T60,T32	Yes	T19,T60,T32	INPUT
tl_i2c2_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T19,T32,T348	Yes	T19,T32,T348	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T32,T248	Yes	T19,T60,T32	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T19,T32,T248	Yes	T19,T60,T32	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T32,*T200,*T76	Yes	T32,T200,T76	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T19,*T32,*T348	Yes	T19,T32,T348	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T19,T60,T32	Yes	T19,T60,T32	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T154,T219,T349	Yes	T154,T219,T349	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T154,T219,T349	Yes	T154,T219,T349	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T60,T154,T219	Yes	T60,T154,T219	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T60,T154,T219	Yes	T60,T154,T219	INPUT
tl_pattgen_i.d_error	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T154,T219,T349	Yes	T154,T219,T349	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T219,T349	Yes	T60,T154,T219	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T154,T219,T349	Yes	T60,T154,T219	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T153,T76,T77	Yes	T76,T77,T78	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T154,*T219,*T349	Yes	T154,T219,T349	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T60,T154,T219	Yes	T60,T154,T219	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T84,T110,T220	Yes	T84,T110,T220	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T84,T110,T220	Yes	T84,T110,T220	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T84,T60,T110	Yes	T84,T60,T110	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T84,T60,T110	Yes	T84,T60,T110	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T84,T110,T220	Yes	T84,T110,T220	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T110,T220	Yes	T84,T60,T110	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T84,T110,T220	Yes	T84,T60,T110	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	T76,*T77,*T79	Yes	T76,T77,T78	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T84,*T110,*T220	Yes	T84,T110,T220	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T84,T60,T110	Yes	T84,T60,T110	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T32,T40,T41	Yes	T32,T40,T41	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T40,T41	Yes	T84,T60,T110	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T32,T40,T41	Yes	T84,T60,T110	INPUT
tl_gpio_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T32,*T200,*T76	Yes	T32,T200,T76	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T18,*T84,*T46	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T67,T154,T53	Yes	T67,T154,T53	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T67,T154,T53	Yes	T67,T154,T53	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T60,T67,T154	Yes	T60,T67,T154	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T60,T67,T154	Yes	T60,T67,T154	INPUT
tl_spi_device_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T67,T154,T53	Yes	T67,T154,T53	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T154,T53	Yes	T67,T154,T53	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T60,T67,T154	Yes	T67,T154,T53	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T153,T76,T77	Yes	T76,T77,T79	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T79	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T60,*T67,*T154	Yes	T67,T154,T53	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T60,T67,T154	Yes	T60,T67,T154	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T20,T84,T110	Yes	T20,T84,T110	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T20,T84,T110	Yes	T20,T84,T110	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T20,T84,T60	Yes	T20,T84,T60	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T20,T84,T60	Yes	T20,T84,T60	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T153,T76,T77	Yes	T76,T77,T79	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T20,T154,T255	Yes	T20,T154,T255	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T84,T110	Yes	T20,T84,T60	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T20,T84,T110	Yes	T20,T84,T60	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T20,*T84,*T110	Yes	T20,T84,T110	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T20,T84,T60	Yes	T20,T84,T60	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T84,T63	Yes	T5,T84,T63	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T84,T63	Yes	T5,T84,T63	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T5,T84,T63	Yes	T5,T84,T63	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T5,T84,T63	Yes	T5,T84,T63	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T63,T172,T176	Yes	T63,T172,T176	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T63,T21	Yes	T5,T63,T115	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T63,T21	Yes	T5,T63,T115	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T153,T76,T77	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T63,*T21	Yes	T5,T84,T63	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T5,T84,T63	Yes	T5,T84,T63	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T46	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T18,T46	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T172,T116	Yes	T6,T172,T116	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T115,T172	Yes	T6,T115,T172	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T116,T118	Yes	T6,T116,T118	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T18,T46	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T18,T46	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T153,T76,T77	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T37,*T153,*T76	Yes	T37,T76,T77	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T172,*T116	Yes	T6,T172,T116	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T79	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T67,*T150,*T151	Yes	T67,T150,T151	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T84,*T115,*T59	Yes	T115,T59,T152	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T6,T18	Yes	T18,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T18,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T153,T76,T77	Yes	T76,T77,T79	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T18,T46,T47	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T23,T59	Yes	T22,T23,T59	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T257,*T258,*T259	Yes	T257,T258,T259	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T21,*T22,*T23	Yes	T5,T21,T22	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T21,T22	Yes	T5,T21,T22	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T121,T95,T1	Yes	T121,T95,T1	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T95,T1	Yes	T60,T121,T95	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T18,*T46,*T47	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T37,*T76,*T77	Yes	T37,T76,T77	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T79	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T18,*T84,*T46	Yes	T5,T18,T84	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T18,T84	Yes	T5,T18,T84	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T178,T117,T107	Yes	T178,T117,T107	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T21,T178,T117	Yes	T5,T21,T58	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T21,T178,T117	Yes	T5,T21,T58	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T79	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T178,*T117,*T107	Yes	T178,T117,T107	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T5,T21,T58	Yes	T5,T21,T58	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T18,T46	Yes	T5,T18,T46	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T18,T46,T47	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T46	Yes	T5,T18,T46	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T46	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T5,T18,T46	Yes	T5,T18,T46	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T79	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T68,*T210,*T201	Yes	T68,T210,T201	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T20,T84	Yes	T18,T20,T84	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T37,*T76,*T77	Yes	T37,T76,T77	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T153,T76,T77	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T20	Yes	T5,T18,T20	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T18,T20	Yes	T5,T18,T20	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T1,T50	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T177,T1,T50	Yes	T177,T60,T1	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T177,T50,T186	Yes	T177,T60,T1	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T32,*T37,*T153	Yes	T32,T37,T76	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T153,T76,T77	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T177,*T1,*T50	Yes	T177,T1,T50	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T177,T60,T1	Yes	T177,T60,T1	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T110,T1,T111	Yes	T110,T1,T111	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T110,T1,T111	Yes	T110,T1,T111	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T60,T110,T1	Yes	T60,T110,T1	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T60,T110,T1	Yes	T60,T110,T1	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T111,T3	Yes	T1,T111,T3	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T1,T111	Yes	T60,T110,T1	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T110,T1,T111	Yes	T60,T110,T1	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T37,*T76,*T77	Yes	T37,T76,T77	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T110,*T1,*T111	Yes	T110,T1,T111	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T60,T110,T1	Yes	T60,T110,T1	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T67,*T32,*T68	Yes	T67,T32,T68	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T32,T68,T37	Yes	T32,T68,T37	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T18,T46,T47	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T76,T77,T79	Yes	T76,T77,T78	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range