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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.84 95.42 93.64 95.49 94.45 96.47 99.58


Total test records in report: 2875
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T299 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3721325182 Jun 02 03:59:26 PM PDT 24 Jun 02 04:09:39 PM PDT 24 6189240568 ps
T300 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3569869200 Jun 02 03:45:50 PM PDT 24 Jun 02 03:53:28 PM PDT 24 5002500036 ps
T168 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.686849979 Jun 02 03:41:29 PM PDT 24 Jun 02 03:43:37 PM PDT 24 3693653854 ps
T301 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3257273331 Jun 02 04:07:52 PM PDT 24 Jun 02 05:06:58 PM PDT 24 14584983420 ps
T302 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.468253391 Jun 02 03:46:06 PM PDT 24 Jun 02 04:08:16 PM PDT 24 8386986128 ps
T166 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.565708262 Jun 02 03:57:19 PM PDT 24 Jun 02 03:59:08 PM PDT 24 2589292719 ps
T37 /workspace/coverage/default/2.chip_jtag_csr_rw.2426479902 Jun 02 03:54:02 PM PDT 24 Jun 02 04:21:34 PM PDT 24 12189564585 ps
T914 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2937818792 Jun 02 03:47:32 PM PDT 24 Jun 02 03:54:24 PM PDT 24 4390064170 ps
T160 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3600988114 Jun 02 03:57:08 PM PDT 24 Jun 02 03:58:55 PM PDT 24 2114590326 ps
T235 /workspace/coverage/default/0.chip_sw_flash_init.2459238064 Jun 02 03:40:52 PM PDT 24 Jun 02 04:15:40 PM PDT 24 16056731550 ps
T82 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2260370493 Jun 02 03:58:59 PM PDT 24 Jun 02 04:23:20 PM PDT 24 11148962780 ps
T181 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3694693090 Jun 02 04:01:39 PM PDT 24 Jun 02 04:05:48 PM PDT 24 2934970600 ps
T409 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2274441607 Jun 02 03:57:09 PM PDT 24 Jun 02 04:19:49 PM PDT 24 8793092056 ps
T274 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.559285831 Jun 02 03:46:51 PM PDT 24 Jun 02 05:10:46 PM PDT 24 17450266938 ps
T410 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683432300 Jun 02 04:05:58 PM PDT 24 Jun 02 04:12:34 PM PDT 24 3637444872 ps
T73 /workspace/coverage/default/0.chip_sw_usbdev_pullup.588341485 Jun 02 03:42:05 PM PDT 24 Jun 02 03:49:17 PM PDT 24 3361528208 ps
T370 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3498310208 Jun 02 04:07:55 PM PDT 24 Jun 02 04:18:58 PM PDT 24 5988861780 ps
T339 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4038755829 Jun 02 03:42:25 PM PDT 24 Jun 02 03:53:01 PM PDT 24 4696079272 ps
T15 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1861744926 Jun 02 03:46:52 PM PDT 24 Jun 02 03:57:07 PM PDT 24 5985716040 ps
T361 /workspace/coverage/default/1.chip_sival_flash_info_access.4205539315 Jun 02 03:47:52 PM PDT 24 Jun 02 03:53:15 PM PDT 24 3134144592 ps
T28 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2502262125 Jun 02 03:43:31 PM PDT 24 Jun 02 03:55:44 PM PDT 24 7799335174 ps
T148 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3378609930 Jun 02 03:47:24 PM PDT 24 Jun 02 04:54:21 PM PDT 24 24925715147 ps
T365 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1839680599 Jun 02 03:51:58 PM PDT 24 Jun 02 03:55:58 PM PDT 24 2352440924 ps
T363 /workspace/coverage/default/0.chip_sw_hmac_enc.2551461339 Jun 02 03:43:59 PM PDT 24 Jun 02 03:48:35 PM PDT 24 2675888216 ps
T342 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2408830005 Jun 02 03:47:23 PM PDT 24 Jun 02 04:09:11 PM PDT 24 6707774332 ps
T437 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1057451685 Jun 02 03:43:50 PM PDT 24 Jun 02 03:57:53 PM PDT 24 5325098800 ps
T378 /workspace/coverage/default/76.chip_sw_all_escalation_resets.673784049 Jun 02 04:12:22 PM PDT 24 Jun 02 04:21:55 PM PDT 24 5547321200 ps
T149 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2850762273 Jun 02 04:02:28 PM PDT 24 Jun 02 05:11:24 PM PDT 24 24716516973 ps
T387 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1240786600 Jun 02 03:44:07 PM PDT 24 Jun 02 03:55:52 PM PDT 24 4420290104 ps
T331 /workspace/coverage/default/1.chip_plic_all_irqs_20.1990083259 Jun 02 03:48:53 PM PDT 24 Jun 02 04:04:43 PM PDT 24 4556332958 ps
T388 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1924039220 Jun 02 04:08:50 PM PDT 24 Jun 02 04:19:35 PM PDT 24 4212504260 ps
T389 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3970722724 Jun 02 04:10:15 PM PDT 24 Jun 02 04:19:27 PM PDT 24 4413542020 ps
T245 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3117294672 Jun 02 04:16:56 PM PDT 24 Jun 02 04:25:47 PM PDT 24 5071366304 ps
T390 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2614480340 Jun 02 03:51:09 PM PDT 24 Jun 02 04:01:47 PM PDT 24 3289020326 ps
T352 /workspace/coverage/default/3.chip_sw_uart_tx_rx.2518198720 Jun 02 04:04:29 PM PDT 24 Jun 02 04:15:19 PM PDT 24 4197320710 ps
T391 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3890824653 Jun 02 04:00:06 PM PDT 24 Jun 02 05:07:53 PM PDT 24 18490205527 ps
T275 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1130083730 Jun 02 03:50:57 PM PDT 24 Jun 02 04:57:25 PM PDT 24 13221208880 ps
T184 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3619379947 Jun 02 03:55:54 PM PDT 24 Jun 02 05:30:17 PM PDT 24 43243076715 ps
T915 /workspace/coverage/default/0.chip_tap_straps_rma.1810805238 Jun 02 03:41:28 PM PDT 24 Jun 02 03:51:45 PM PDT 24 6124623634 ps
T916 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3299213960 Jun 02 03:45:45 PM PDT 24 Jun 02 04:51:35 PM PDT 24 19004728658 ps
T51 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.365540941 Jun 02 03:58:04 PM PDT 24 Jun 02 04:08:33 PM PDT 24 4928082306 ps
T734 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2615776269 Jun 02 04:07:42 PM PDT 24 Jun 02 04:14:38 PM PDT 24 3564199290 ps
T24 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3357512337 Jun 02 03:44:53 PM PDT 24 Jun 02 03:49:52 PM PDT 24 2544755814 ps
T364 /workspace/coverage/default/2.chip_sw_hmac_enc.356282581 Jun 02 04:01:57 PM PDT 24 Jun 02 04:06:27 PM PDT 24 3375969096 ps
T917 /workspace/coverage/default/2.chip_sw_aes_idle.3278981845 Jun 02 03:59:05 PM PDT 24 Jun 02 04:02:39 PM PDT 24 2896777874 ps
T918 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3390374150 Jun 02 04:08:02 PM PDT 24 Jun 02 04:20:07 PM PDT 24 8194346279 ps
T167 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3903329755 Jun 02 03:56:29 PM PDT 24 Jun 02 05:15:52 PM PDT 24 47832914530 ps
T210 /workspace/coverage/default/1.chip_jtag_mem_access.4253608691 Jun 02 03:39:05 PM PDT 24 Jun 02 04:05:52 PM PDT 24 13275507351 ps
T919 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1739556838 Jun 02 03:57:18 PM PDT 24 Jun 02 04:02:20 PM PDT 24 4140626020 ps
T668 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.146635126 Jun 02 03:46:22 PM PDT 24 Jun 02 03:48:14 PM PDT 24 2487048996 ps
T366 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4146640101 Jun 02 04:05:57 PM PDT 24 Jun 02 04:13:18 PM PDT 24 3669386938 ps
T920 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3311908551 Jun 02 04:07:54 PM PDT 24 Jun 02 05:13:51 PM PDT 24 14059845840 ps
T713 /workspace/coverage/default/31.chip_sw_all_escalation_resets.2097754490 Jun 02 04:08:22 PM PDT 24 Jun 02 04:17:27 PM PDT 24 5648881446 ps
T328 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4074293559 Jun 02 03:58:23 PM PDT 24 Jun 02 04:35:25 PM PDT 24 14390119860 ps
T921 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1685536635 Jun 02 03:46:38 PM PDT 24 Jun 02 03:51:07 PM PDT 24 2565814630 ps
T800 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191389190 Jun 02 04:12:44 PM PDT 24 Jun 02 04:19:02 PM PDT 24 3768876892 ps
T9 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.678054004 Jun 02 03:50:27 PM PDT 24 Jun 02 04:23:09 PM PDT 24 21060416128 ps
T922 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1521252163 Jun 02 03:43:00 PM PDT 24 Jun 02 03:47:20 PM PDT 24 3198279486 ps
T802 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3813461047 Jun 02 04:09:14 PM PDT 24 Jun 02 04:16:40 PM PDT 24 3956787718 ps
T253 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2510311371 Jun 02 04:01:01 PM PDT 24 Jun 02 04:05:37 PM PDT 24 2698276012 ps
T799 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3009364483 Jun 02 04:07:38 PM PDT 24 Jun 02 04:18:31 PM PDT 24 5032904014 ps
T85 /workspace/coverage/default/54.chip_sw_all_escalation_resets.688906429 Jun 02 04:09:53 PM PDT 24 Jun 02 04:18:44 PM PDT 24 4999277950 ps
T291 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.976180125 Jun 02 03:41:54 PM PDT 24 Jun 02 03:52:12 PM PDT 24 5144525117 ps
T923 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3441919271 Jun 02 03:49:51 PM PDT 24 Jun 02 04:48:32 PM PDT 24 12939290227 ps
T924 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3941860019 Jun 02 03:54:11 PM PDT 24 Jun 02 03:58:00 PM PDT 24 2778794810 ps
T340 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.142965451 Jun 02 03:55:48 PM PDT 24 Jun 02 04:06:02 PM PDT 24 3867128192 ps
T161 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.859874560 Jun 02 03:49:15 PM PDT 24 Jun 02 03:55:08 PM PDT 24 2827150659 ps
T401 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.205325839 Jun 02 04:02:16 PM PDT 24 Jun 02 04:06:10 PM PDT 24 2796087056 ps
T730 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655953858 Jun 02 04:05:53 PM PDT 24 Jun 02 04:12:50 PM PDT 24 3852099024 ps
T676 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1283228793 Jun 02 04:07:41 PM PDT 24 Jun 02 04:18:53 PM PDT 24 5692677880 ps
T925 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3631967185 Jun 02 03:47:13 PM PDT 24 Jun 02 03:55:07 PM PDT 24 5232126208 ps
T926 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2286557265 Jun 02 04:07:54 PM PDT 24 Jun 02 05:10:55 PM PDT 24 15233088120 ps
T29 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3454356595 Jun 02 03:45:08 PM PDT 24 Jun 02 03:48:47 PM PDT 24 2752517608 ps
T927 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2943007542 Jun 02 04:06:27 PM PDT 24 Jun 02 04:14:40 PM PDT 24 5621782456 ps
T779 /workspace/coverage/default/49.chip_sw_all_escalation_resets.415544507 Jun 02 04:09:26 PM PDT 24 Jun 02 04:20:12 PM PDT 24 4627799032 ps
T41 /workspace/coverage/default/1.chip_sw_gpio.3136294964 Jun 02 03:48:42 PM PDT 24 Jun 02 03:56:18 PM PDT 24 3651318376 ps
T48 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2484187047 Jun 02 03:49:27 PM PDT 24 Jun 02 03:55:54 PM PDT 24 2761729080 ps
T214 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1379982823 Jun 02 03:59:00 PM PDT 24 Jun 02 04:21:00 PM PDT 24 6278981892 ps
T233 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1770027015 Jun 02 04:00:04 PM PDT 24 Jun 02 05:12:09 PM PDT 24 13961739482 ps
T928 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.676388732 Jun 02 03:51:52 PM PDT 24 Jun 02 03:56:39 PM PDT 24 2836904490 ps
T929 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4178829608 Jun 02 03:50:27 PM PDT 24 Jun 02 04:42:27 PM PDT 24 11229044553 ps
T930 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.83607377 Jun 02 03:46:00 PM PDT 24 Jun 02 03:50:38 PM PDT 24 3282471208 ps
T379 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2555379610 Jun 02 04:09:15 PM PDT 24 Jun 02 04:16:29 PM PDT 24 3611821854 ps
T332 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3372391028 Jun 02 03:42:38 PM PDT 24 Jun 02 03:52:41 PM PDT 24 3703777075 ps
T931 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1224230603 Jun 02 03:44:21 PM PDT 24 Jun 02 03:48:22 PM PDT 24 2785207896 ps
T731 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.801081931 Jun 02 04:06:46 PM PDT 24 Jun 02 04:13:42 PM PDT 24 3487317134 ps
T686 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2556443856 Jun 02 03:59:01 PM PDT 24 Jun 02 04:04:40 PM PDT 24 3356218984 ps
T932 /workspace/coverage/default/2.chip_sw_example_flash.2020046415 Jun 02 03:53:45 PM PDT 24 Jun 02 03:58:40 PM PDT 24 2727631704 ps
T933 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4254208504 Jun 02 03:43:58 PM PDT 24 Jun 02 03:49:34 PM PDT 24 3511775922 ps
T934 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.826803030 Jun 02 04:05:18 PM PDT 24 Jun 02 05:51:29 PM PDT 24 26864087098 ps
T935 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.684806479 Jun 02 03:41:42 PM PDT 24 Jun 02 03:45:31 PM PDT 24 2854926980 ps
T759 /workspace/coverage/default/17.chip_sw_all_escalation_resets.2675228507 Jun 02 04:06:57 PM PDT 24 Jun 02 04:19:52 PM PDT 24 5465678498 ps
T353 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.804976900 Jun 02 04:05:01 PM PDT 24 Jun 02 04:15:10 PM PDT 24 4332225284 ps
T405 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.823590603 Jun 02 03:46:27 PM PDT 24 Jun 02 03:49:50 PM PDT 24 2495100798 ps
T776 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3917873094 Jun 02 04:09:50 PM PDT 24 Jun 02 04:19:54 PM PDT 24 5581499116 ps
T936 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.741914078 Jun 02 03:48:43 PM PDT 24 Jun 02 03:59:40 PM PDT 24 8187214928 ps
T937 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1514199604 Jun 02 04:05:54 PM PDT 24 Jun 02 04:37:34 PM PDT 24 8125322858 ps
T938 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2773142965 Jun 02 03:46:02 PM PDT 24 Jun 02 03:51:21 PM PDT 24 2938269660 ps
T329 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.910701271 Jun 02 03:42:29 PM PDT 24 Jun 02 04:09:16 PM PDT 24 11322843820 ps
T939 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2905734711 Jun 02 03:56:33 PM PDT 24 Jun 02 04:22:38 PM PDT 24 7870589240 ps
T755 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.557381508 Jun 02 04:04:29 PM PDT 24 Jun 02 04:12:16 PM PDT 24 4164827288 ps
T38 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1826762768 Jun 02 03:42:02 PM PDT 24 Jun 02 04:26:27 PM PDT 24 11858390828 ps
T150 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1529287841 Jun 02 03:46:54 PM PDT 24 Jun 02 06:59:47 PM PDT 24 57647978315 ps
T940 /workspace/coverage/default/2.chip_sw_rv_timer_irq.771628112 Jun 02 03:58:42 PM PDT 24 Jun 02 04:02:28 PM PDT 24 2825059376 ps
T941 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1952235655 Jun 02 03:43:17 PM PDT 24 Jun 02 03:48:26 PM PDT 24 2651047500 ps
T942 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2939919966 Jun 02 03:48:50 PM PDT 24 Jun 02 03:54:23 PM PDT 24 2790257006 ps
T687 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3907080952 Jun 02 03:49:16 PM PDT 24 Jun 02 03:53:09 PM PDT 24 3427115342 ps
T744 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.936568364 Jun 02 04:10:13 PM PDT 24 Jun 02 04:17:40 PM PDT 24 3840770718 ps
T737 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2200597994 Jun 02 04:06:58 PM PDT 24 Jun 02 04:21:10 PM PDT 24 4938554856 ps
T789 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1112759892 Jun 02 04:09:13 PM PDT 24 Jun 02 04:15:09 PM PDT 24 4231755660 ps
T943 /workspace/coverage/default/1.rom_keymgr_functest.873025777 Jun 02 03:51:27 PM PDT 24 Jun 02 04:04:17 PM PDT 24 4672197828 ps
T944 /workspace/coverage/default/1.chip_sw_hmac_smoketest.2043922559 Jun 02 03:51:30 PM PDT 24 Jun 02 03:56:42 PM PDT 24 3599618030 ps
T70 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3557803297 Jun 02 03:47:25 PM PDT 24 Jun 02 03:53:52 PM PDT 24 4735715801 ps
T174 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2181034676 Jun 02 03:41:51 PM PDT 24 Jun 02 05:23:59 PM PDT 24 48318458028 ps
T945 /workspace/coverage/default/1.rom_e2e_asm_init_prod.966262352 Jun 02 03:57:16 PM PDT 24 Jun 02 05:08:11 PM PDT 24 14215371098 ps
T544 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.923294438 Jun 02 03:45:32 PM PDT 24 Jun 02 04:00:32 PM PDT 24 4761927808 ps
T946 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2834347212 Jun 02 03:48:40 PM PDT 24 Jun 02 04:43:19 PM PDT 24 11027534886 ps
T714 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3125964957 Jun 02 04:07:37 PM PDT 24 Jun 02 04:20:00 PM PDT 24 6016286776 ps
T947 /workspace/coverage/default/2.chip_sw_kmac_idle.4040082285 Jun 02 04:00:32 PM PDT 24 Jun 02 04:04:55 PM PDT 24 2345007770 ps
T794 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1083754578 Jun 02 04:05:22 PM PDT 24 Jun 02 04:16:18 PM PDT 24 4634670860 ps
T948 /workspace/coverage/default/1.chip_sw_power_idle_load.485719239 Jun 02 03:51:47 PM PDT 24 Jun 02 04:03:40 PM PDT 24 4054662200 ps
T144 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2300271935 Jun 02 03:46:32 PM PDT 24 Jun 02 03:51:17 PM PDT 24 3047250697 ps
T772 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2182831520 Jun 02 04:09:32 PM PDT 24 Jun 02 04:21:50 PM PDT 24 4977751436 ps
T949 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1312533835 Jun 02 03:47:16 PM PDT 24 Jun 02 05:00:16 PM PDT 24 14272426822 ps
T10 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.516219829 Jun 02 03:44:12 PM PDT 24 Jun 02 04:12:27 PM PDT 24 20931344520 ps
T950 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2740500747 Jun 02 04:05:15 PM PDT 24 Jun 02 04:13:25 PM PDT 24 3832857980 ps
T951 /workspace/coverage/default/1.chip_sw_aes_entropy.2028261045 Jun 02 03:45:18 PM PDT 24 Jun 02 03:50:15 PM PDT 24 3264766072 ps
T952 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1060289818 Jun 02 03:53:57 PM PDT 24 Jun 02 04:05:13 PM PDT 24 4343548482 ps
T767 /workspace/coverage/default/43.chip_sw_all_escalation_resets.3132831980 Jun 02 04:08:20 PM PDT 24 Jun 02 04:21:43 PM PDT 24 5215457882 ps
T257 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2097469035 Jun 02 03:45:06 PM PDT 24 Jun 02 03:52:41 PM PDT 24 3600451230 ps
T953 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1062180218 Jun 02 03:47:40 PM PDT 24 Jun 02 04:25:45 PM PDT 24 28606626582 ps
T954 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4229705681 Jun 02 03:48:21 PM PDT 24 Jun 02 04:47:50 PM PDT 24 13338337274 ps
T955 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2046203558 Jun 02 04:01:43 PM PDT 24 Jun 02 04:10:39 PM PDT 24 4449802060 ps
T956 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4116918074 Jun 02 03:44:56 PM PDT 24 Jun 02 04:14:00 PM PDT 24 7768445702 ps
T188 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2704591912 Jun 02 03:46:29 PM PDT 24 Jun 02 03:57:57 PM PDT 24 5326481375 ps
T12 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.87970571 Jun 02 03:53:34 PM PDT 24 Jun 02 03:59:02 PM PDT 24 3412875252 ps
T439 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3419156168 Jun 02 04:04:34 PM PDT 24 Jun 02 04:16:01 PM PDT 24 6842117802 ps
T338 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2192459983 Jun 02 03:49:04 PM PDT 24 Jun 02 03:59:58 PM PDT 24 4999683346 ps
T25 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1914170374 Jun 02 03:43:27 PM PDT 24 Jun 02 03:48:20 PM PDT 24 2710588406 ps
T164 /workspace/coverage/default/88.chip_sw_all_escalation_resets.4219984026 Jun 02 04:13:38 PM PDT 24 Jun 02 04:22:10 PM PDT 24 4026178916 ps
T440 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.336565662 Jun 02 03:46:55 PM PDT 24 Jun 02 04:48:29 PM PDT 24 18486726147 ps
T441 /workspace/coverage/default/2.rom_e2e_shutdown_output.2390900263 Jun 02 04:09:27 PM PDT 24 Jun 02 05:00:39 PM PDT 24 23391041720 ps
T139 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1655002521 Jun 02 03:43:58 PM PDT 24 Jun 02 04:17:47 PM PDT 24 15188407890 ps
T442 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1379120221 Jun 02 03:57:09 PM PDT 24 Jun 02 04:14:15 PM PDT 24 6100588200 ps
T246 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2337592930 Jun 02 04:07:12 PM PDT 24 Jun 02 04:15:36 PM PDT 24 4232268742 ps
T460 /workspace/coverage/default/89.chip_sw_all_escalation_resets.3696136273 Jun 02 04:13:33 PM PDT 24 Jun 02 04:24:17 PM PDT 24 5001860100 ps
T132 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4278276912 Jun 02 04:06:24 PM PDT 24 Jun 02 04:17:42 PM PDT 24 6483629750 ps
T377 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1168147055 Jun 02 03:44:49 PM PDT 24 Jun 02 07:29:02 PM PDT 24 78098254386 ps
T957 /workspace/coverage/default/3.chip_tap_straps_prod.1832542435 Jun 02 04:03:27 PM PDT 24 Jun 02 04:06:21 PM PDT 24 2812288705 ps
T26 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4113616961 Jun 02 03:53:39 PM PDT 24 Jun 02 03:59:05 PM PDT 24 3042213179 ps
T39 /workspace/coverage/default/0.chip_sw_usbdev_stream.1208263860 Jun 02 03:44:34 PM PDT 24 Jun 02 05:01:49 PM PDT 24 18837364400 ps
T958 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4088049433 Jun 02 03:48:39 PM PDT 24 Jun 02 03:57:07 PM PDT 24 4312667558 ps
T959 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2826254161 Jun 02 03:46:43 PM PDT 24 Jun 02 03:57:22 PM PDT 24 6299512598 ps
T145 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2672718132 Jun 02 03:42:44 PM PDT 24 Jun 02 03:53:00 PM PDT 24 3349599976 ps
T960 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1881446629 Jun 02 03:43:16 PM PDT 24 Jun 02 04:27:02 PM PDT 24 28673869560 ps
T376 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2162836251 Jun 02 03:48:06 PM PDT 24 Jun 02 03:51:28 PM PDT 24 2185860143 ps
T961 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2106697918 Jun 02 04:07:03 PM PDT 24 Jun 02 04:58:23 PM PDT 24 14267184302 ps
T736 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3568371284 Jun 02 04:13:42 PM PDT 24 Jun 02 04:23:05 PM PDT 24 5402777394 ps
T65 /workspace/coverage/default/3.chip_tap_straps_rma.2144991198 Jun 02 04:03:48 PM PDT 24 Jun 02 04:07:46 PM PDT 24 3377968986 ps
T962 /workspace/coverage/default/2.chip_tap_straps_dev.2679375937 Jun 02 04:01:23 PM PDT 24 Jun 02 04:14:29 PM PDT 24 6123280108 ps
T963 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1433483155 Jun 02 03:50:15 PM PDT 24 Jun 02 04:00:43 PM PDT 24 6936072248 ps
T964 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2353810778 Jun 02 03:57:52 PM PDT 24 Jun 02 04:32:39 PM PDT 24 11698281691 ps
T965 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.606063343 Jun 02 03:45:25 PM PDT 24 Jun 02 04:18:49 PM PDT 24 11090815687 ps
T400 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1040847933 Jun 02 04:08:01 PM PDT 24 Jun 02 05:11:24 PM PDT 24 14415149996 ps
T966 /workspace/coverage/default/70.chip_sw_all_escalation_resets.1584681674 Jun 02 04:15:12 PM PDT 24 Jun 02 04:26:29 PM PDT 24 6460118924 ps
T360 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2222378989 Jun 02 03:45:28 PM PDT 24 Jun 02 03:58:17 PM PDT 24 4751231068 ps
T967 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2633517412 Jun 02 03:43:48 PM PDT 24 Jun 02 04:36:14 PM PDT 24 13170986992 ps
T61 /workspace/coverage/default/2.chip_sw_alert_test.1836545853 Jun 02 04:01:13 PM PDT 24 Jun 02 04:06:23 PM PDT 24 3231529576 ps
T968 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.553090997 Jun 02 03:46:58 PM PDT 24 Jun 02 03:57:25 PM PDT 24 4685886534 ps
T461 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1849932856 Jun 02 03:41:11 PM PDT 24 Jun 02 03:44:53 PM PDT 24 2199449180 ps
T407 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3141210250 Jun 02 03:44:26 PM PDT 24 Jun 02 03:52:00 PM PDT 24 3828273542 ps
T292 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2498751656 Jun 02 04:00:16 PM PDT 24 Jun 02 04:09:46 PM PDT 24 3790159417 ps
T373 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1849506641 Jun 02 03:57:28 PM PDT 24 Jun 02 04:46:20 PM PDT 24 34688265290 ps
T969 /workspace/coverage/default/0.chip_sw_otbn_randomness.2531425293 Jun 02 03:43:00 PM PDT 24 Jun 02 03:59:17 PM PDT 24 5976098944 ps
T345 /workspace/coverage/default/0.chip_plic_all_irqs_20.4197806836 Jun 02 03:45:05 PM PDT 24 Jun 02 03:56:57 PM PDT 24 4569176332 ps
T970 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1260005528 Jun 02 03:58:11 PM PDT 24 Jun 02 04:16:02 PM PDT 24 5409712628 ps
T971 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.864785911 Jun 02 03:57:18 PM PDT 24 Jun 02 05:03:02 PM PDT 24 13921429855 ps
T972 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017235286 Jun 02 04:09:45 PM PDT 24 Jun 02 04:17:39 PM PDT 24 4176145768 ps
T52 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2794931578 Jun 02 03:44:53 PM PDT 24 Jun 02 03:54:40 PM PDT 24 6134373200 ps
T973 /workspace/coverage/default/1.chip_sw_example_manufacturer.96464519 Jun 02 03:48:51 PM PDT 24 Jun 02 03:52:05 PM PDT 24 2821423436 ps
T354 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.278484027 Jun 02 04:08:12 PM PDT 24 Jun 02 04:35:30 PM PDT 24 9423092972 ps
T786 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348462190 Jun 02 04:12:46 PM PDT 24 Jun 02 04:20:25 PM PDT 24 3372764488 ps
T230 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.70473614 Jun 02 03:47:57 PM PDT 24 Jun 02 04:18:42 PM PDT 24 9522083170 ps
T974 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027315883 Jun 02 03:45:15 PM PDT 24 Jun 02 03:51:44 PM PDT 24 3397600804 ps
T49 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4197741363 Jun 02 03:56:11 PM PDT 24 Jun 02 04:02:02 PM PDT 24 2962659348 ps
T975 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3626147018 Jun 02 03:59:26 PM PDT 24 Jun 02 04:04:31 PM PDT 24 2413266904 ps
T976 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.326707921 Jun 02 03:47:36 PM PDT 24 Jun 02 03:51:18 PM PDT 24 2947277122 ps
T238 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3110246795 Jun 02 03:46:56 PM PDT 24 Jun 02 04:21:30 PM PDT 24 24958881371 ps
T977 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3890776541 Jun 02 04:03:03 PM PDT 24 Jun 02 04:07:36 PM PDT 24 2847690243 ps
T978 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3321521299 Jun 02 04:04:59 PM PDT 24 Jun 02 04:34:32 PM PDT 24 8396638470 ps
T795 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497270578 Jun 02 04:06:38 PM PDT 24 Jun 02 04:12:13 PM PDT 24 3222486660 ps
T748 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1773737542 Jun 02 04:12:31 PM PDT 24 Jun 02 04:24:01 PM PDT 24 4791196630 ps
T398 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3840656285 Jun 02 03:49:12 PM PDT 24 Jun 02 05:28:09 PM PDT 24 22733178146 ps
T468 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.741585592 Jun 02 04:09:34 PM PDT 24 Jun 02 04:16:57 PM PDT 24 3891238310 ps
T979 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3239418891 Jun 02 03:43:59 PM PDT 24 Jun 02 04:31:18 PM PDT 24 12355837736 ps
T980 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4111955366 Jun 02 04:07:23 PM PDT 24 Jun 02 04:32:34 PM PDT 24 8008627702 ps
T981 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1996995011 Jun 02 04:04:17 PM PDT 24 Jun 02 04:08:03 PM PDT 24 2314452408 ps
T750 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.726740827 Jun 02 04:11:26 PM PDT 24 Jun 02 04:17:18 PM PDT 24 3735082680 ps
T781 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3242776990 Jun 02 04:12:15 PM PDT 24 Jun 02 04:21:45 PM PDT 24 4394572700 ps
T791 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3176104466 Jun 02 04:11:36 PM PDT 24 Jun 02 04:22:03 PM PDT 24 4977530456 ps
T982 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2060695769 Jun 02 04:06:00 PM PDT 24 Jun 02 04:14:01 PM PDT 24 6144347542 ps
T983 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3317097903 Jun 02 03:42:01 PM PDT 24 Jun 02 03:49:34 PM PDT 24 4665499551 ps
T984 /workspace/coverage/default/0.chip_sw_kmac_idle.467744444 Jun 02 03:43:19 PM PDT 24 Jun 02 03:46:31 PM PDT 24 2418324580 ps
T985 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1521041639 Jun 02 03:58:05 PM PDT 24 Jun 02 04:01:36 PM PDT 24 2438676720 ps
T216 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3105480885 Jun 02 03:46:04 PM PDT 24 Jun 02 03:51:53 PM PDT 24 2709231703 ps
T333 /workspace/coverage/default/2.chip_plic_all_irqs_0.4253415543 Jun 02 04:01:00 PM PDT 24 Jun 02 04:21:33 PM PDT 24 5572163732 ps
T715 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784875043 Jun 02 04:08:58 PM PDT 24 Jun 02 04:14:36 PM PDT 24 3158503294 ps
T236 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.489825643 Jun 02 03:48:46 PM PDT 24 Jun 02 05:21:17 PM PDT 24 49170301538 ps
T986 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2463294939 Jun 02 03:51:41 PM PDT 24 Jun 02 04:53:34 PM PDT 24 24725793560 ps
T987 /workspace/coverage/default/1.chip_sw_edn_auto_mode.734317128 Jun 02 03:45:33 PM PDT 24 Jun 02 04:02:56 PM PDT 24 4747620522 ps
T469 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1339443613 Jun 02 04:00:20 PM PDT 24 Jun 02 04:21:08 PM PDT 24 5507033596 ps
T988 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3037230835 Jun 02 03:58:43 PM PDT 24 Jun 02 04:06:27 PM PDT 24 7635084300 ps
T989 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.237334273 Jun 02 03:43:05 PM PDT 24 Jun 02 04:10:11 PM PDT 24 6708703790 ps
T158 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3104547523 Jun 02 03:43:27 PM PDT 24 Jun 02 07:04:34 PM PDT 24 255669387204 ps
T990 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1151872130 Jun 02 03:43:22 PM PDT 24 Jun 02 03:57:32 PM PDT 24 5368635740 ps
T349 /workspace/coverage/default/1.chip_sw_pattgen_ios.3795577138 Jun 02 03:40:57 PM PDT 24 Jun 02 03:44:54 PM PDT 24 2821437784 ps
T991 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2275043978 Jun 02 03:49:24 PM PDT 24 Jun 02 04:52:18 PM PDT 24 14113612488 ps
T739 /workspace/coverage/default/52.chip_sw_all_escalation_resets.360011124 Jun 02 04:09:28 PM PDT 24 Jun 02 04:21:35 PM PDT 24 6183001304 ps
T992 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1207627086 Jun 02 03:47:39 PM PDT 24 Jun 02 04:58:14 PM PDT 24 15160277020 ps
T334 /workspace/coverage/default/1.chip_plic_all_irqs_0.3363420717 Jun 02 03:44:51 PM PDT 24 Jun 02 04:08:24 PM PDT 24 5818559164 ps
T993 /workspace/coverage/default/4.chip_tap_straps_rma.4176438670 Jun 02 04:04:21 PM PDT 24 Jun 02 04:19:06 PM PDT 24 7504282098 ps
T666 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.703687564 Jun 02 03:46:44 PM PDT 24 Jun 02 03:55:58 PM PDT 24 4316686688 ps
T994 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.320321669 Jun 02 04:00:45 PM PDT 24 Jun 02 04:13:42 PM PDT 24 4619582292 ps
T719 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.253709149 Jun 02 04:06:46 PM PDT 24 Jun 02 04:13:50 PM PDT 24 3058228600 ps
T293 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.610830629 Jun 02 03:46:44 PM PDT 24 Jun 02 03:56:59 PM PDT 24 5906618440 ps
T760 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.147735382 Jun 02 04:08:41 PM PDT 24 Jun 02 04:16:43 PM PDT 24 3783754040 ps
T995 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3946080577 Jun 02 03:49:16 PM PDT 24 Jun 02 04:02:01 PM PDT 24 4841465828 ps
T996 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.914003840 Jun 02 04:05:49 PM PDT 24 Jun 02 04:40:53 PM PDT 24 8727441810 ps
T997 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2617961108 Jun 02 03:47:42 PM PDT 24 Jun 02 04:46:31 PM PDT 24 13113714120 ps
T399 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2249208131 Jun 02 03:47:33 PM PDT 24 Jun 02 05:36:25 PM PDT 24 21922625240 ps
T998 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2715187744 Jun 02 03:44:57 PM PDT 24 Jun 02 03:49:04 PM PDT 24 3050774758 ps
T999 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3811126579 Jun 02 03:45:05 PM PDT 24 Jun 02 04:49:45 PM PDT 24 16623481872 ps
T658 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1680190914 Jun 02 04:09:33 PM PDT 24 Jun 02 04:15:24 PM PDT 24 3113539240 ps
T204 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1696898237 Jun 02 03:46:48 PM PDT 24 Jun 02 03:58:18 PM PDT 24 5238569146 ps
T1000 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.341388791 Jun 02 03:45:02 PM PDT 24 Jun 02 03:49:35 PM PDT 24 2973599054 ps
T303 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1302651266 Jun 02 03:45:42 PM PDT 24 Jun 02 03:50:45 PM PDT 24 2838422192 ps
T1001 /workspace/coverage/default/1.chip_sw_edn_kat.2737338169 Jun 02 03:45:40 PM PDT 24 Jun 02 03:56:18 PM PDT 24 3538865920 ps
T765 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3752730190 Jun 02 04:10:05 PM PDT 24 Jun 02 04:23:40 PM PDT 24 5749245104 ps
T1002 /workspace/coverage/default/2.chip_sw_edn_sw_mode.73533684 Jun 02 04:01:46 PM PDT 24 Jun 02 04:25:17 PM PDT 24 5731407342 ps
T244 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3004387340 Jun 02 03:47:48 PM PDT 24 Jun 02 06:42:53 PM PDT 24 254954535900 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.726794242 Jun 02 03:45:08 PM PDT 24 Jun 02 03:54:17 PM PDT 24 4253946710 ps
T1003 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1857463208 Jun 02 03:50:02 PM PDT 24 Jun 02 04:46:49 PM PDT 24 11456380806 ps
T263 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1410930056 Jun 02 04:14:04 PM PDT 24 Jun 02 04:22:22 PM PDT 24 4399073360 ps
T761 /workspace/coverage/default/79.chip_sw_all_escalation_resets.132907558 Jun 02 04:11:50 PM PDT 24 Jun 02 04:21:18 PM PDT 24 4455223676 ps
T1004 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2975542671 Jun 02 03:48:36 PM PDT 24 Jun 02 04:04:57 PM PDT 24 5783491085 ps
T1005 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1584353403 Jun 02 03:57:10 PM PDT 24 Jun 02 04:48:45 PM PDT 24 11014827243 ps
T1006 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.800659082 Jun 02 03:57:56 PM PDT 24 Jun 02 04:06:43 PM PDT 24 4089525664 ps
T343 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.4229976767 Jun 02 03:48:10 PM PDT 24 Jun 02 04:19:46 PM PDT 24 7488596424 ps
T1007 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3683108426 Jun 02 03:58:04 PM PDT 24 Jun 02 04:43:03 PM PDT 24 23051451707 ps
T1008 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1190569258 Jun 02 03:50:47 PM PDT 24 Jun 02 03:56:55 PM PDT 24 2960027372 ps
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