Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.84 95.42 93.64 95.49 94.45 96.47 99.58


Total test records in report: 2875
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html
T221 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.885501763 Jun 02 03:45:26 PM PDT 24 Jun 02 04:40:46 PM PDT 24 20106606626 ps
T1009 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2050561701 Jun 02 03:47:08 PM PDT 24 Jun 02 04:07:32 PM PDT 24 6411847258 ps
T669 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1234449185 Jun 02 03:57:32 PM PDT 24 Jun 02 03:59:39 PM PDT 24 3101059389 ps
T1010 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2104515327 Jun 02 03:47:11 PM PDT 24 Jun 02 04:09:32 PM PDT 24 5603793155 ps
T1011 /workspace/coverage/default/1.chip_sw_power_sleep_load.880629556 Jun 02 03:51:39 PM PDT 24 Jun 02 04:01:10 PM PDT 24 10762912168 ps
T1012 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.395400833 Jun 02 03:46:23 PM PDT 24 Jun 02 03:48:39 PM PDT 24 2440287168 ps
T1013 /workspace/coverage/default/1.chip_sw_aes_idle.2947740220 Jun 02 03:47:38 PM PDT 24 Jun 02 03:52:50 PM PDT 24 3239570708 ps
T264 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.769856793 Jun 02 03:41:35 PM PDT 24 Jun 02 03:50:03 PM PDT 24 5625900720 ps
T1014 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2053746143 Jun 02 03:59:52 PM PDT 24 Jun 02 04:10:42 PM PDT 24 3998260300 ps
T1015 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.599545291 Jun 02 03:52:02 PM PDT 24 Jun 02 04:00:18 PM PDT 24 3705079848 ps
T1016 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.454216140 Jun 02 03:57:39 PM PDT 24 Jun 02 04:09:12 PM PDT 24 6974982361 ps
T347 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1923745787 Jun 02 03:44:03 PM PDT 24 Jun 02 03:57:20 PM PDT 24 5041563294 ps
T777 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1479983654 Jun 02 04:12:36 PM PDT 24 Jun 02 04:21:37 PM PDT 24 4847157556 ps
T1017 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1960877096 Jun 02 03:47:04 PM PDT 24 Jun 02 03:50:04 PM PDT 24 2156139779 ps
T86 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028427642 Jun 02 04:09:44 PM PDT 24 Jun 02 04:16:30 PM PDT 24 4178224264 ps
T1018 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3197181410 Jun 02 04:02:14 PM PDT 24 Jun 02 04:14:30 PM PDT 24 5020408494 ps
T1019 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2552468021 Jun 02 03:54:33 PM PDT 24 Jun 02 05:01:18 PM PDT 24 14624806832 ps
T1020 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.715902064 Jun 02 04:05:46 PM PDT 24 Jun 02 04:14:49 PM PDT 24 4649384890 ps
T1021 /workspace/coverage/default/2.chip_tap_straps_prod.624344535 Jun 02 04:01:26 PM PDT 24 Jun 02 04:17:47 PM PDT 24 10532498947 ps
T185 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3267112447 Jun 02 03:42:51 PM PDT 24 Jun 02 03:49:29 PM PDT 24 3850169180 ps
T254 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3487199487 Jun 02 03:46:57 PM PDT 24 Jun 02 03:51:15 PM PDT 24 2211589968 ps
T1022 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.557971589 Jun 02 04:00:46 PM PDT 24 Jun 02 04:10:05 PM PDT 24 3228830186 ps
T1023 /workspace/coverage/default/1.rom_e2e_asm_init_rma.727978326 Jun 02 03:55:28 PM PDT 24 Jun 02 04:58:11 PM PDT 24 14378301008 ps
T735 /workspace/coverage/default/34.chip_sw_all_escalation_resets.4154273911 Jun 02 04:09:44 PM PDT 24 Jun 02 04:20:35 PM PDT 24 5289220296 ps
T1024 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.433167504 Jun 02 03:45:32 PM PDT 24 Jun 02 04:55:30 PM PDT 24 15827056244 ps
T134 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2433446859 Jun 02 04:00:57 PM PDT 24 Jun 02 04:08:41 PM PDT 24 4922010008 ps
T1025 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.186627267 Jun 02 03:45:47 PM PDT 24 Jun 02 04:05:39 PM PDT 24 5488619114 ps
T723 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986947521 Jun 02 04:09:41 PM PDT 24 Jun 02 04:16:56 PM PDT 24 4657232008 ps
T1026 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.107988362 Jun 02 03:41:42 PM PDT 24 Jun 02 03:59:13 PM PDT 24 11795984600 ps
T667 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4001272806 Jun 02 03:48:40 PM PDT 24 Jun 02 03:57:43 PM PDT 24 5458498694 ps
T237 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1865560162 Jun 02 03:46:31 PM PDT 24 Jun 02 05:20:53 PM PDT 24 50809038704 ps
T1027 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1890263795 Jun 02 03:46:58 PM PDT 24 Jun 02 03:51:20 PM PDT 24 2979364924 ps
T189 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1096375024 Jun 02 03:48:01 PM PDT 24 Jun 02 03:56:03 PM PDT 24 4070012965 ps
T753 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2792572926 Jun 02 04:13:30 PM PDT 24 Jun 02 04:23:36 PM PDT 24 5711396540 ps
T1028 /workspace/coverage/default/1.chip_sw_aes_enc.1941538050 Jun 02 03:47:26 PM PDT 24 Jun 02 03:51:50 PM PDT 24 2943656536 ps
T803 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3636115020 Jun 02 04:07:49 PM PDT 24 Jun 02 04:13:30 PM PDT 24 4241631652 ps
T1029 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1202058984 Jun 02 04:08:02 PM PDT 24 Jun 02 04:18:27 PM PDT 24 8329023900 ps
T155 /workspace/coverage/default/0.chip_plic_all_irqs_10.1375551718 Jun 02 03:49:13 PM PDT 24 Jun 02 03:59:48 PM PDT 24 4349774320 ps
T773 /workspace/coverage/default/53.chip_sw_all_escalation_resets.363272107 Jun 02 04:11:03 PM PDT 24 Jun 02 04:20:31 PM PDT 24 4779687928 ps
T7 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4098777055 Jun 02 03:48:55 PM PDT 24 Jun 02 03:55:38 PM PDT 24 3404437996 ps
T87 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.886793557 Jun 02 04:13:51 PM PDT 24 Jun 02 04:22:15 PM PDT 24 3711819320 ps
T128 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1330953469 Jun 02 03:47:37 PM PDT 24 Jun 02 03:53:16 PM PDT 24 5314386610 ps
T448 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2521370346 Jun 02 04:06:14 PM PDT 24 Jun 02 04:44:05 PM PDT 24 13107694788 ps
T371 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.336870085 Jun 02 03:59:54 PM PDT 24 Jun 02 04:09:03 PM PDT 24 19525043292 ps
T449 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2867842804 Jun 02 04:03:17 PM PDT 24 Jun 02 04:07:55 PM PDT 24 3502026897 ps
T450 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2002443047 Jun 02 04:07:57 PM PDT 24 Jun 02 04:14:37 PM PDT 24 3466516658 ps
T451 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3298302906 Jun 02 03:43:26 PM PDT 24 Jun 02 03:51:06 PM PDT 24 5596503344 ps
T452 /workspace/coverage/default/19.chip_sw_all_escalation_resets.4066335351 Jun 02 04:10:13 PM PDT 24 Jun 02 04:22:12 PM PDT 24 5762946892 ps
T453 /workspace/coverage/default/1.chip_sw_otbn_randomness.2730483436 Jun 02 03:46:44 PM PDT 24 Jun 02 04:02:31 PM PDT 24 5480287992 ps
T140 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1097081015 Jun 02 04:04:14 PM PDT 24 Jun 02 04:40:15 PM PDT 24 17579217507 ps
T151 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.776762673 Jun 02 03:42:05 PM PDT 24 Jun 02 06:40:55 PM PDT 24 58178163783 ps
T778 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080784836 Jun 02 04:12:47 PM PDT 24 Jun 02 04:21:05 PM PDT 24 3975015560 ps
T1030 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4096594057 Jun 02 03:47:43 PM PDT 24 Jun 02 05:15:31 PM PDT 24 21704976083 ps
T1031 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3060638208 Jun 02 04:02:04 PM PDT 24 Jun 02 04:32:18 PM PDT 24 8665161240 ps
T1032 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2602152225 Jun 02 04:05:19 PM PDT 24 Jun 02 06:03:24 PM PDT 24 31468266792 ps
T1033 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3933140904 Jun 02 03:47:57 PM PDT 24 Jun 02 04:00:37 PM PDT 24 19078364520 ps
T1034 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1496433172 Jun 02 03:44:19 PM PDT 24 Jun 02 03:52:06 PM PDT 24 7057565999 ps
T62 /workspace/coverage/default/1.chip_sw_alert_test.1254508553 Jun 02 03:47:57 PM PDT 24 Jun 02 03:53:13 PM PDT 24 3724216520 ps
T1035 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3012486716 Jun 02 04:09:12 PM PDT 24 Jun 02 05:11:27 PM PDT 24 13982664790 ps
T1036 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1591313073 Jun 02 03:58:52 PM PDT 24 Jun 02 04:04:05 PM PDT 24 3529142394 ps
T1037 /workspace/coverage/default/0.chip_sw_kmac_smoketest.814624560 Jun 02 03:42:13 PM PDT 24 Jun 02 03:46:26 PM PDT 24 3120022616 ps
T374 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3274014775 Jun 02 03:47:28 PM PDT 24 Jun 02 04:45:29 PM PDT 24 36903702857 ps
T1038 /workspace/coverage/default/2.chip_sw_gpio_smoketest.998348055 Jun 02 04:03:29 PM PDT 24 Jun 02 04:07:32 PM PDT 24 2534662275 ps
T1039 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3966904608 Jun 02 03:48:49 PM PDT 24 Jun 02 04:12:19 PM PDT 24 7095738521 ps
T1040 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1046032907 Jun 02 04:00:20 PM PDT 24 Jun 02 04:10:04 PM PDT 24 3712173364 ps
T1041 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.527726059 Jun 02 03:46:38 PM PDT 24 Jun 02 04:40:43 PM PDT 24 13623337506 ps
T1042 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1972231616 Jun 02 03:43:33 PM PDT 24 Jun 02 04:13:03 PM PDT 24 8382583660 ps
T1043 /workspace/coverage/default/4.chip_tap_straps_testunlock0.986436204 Jun 02 04:03:46 PM PDT 24 Jun 02 04:20:01 PM PDT 24 8587696216 ps
T1044 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2125714895 Jun 02 03:42:59 PM PDT 24 Jun 02 03:49:11 PM PDT 24 9318875810 ps
T1045 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.981045897 Jun 02 04:07:52 PM PDT 24 Jun 02 04:17:20 PM PDT 24 3662499500 ps
T1046 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2930060770 Jun 02 03:46:46 PM PDT 24 Jun 02 04:17:41 PM PDT 24 7874911752 ps
T1047 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.251050530 Jun 02 04:02:53 PM PDT 24 Jun 02 04:08:34 PM PDT 24 2625470284 ps
T1048 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4178899641 Jun 02 03:59:59 PM PDT 24 Jun 02 04:50:54 PM PDT 24 12208300820 ps
T1049 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.998350923 Jun 02 03:57:40 PM PDT 24 Jun 02 04:05:19 PM PDT 24 3431263880 ps
T670 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1200416100 Jun 02 03:45:17 PM PDT 24 Jun 02 03:47:21 PM PDT 24 2190031815 ps
T1050 /workspace/coverage/default/2.chip_sw_otbn_randomness.608665518 Jun 02 03:58:53 PM PDT 24 Jun 02 04:14:19 PM PDT 24 5976107556 ps
T101 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3090693099 Jun 02 03:45:44 PM PDT 24 Jun 02 04:17:13 PM PDT 24 18893021320 ps
T1051 /workspace/coverage/default/1.chip_sw_aes_masking_off.3632641783 Jun 02 03:51:47 PM PDT 24 Jun 02 03:57:00 PM PDT 24 3685901747 ps
T788 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3796670079 Jun 02 04:15:06 PM PDT 24 Jun 02 04:21:32 PM PDT 24 3200466900 ps
T1052 /workspace/coverage/default/80.chip_sw_all_escalation_resets.1657846773 Jun 02 04:11:37 PM PDT 24 Jun 02 04:23:55 PM PDT 24 5058862770 ps
T1053 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3330039535 Jun 02 03:54:47 PM PDT 24 Jun 02 05:06:08 PM PDT 24 13699734120 ps
T792 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.886341697 Jun 02 04:11:18 PM PDT 24 Jun 02 04:17:31 PM PDT 24 3610666952 ps
T763 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3006265266 Jun 02 04:05:04 PM PDT 24 Jun 02 04:15:15 PM PDT 24 5218616350 ps
T1054 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3526596745 Jun 02 03:48:01 PM PDT 24 Jun 02 04:57:26 PM PDT 24 15517970600 ps
T66 /workspace/coverage/default/1.chip_tap_straps_rma.505271227 Jun 02 03:47:07 PM PDT 24 Jun 02 03:51:57 PM PDT 24 3464951703 ps
T787 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3329409549 Jun 02 04:12:38 PM PDT 24 Jun 02 04:19:59 PM PDT 24 4530727780 ps
T1055 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1750260345 Jun 02 03:51:38 PM PDT 24 Jun 02 03:56:06 PM PDT 24 3245212622 ps
T1056 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2272892127 Jun 02 03:49:27 PM PDT 24 Jun 02 03:54:26 PM PDT 24 2866583234 ps
T1057 /workspace/coverage/default/0.chip_sw_example_flash.1414199046 Jun 02 03:44:19 PM PDT 24 Jun 02 03:47:27 PM PDT 24 2333934692 ps
T752 /workspace/coverage/default/56.chip_sw_all_escalation_resets.808328220 Jun 02 04:12:20 PM PDT 24 Jun 02 04:22:44 PM PDT 24 6078339780 ps
T346 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3011329649 Jun 02 03:46:04 PM PDT 24 Jun 02 04:00:41 PM PDT 24 4909696424 ps
T1058 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.177201223 Jun 02 03:48:57 PM PDT 24 Jun 02 03:53:57 PM PDT 24 2647135378 ps
T1059 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2516495787 Jun 02 03:47:12 PM PDT 24 Jun 02 03:50:38 PM PDT 24 2543402886 ps
T341 /workspace/coverage/default/0.chip_plic_all_irqs_0.1608488463 Jun 02 03:44:28 PM PDT 24 Jun 02 04:04:32 PM PDT 24 5797209640 ps
T1060 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1042821641 Jun 02 04:03:38 PM PDT 24 Jun 02 04:15:26 PM PDT 24 3766985012 ps
T1061 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2601518330 Jun 02 04:06:34 PM PDT 24 Jun 02 04:16:25 PM PDT 24 7434775954 ps
T1062 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2577159794 Jun 02 04:07:54 PM PDT 24 Jun 02 05:03:24 PM PDT 24 14009743338 ps
T1063 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2462170430 Jun 02 03:46:29 PM PDT 24 Jun 02 03:56:44 PM PDT 24 3474437000 ps
T175 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3338558424 Jun 02 03:57:26 PM PDT 24 Jun 02 03:59:58 PM PDT 24 2631375344 ps
T1064 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3672143943 Jun 02 04:01:39 PM PDT 24 Jun 02 04:13:36 PM PDT 24 5036166340 ps
T200 /workspace/coverage/default/0.chip_jtag_csr_rw.3686159517 Jun 02 03:33:48 PM PDT 24 Jun 02 03:59:01 PM PDT 24 10706385144 ps
T1065 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.49273210 Jun 02 04:01:58 PM PDT 24 Jun 02 04:08:03 PM PDT 24 2653231906 ps
T202 /workspace/coverage/default/0.chip_sw_usbdev_vbus.88887626 Jun 02 03:44:34 PM PDT 24 Jun 02 03:48:48 PM PDT 24 2320521840 ps
T406 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.120531191 Jun 02 03:55:37 PM PDT 24 Jun 02 04:08:46 PM PDT 24 5044802680 ps
T1066 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3086786784 Jun 02 03:49:19 PM PDT 24 Jun 02 04:01:27 PM PDT 24 4693102200 ps
T1067 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3004394554 Jun 02 03:47:40 PM PDT 24 Jun 02 04:08:36 PM PDT 24 6132705920 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3043311111 Jun 02 03:45:26 PM PDT 24 Jun 02 05:35:56 PM PDT 24 31683401790 ps
T1068 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2866814246 Jun 02 03:49:26 PM PDT 24 Jun 02 04:46:58 PM PDT 24 13296612804 ps
T1069 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3099495557 Jun 02 03:47:54 PM PDT 24 Jun 02 03:51:51 PM PDT 24 2012538971 ps
T757 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724003566 Jun 02 04:13:01 PM PDT 24 Jun 02 04:20:35 PM PDT 24 4155908432 ps
T1070 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2775442987 Jun 02 03:45:58 PM PDT 24 Jun 02 04:06:22 PM PDT 24 6180773600 ps
T317 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4248988881 Jun 02 04:06:50 PM PDT 24 Jun 02 04:14:01 PM PDT 24 3376918280 ps
T320 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1592910711 Jun 02 04:08:05 PM PDT 24 Jun 02 04:47:07 PM PDT 24 10629394760 ps
T321 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.621455279 Jun 02 04:06:46 PM PDT 24 Jun 02 04:17:11 PM PDT 24 3462473960 ps
T322 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1637981995 Jun 02 03:59:16 PM PDT 24 Jun 02 04:17:14 PM PDT 24 10083411060 ps
T323 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130045014 Jun 02 04:11:16 PM PDT 24 Jun 02 04:17:15 PM PDT 24 3369993274 ps
T239 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1651987953 Jun 02 04:01:36 PM PDT 24 Jun 02 04:32:43 PM PDT 24 17621289790 ps
T324 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.387196279 Jun 02 04:11:51 PM PDT 24 Jun 02 04:17:43 PM PDT 24 2946394840 ps
T325 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4292995765 Jun 02 03:50:22 PM PDT 24 Jun 02 03:57:48 PM PDT 24 4539097616 ps
T326 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3457073078 Jun 02 04:04:52 PM PDT 24 Jun 02 04:20:53 PM PDT 24 5865061420 ps
T327 /workspace/coverage/default/1.chip_tap_straps_dev.4071515239 Jun 02 03:47:07 PM PDT 24 Jun 02 04:05:50 PM PDT 24 9034905062 ps
T742 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3357630389 Jun 02 04:13:39 PM PDT 24 Jun 02 04:24:04 PM PDT 24 5480571992 ps
T1071 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2655198039 Jun 02 04:00:13 PM PDT 24 Jun 02 04:26:09 PM PDT 24 7781431363 ps
T1072 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3645149378 Jun 02 03:42:10 PM PDT 24 Jun 02 04:30:23 PM PDT 24 22407605254 ps
T1073 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.501826417 Jun 02 03:59:08 PM PDT 24 Jun 02 04:07:27 PM PDT 24 4747716184 ps
T1074 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3160130889 Jun 02 03:42:00 PM PDT 24 Jun 02 04:15:59 PM PDT 24 12572011908 ps
T1075 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3064363216 Jun 02 04:04:01 PM PDT 24 Jun 02 04:11:35 PM PDT 24 5223021500 ps
T240 /workspace/coverage/default/2.chip_sw_flash_init.1551511629 Jun 02 03:55:42 PM PDT 24 Jun 02 04:35:03 PM PDT 24 23837404640 ps
T1076 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1803891702 Jun 02 04:07:20 PM PDT 24 Jun 02 05:43:01 PM PDT 24 22029541588 ps
T241 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3180722724 Jun 02 03:42:03 PM PDT 24 Jun 02 05:11:39 PM PDT 24 49679927432 ps
T1077 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3994602348 Jun 02 03:45:47 PM PDT 24 Jun 02 03:52:54 PM PDT 24 6030304766 ps
T205 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3726390168 Jun 02 03:57:54 PM PDT 24 Jun 02 04:04:12 PM PDT 24 2586849415 ps
T1078 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3928941409 Jun 02 03:57:11 PM PDT 24 Jun 02 04:04:44 PM PDT 24 6448269876 ps
T1079 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3389912475 Jun 02 03:49:02 PM PDT 24 Jun 02 04:34:42 PM PDT 24 12156209480 ps
T1080 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2766275629 Jun 02 04:02:44 PM PDT 24 Jun 02 04:10:13 PM PDT 24 6223354942 ps
T671 /workspace/coverage/default/0.rom_volatile_raw_unlock.1392860794 Jun 02 03:45:41 PM PDT 24 Jun 02 03:47:22 PM PDT 24 2133707148 ps
T1081 /workspace/coverage/default/0.chip_sw_aes_entropy.535740352 Jun 02 03:44:43 PM PDT 24 Jun 02 03:49:08 PM PDT 24 2854024744 ps
T1082 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1050443929 Jun 02 04:04:10 PM PDT 24 Jun 02 04:15:35 PM PDT 24 4703253928 ps
T1083 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2821383957 Jun 02 03:46:26 PM PDT 24 Jun 02 03:57:42 PM PDT 24 4238839330 ps
T1084 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4265714789 Jun 02 04:06:42 PM PDT 24 Jun 02 05:24:33 PM PDT 24 23371637392 ps
T784 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540908108 Jun 02 04:11:54 PM PDT 24 Jun 02 04:18:15 PM PDT 24 4033173192 ps
T1085 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2173434090 Jun 02 03:43:57 PM PDT 24 Jun 02 03:51:42 PM PDT 24 4665908646 ps
T1086 /workspace/coverage/default/1.chip_sw_kmac_idle.2335357908 Jun 02 03:44:15 PM PDT 24 Jun 02 03:48:22 PM PDT 24 2884811944 ps
T1087 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2128722719 Jun 02 03:43:24 PM PDT 24 Jun 02 03:54:21 PM PDT 24 3736278192 ps
T404 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2028024870 Jun 02 03:55:57 PM PDT 24 Jun 02 04:11:03 PM PDT 24 5076515804 ps
T42 /workspace/coverage/default/2.chip_sw_gpio.1492043693 Jun 02 03:55:46 PM PDT 24 Jun 02 04:03:42 PM PDT 24 3573533164 ps
T745 /workspace/coverage/default/47.chip_sw_all_escalation_resets.123847943 Jun 02 04:10:50 PM PDT 24 Jun 02 04:24:08 PM PDT 24 4860001514 ps
T1088 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.4248368619 Jun 02 03:46:18 PM PDT 24 Jun 02 03:54:26 PM PDT 24 5906324344 ps
T1089 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2627965592 Jun 02 03:44:45 PM PDT 24 Jun 02 03:54:13 PM PDT 24 5278987504 ps
T1090 /workspace/coverage/default/2.rom_e2e_smoke.386853359 Jun 02 04:07:05 PM PDT 24 Jun 02 05:07:01 PM PDT 24 13891345160 ps
T83 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2956014064 Jun 02 03:45:52 PM PDT 24 Jun 02 04:06:04 PM PDT 24 11155409312 ps
T804 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239261406 Jun 02 04:11:08 PM PDT 24 Jun 02 04:18:33 PM PDT 24 3709712430 ps
T1091 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3399716061 Jun 02 03:48:23 PM PDT 24 Jun 02 03:53:44 PM PDT 24 3513736689 ps
T1092 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.443839065 Jun 02 03:43:55 PM PDT 24 Jun 02 04:25:47 PM PDT 24 24145196233 ps
T1093 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3131136623 Jun 02 03:52:57 PM PDT 24 Jun 02 03:56:53 PM PDT 24 2443083893 ps
T1094 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4197849165 Jun 02 03:40:25 PM PDT 24 Jun 02 03:53:22 PM PDT 24 9766763940 ps
T766 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038506418 Jun 02 04:11:07 PM PDT 24 Jun 02 04:17:26 PM PDT 24 3857592934 ps
T780 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.678547827 Jun 02 04:04:39 PM PDT 24 Jun 02 04:12:52 PM PDT 24 3843219722 ps
T1095 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.93210799 Jun 02 03:50:14 PM PDT 24 Jun 02 04:13:15 PM PDT 24 9287000778 ps
T304 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1155107369 Jun 02 03:50:00 PM PDT 24 Jun 02 03:55:04 PM PDT 24 2989852650 ps
T1096 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194666612 Jun 02 04:11:51 PM PDT 24 Jun 02 04:19:43 PM PDT 24 3990429088 ps
T1097 /workspace/coverage/default/50.chip_sw_all_escalation_resets.2272005459 Jun 02 04:12:22 PM PDT 24 Jun 02 04:22:33 PM PDT 24 4028195488 ps
T1098 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1045391676 Jun 02 03:45:42 PM PDT 24 Jun 02 03:57:34 PM PDT 24 4872100840 ps
T1099 /workspace/coverage/default/2.chip_sw_hmac_smoketest.140183487 Jun 02 04:03:23 PM PDT 24 Jun 02 04:09:33 PM PDT 24 3358871040 ps
T1100 /workspace/coverage/default/2.chip_sw_aes_entropy.2241512815 Jun 02 04:00:01 PM PDT 24 Jun 02 04:04:59 PM PDT 24 3486885000 ps
T1101 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1964906780 Jun 02 03:56:21 PM PDT 24 Jun 02 04:02:53 PM PDT 24 3596169400 ps
T672 /workspace/coverage/default/1.rom_volatile_raw_unlock.2442000916 Jun 02 03:54:04 PM PDT 24 Jun 02 03:55:51 PM PDT 24 2564781551 ps
T1102 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1612690438 Jun 02 03:43:10 PM PDT 24 Jun 02 03:53:43 PM PDT 24 4154921802 ps
T754 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1133476542 Jun 02 04:09:04 PM PDT 24 Jun 02 04:15:22 PM PDT 24 3766441088 ps
T756 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4262084171 Jun 02 04:08:51 PM PDT 24 Jun 02 04:16:19 PM PDT 24 3976918634 ps
T1103 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2924877357 Jun 02 04:01:26 PM PDT 24 Jun 02 04:07:26 PM PDT 24 3110042556 ps
T88 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1450858103 Jun 02 04:09:17 PM PDT 24 Jun 02 04:15:52 PM PDT 24 3106373584 ps
T1104 /workspace/coverage/default/0.chip_sw_edn_auto_mode.4012384920 Jun 02 03:44:59 PM PDT 24 Jun 02 04:01:33 PM PDT 24 4066413052 ps
T1105 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2165435507 Jun 02 04:06:34 PM PDT 24 Jun 02 04:26:55 PM PDT 24 8155869301 ps
T206 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3948247371 Jun 02 03:43:19 PM PDT 24 Jun 02 04:15:50 PM PDT 24 24131114678 ps
T462 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2561794144 Jun 02 03:49:13 PM PDT 24 Jun 02 03:52:02 PM PDT 24 2766765100 ps
T774 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084366197 Jun 02 04:12:41 PM PDT 24 Jun 02 04:20:28 PM PDT 24 4181816152 ps
T1106 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3824378788 Jun 02 03:59:48 PM PDT 24 Jun 02 04:38:26 PM PDT 24 12205836249 ps
T1107 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1179810811 Jun 02 04:10:36 PM PDT 24 Jun 02 04:22:20 PM PDT 24 5991661580 ps
T1108 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2098196556 Jun 02 03:44:34 PM PDT 24 Jun 02 03:58:21 PM PDT 24 7599198726 ps
T402 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.22677397 Jun 02 03:50:35 PM PDT 24 Jun 02 03:52:44 PM PDT 24 2701039448 ps
T726 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3258585218 Jun 02 04:08:20 PM PDT 24 Jun 02 04:18:28 PM PDT 24 6297284120 ps
T1109 /workspace/coverage/default/0.chip_sw_edn_kat.3919793952 Jun 02 03:43:29 PM PDT 24 Jun 02 03:53:41 PM PDT 24 3308112904 ps
T1110 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4199810755 Jun 02 03:49:13 PM PDT 24 Jun 02 04:34:11 PM PDT 24 25438718230 ps
T1111 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1738583484 Jun 02 03:47:21 PM PDT 24 Jun 02 04:00:30 PM PDT 24 4013668302 ps
T1112 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1760502352 Jun 02 03:48:31 PM PDT 24 Jun 02 04:50:11 PM PDT 24 14059130802 ps
T762 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1449908731 Jun 02 04:10:40 PM PDT 24 Jun 02 04:16:20 PM PDT 24 4325404440 ps
T1113 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.658742463 Jun 02 04:02:47 PM PDT 24 Jun 02 04:09:29 PM PDT 24 4005071582 ps
T1114 /workspace/coverage/default/2.rom_keymgr_functest.2119673364 Jun 02 04:04:57 PM PDT 24 Jun 02 04:15:47 PM PDT 24 4303927504 ps
T471 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1099100752 Jun 02 03:44:37 PM PDT 24 Jun 02 03:53:37 PM PDT 24 3187436086 ps
T689 /workspace/coverage/default/0.chip_sw_plic_sw_irq.37615630 Jun 02 03:43:19 PM PDT 24 Jun 02 03:47:43 PM PDT 24 2552007800 ps
T242 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1969713209 Jun 02 03:46:42 PM PDT 24 Jun 02 05:07:42 PM PDT 24 51034797360 ps
T305 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.100698586 Jun 02 04:02:53 PM PDT 24 Jun 02 04:07:30 PM PDT 24 2545378187 ps
T1115 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3211715910 Jun 02 03:51:41 PM PDT 24 Jun 02 03:55:43 PM PDT 24 3058339114 ps
T1116 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1336892941 Jun 02 03:54:25 PM PDT 24 Jun 02 04:04:26 PM PDT 24 4465732984 ps
T1117 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.963353204 Jun 02 04:05:03 PM PDT 24 Jun 02 04:24:35 PM PDT 24 14191122702 ps
T1118 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3909366498 Jun 02 03:46:20 PM PDT 24 Jun 02 03:50:35 PM PDT 24 3086937340 ps
T764 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774721774 Jun 02 04:08:08 PM PDT 24 Jun 02 04:16:09 PM PDT 24 3975133370 ps
T1119 /workspace/coverage/default/2.chip_sw_csrng_smoketest.4005427542 Jun 02 04:03:36 PM PDT 24 Jun 02 04:08:03 PM PDT 24 2804145880 ps
T1120 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4058977677 Jun 02 04:01:52 PM PDT 24 Jun 02 04:10:11 PM PDT 24 4592101128 ps
T222 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2139160437 Jun 02 03:58:41 PM PDT 24 Jun 02 04:57:18 PM PDT 24 21101312878 ps
T207 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2036652113 Jun 02 03:46:36 PM PDT 24 Jun 02 03:52:37 PM PDT 24 2618577911 ps
T1121 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3369637882 Jun 02 03:49:18 PM PDT 24 Jun 02 03:53:16 PM PDT 24 2218985688 ps
T1122 /workspace/coverage/default/1.chip_sw_example_concurrency.1387975572 Jun 02 03:46:42 PM PDT 24 Jun 02 03:51:33 PM PDT 24 3429779500 ps
T768 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3482133127 Jun 02 04:07:02 PM PDT 24 Jun 02 04:17:45 PM PDT 24 5351991416 ps
T1123 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.285508403 Jun 02 03:45:37 PM PDT 24 Jun 02 03:55:04 PM PDT 24 7513497176 ps
T1124 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1517698526 Jun 02 03:44:18 PM PDT 24 Jun 02 03:52:46 PM PDT 24 3409286504 ps
T367 /workspace/coverage/default/0.chip_sw_pattgen_ios.3149441283 Jun 02 03:45:20 PM PDT 24 Jun 02 03:50:05 PM PDT 24 2482917680 ps
T1125 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2864937242 Jun 02 03:42:31 PM PDT 24 Jun 02 04:18:43 PM PDT 24 9678724944 ps
T380 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1590314525 Jun 02 04:10:25 PM PDT 24 Jun 02 04:19:12 PM PDT 24 5271988442 ps
T190 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.399373232 Jun 02 03:56:43 PM PDT 24 Jun 02 04:05:46 PM PDT 24 4006534686 ps
T421 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3953333873 Jun 02 04:02:12 PM PDT 24 Jun 02 04:09:32 PM PDT 24 4946589914 ps
T1126 /workspace/coverage/default/0.chip_sw_aes_smoketest.4059138911 Jun 02 03:46:43 PM PDT 24 Jun 02 03:50:34 PM PDT 24 3075918154 ps
T1127 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2927168567 Jun 02 03:59:12 PM PDT 24 Jun 02 04:09:21 PM PDT 24 7486552194 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1289126215 Jun 02 03:45:32 PM PDT 24 Jun 02 03:50:43 PM PDT 24 3350277572 ps
T129 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.826224826 Jun 02 03:48:20 PM PDT 24 Jun 02 03:57:53 PM PDT 24 5051937220 ps
T429 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3572833445 Jun 02 03:57:47 PM PDT 24 Jun 02 04:21:55 PM PDT 24 9451844104 ps
T277 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1752602725 Jun 02 03:43:48 PM PDT 24 Jun 02 03:56:17 PM PDT 24 5434657000 ps
T430 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.249920233 Jun 02 03:49:33 PM PDT 24 Jun 02 03:52:22 PM PDT 24 2593765128 ps
T311 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2547101099 Jun 02 03:46:54 PM PDT 24 Jun 02 04:03:29 PM PDT 24 7841219739 ps
T431 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.4221126895 Jun 02 04:05:16 PM PDT 24 Jun 02 04:17:21 PM PDT 24 4057710210 ps
T432 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2589530411 Jun 02 03:41:31 PM PDT 24 Jun 02 03:47:28 PM PDT 24 3125491432 ps
T433 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.414752966 Jun 02 04:00:51 PM PDT 24 Jun 02 04:06:06 PM PDT 24 2751321408 ps
T434 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3967804146 Jun 02 03:49:03 PM PDT 24 Jun 02 03:59:00 PM PDT 24 5256753068 ps
T1128 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1699928929 Jun 02 03:43:00 PM PDT 24 Jun 02 03:51:57 PM PDT 24 4632584920 ps
T1129 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3561497199 Jun 02 04:08:37 PM PDT 24 Jun 02 04:15:14 PM PDT 24 3859667080 ps
T727 /workspace/coverage/default/28.chip_sw_all_escalation_resets.349326720 Jun 02 04:10:22 PM PDT 24 Jun 02 04:24:00 PM PDT 24 4865345384 ps
T1130 /workspace/coverage/default/0.chip_tap_straps_dev.1532319288 Jun 02 03:43:17 PM PDT 24 Jun 02 03:48:01 PM PDT 24 3654615728 ps
T1131 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2649555190 Jun 02 04:00:08 PM PDT 24 Jun 02 04:06:06 PM PDT 24 2889965641 ps
T1132 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3899272274 Jun 02 03:57:16 PM PDT 24 Jun 02 04:01:12 PM PDT 24 2613379568 ps
T806 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.952384877 Jun 02 04:11:46 PM PDT 24 Jun 02 04:18:31 PM PDT 24 3183650456 ps
T1133 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1915322655 Jun 02 04:05:54 PM PDT 24 Jun 02 04:39:37 PM PDT 24 13824969999 ps
T698 /workspace/coverage/default/0.chip_sw_power_sleep_load.2910998436 Jun 02 03:45:07 PM PDT 24 Jun 02 03:54:11 PM PDT 24 4752336618 ps
T1134 /workspace/coverage/default/2.chip_sw_aes_masking_off.1463537443 Jun 02 03:59:02 PM PDT 24 Jun 02 04:03:11 PM PDT 24 2523346595 ps
T769 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1076969925 Jun 02 04:10:09 PM PDT 24 Jun 02 04:21:34 PM PDT 24 5686939372 ps
T1135 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2948767946 Jun 02 03:43:54 PM PDT 24 Jun 02 03:49:37 PM PDT 24 3216329300 ps
T1136 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2725524187 Jun 02 03:47:52 PM PDT 24 Jun 02 03:56:05 PM PDT 24 7753562592 ps
T1137 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2617598617 Jun 02 03:45:27 PM PDT 24 Jun 02 03:55:55 PM PDT 24 5356413600 ps
T1138 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.296186126 Jun 02 04:01:39 PM PDT 24 Jun 02 04:04:47 PM PDT 24 2537569454 ps
T243 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3945946148 Jun 02 03:48:53 PM PDT 24 Jun 02 05:15:56 PM PDT 24 49553493950 ps
T1139 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3606038144 Jun 02 03:48:01 PM PDT 24 Jun 02 04:27:09 PM PDT 24 27310644597 ps
T673 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3517933508 Jun 02 03:47:05 PM PDT 24 Jun 02 03:49:10 PM PDT 24 3309249795 ps
T1140 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.192624749 Jun 02 03:45:36 PM PDT 24 Jun 02 03:49:55 PM PDT 24 3054502862 ps
T1141 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1327890483 Jun 02 04:11:27 PM PDT 24 Jun 02 04:22:01 PM PDT 24 4760123120 ps
T1142 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.874953784 Jun 02 04:06:21 PM PDT 24 Jun 02 04:25:10 PM PDT 24 13531730693 ps
T1143 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3800236543 Jun 02 03:46:58 PM PDT 24 Jun 02 04:04:00 PM PDT 24 7163467835 ps
T790 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912614977 Jun 02 04:09:12 PM PDT 24 Jun 02 04:15:32 PM PDT 24 4453348060 ps
T1144 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3744248201 Jun 02 03:45:23 PM PDT 24 Jun 02 03:49:38 PM PDT 24 2064452814 ps
T1145 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3160373612 Jun 02 03:40:51 PM PDT 24 Jun 02 03:44:14 PM PDT 24 2521277614 ps
T1146 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3423435783 Jun 02 03:50:32 PM PDT 24 Jun 02 05:04:02 PM PDT 24 13523704036 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%