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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.84 95.42 93.64 95.49 94.45 96.47 99.58


Total test records in report: 2875
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T1147 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.271817697 Jun 02 03:58:36 PM PDT 24 Jun 02 04:04:00 PM PDT 24 2490806477 ps
T751 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1547394327 Jun 02 04:13:08 PM PDT 24 Jun 02 04:19:47 PM PDT 24 3778447128 ps
T278 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2224684613 Jun 02 03:54:01 PM PDT 24 Jun 02 04:07:08 PM PDT 24 4521363296 ps
T89 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1473204814 Jun 02 04:11:39 PM PDT 24 Jun 02 04:21:43 PM PDT 24 5857541880 ps
T1148 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1495455399 Jun 02 03:48:18 PM PDT 24 Jun 02 03:55:48 PM PDT 24 7242303640 ps
T1149 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.897465086 Jun 02 03:49:01 PM PDT 24 Jun 02 04:54:59 PM PDT 24 14450070664 ps
T1150 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.4264535284 Jun 02 03:47:06 PM PDT 24 Jun 02 06:43:06 PM PDT 24 63623794946 ps
T1151 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2062357294 Jun 02 03:45:32 PM PDT 24 Jun 02 03:56:02 PM PDT 24 4394732382 ps
T1152 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3640089583 Jun 02 04:01:55 PM PDT 24 Jun 02 04:20:47 PM PDT 24 6630239209 ps
T1153 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3746165677 Jun 02 04:15:18 PM PDT 24 Jun 02 04:26:37 PM PDT 24 5719253600 ps
T90 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2928880791 Jun 02 04:10:07 PM PDT 24 Jun 02 04:17:50 PM PDT 24 4026176320 ps
T1154 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.692483268 Jun 02 03:50:35 PM PDT 24 Jun 02 03:53:59 PM PDT 24 3295580749 ps
T1155 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1954038897 Jun 02 03:59:10 PM PDT 24 Jun 02 05:01:17 PM PDT 24 17055754776 ps
T156 /workspace/coverage/default/1.chip_plic_all_irqs_10.2499899609 Jun 02 03:49:32 PM PDT 24 Jun 02 03:59:24 PM PDT 24 4354059428 ps
T1156 /workspace/coverage/default/1.chip_sw_kmac_smoketest.38527581 Jun 02 03:52:27 PM PDT 24 Jun 02 03:58:27 PM PDT 24 2618801264 ps
T137 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.249310739 Jun 02 03:45:31 PM PDT 24 Jun 02 03:52:04 PM PDT 24 4764062194 ps
T1157 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2196532363 Jun 02 03:45:47 PM PDT 24 Jun 02 03:50:48 PM PDT 24 2602113194 ps
T265 /workspace/coverage/default/16.chip_sw_all_escalation_resets.451181274 Jun 02 04:06:29 PM PDT 24 Jun 02 04:14:39 PM PDT 24 4526764902 ps
T355 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3960346663 Jun 02 03:41:44 PM PDT 24 Jun 02 03:49:54 PM PDT 24 3546407418 ps
T1158 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2435019384 Jun 02 03:59:24 PM PDT 24 Jun 02 04:03:51 PM PDT 24 3012995184 ps
T1159 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.550796615 Jun 02 04:04:12 PM PDT 24 Jun 02 04:08:47 PM PDT 24 2051539040 ps
T91 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.78786779 Jun 02 04:06:37 PM PDT 24 Jun 02 04:13:35 PM PDT 24 4300442452 ps
T1160 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3444713301 Jun 02 04:08:56 PM PDT 24 Jun 02 04:19:05 PM PDT 24 3986901760 ps
T728 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1023183922 Jun 02 04:12:00 PM PDT 24 Jun 02 04:18:52 PM PDT 24 3712291864 ps
T266 /workspace/coverage/default/68.chip_sw_all_escalation_resets.218493408 Jun 02 04:15:09 PM PDT 24 Jun 02 04:23:49 PM PDT 24 4409698230 ps
T1161 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1947312026 Jun 02 03:52:24 PM PDT 24 Jun 02 03:56:36 PM PDT 24 2748794730 ps
T1162 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3996715438 Jun 02 04:07:34 PM PDT 24 Jun 02 04:16:42 PM PDT 24 7108073291 ps
T1163 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2321364783 Jun 02 04:02:22 PM PDT 24 Jun 02 04:33:45 PM PDT 24 8549686300 ps
T1164 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3744534450 Jun 02 03:56:56 PM PDT 24 Jun 02 04:07:28 PM PDT 24 8134088348 ps
T1165 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.733217985 Jun 02 03:58:26 PM PDT 24 Jun 02 04:14:23 PM PDT 24 6329311500 ps
T1166 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3865573252 Jun 02 03:44:45 PM PDT 24 Jun 02 03:51:35 PM PDT 24 2944215878 ps
T1167 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2299102069 Jun 02 04:01:12 PM PDT 24 Jun 02 04:13:09 PM PDT 24 4552082420 ps
T782 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1316188955 Jun 02 04:16:42 PM PDT 24 Jun 02 04:22:57 PM PDT 24 3830143750 ps
T1168 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2333882665 Jun 02 03:49:15 PM PDT 24 Jun 02 03:55:01 PM PDT 24 4655409332 ps
T1169 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.981536490 Jun 02 03:49:32 PM PDT 24 Jun 02 04:45:05 PM PDT 24 13635063558 ps
T1170 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.4190429844 Jun 02 03:45:04 PM PDT 24 Jun 02 03:56:00 PM PDT 24 4194750080 ps
T1171 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1260667004 Jun 02 03:53:34 PM PDT 24 Jun 02 05:14:05 PM PDT 24 17154880680 ps
T1172 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1648581906 Jun 02 03:42:01 PM PDT 24 Jun 02 03:48:04 PM PDT 24 5983543728 ps
T1173 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3843433762 Jun 02 03:47:08 PM PDT 24 Jun 02 03:49:42 PM PDT 24 2945681218 ps
T793 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214717858 Jun 02 04:07:26 PM PDT 24 Jun 02 04:13:55 PM PDT 24 3801015280 ps
T1174 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1134875397 Jun 02 03:55:48 PM PDT 24 Jun 02 04:07:20 PM PDT 24 4221493342 ps
T267 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.161318270 Jun 02 03:57:16 PM PDT 24 Jun 02 04:07:54 PM PDT 24 6510210302 ps
T312 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3034056480 Jun 02 04:02:32 PM PDT 24 Jun 02 04:16:38 PM PDT 24 8205177685 ps
T1175 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2633492635 Jun 02 03:55:27 PM PDT 24 Jun 02 07:12:39 PM PDT 24 64706062042 ps
T1176 /workspace/coverage/default/2.chip_sw_aes_enc.1449394857 Jun 02 03:58:12 PM PDT 24 Jun 02 04:02:53 PM PDT 24 2491854730 ps
T1177 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1306044774 Jun 02 03:56:50 PM PDT 24 Jun 02 04:13:24 PM PDT 24 5828426445 ps
T1178 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3796399436 Jun 02 04:04:21 PM PDT 24 Jun 02 04:11:51 PM PDT 24 5029885740 ps
T741 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3007148634 Jun 02 03:53:16 PM PDT 24 Jun 02 04:05:58 PM PDT 24 4882619960 ps
T1179 /workspace/coverage/default/1.chip_sw_aon_timer_irq.767050713 Jun 02 03:44:40 PM PDT 24 Jun 02 03:50:03 PM PDT 24 3994020260 ps
T1180 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2935349729 Jun 02 03:51:36 PM PDT 24 Jun 02 03:54:41 PM PDT 24 2699477152 ps
T1181 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2869822336 Jun 02 03:54:51 PM PDT 24 Jun 02 04:08:00 PM PDT 24 4072219090 ps
T1182 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3951121531 Jun 02 03:59:10 PM PDT 24 Jun 02 04:03:57 PM PDT 24 3096569816 ps
T1183 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.281790902 Jun 02 03:57:57 PM PDT 24 Jun 02 04:12:25 PM PDT 24 9986831140 ps
T130 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2223818426 Jun 02 04:04:24 PM PDT 24 Jun 02 04:16:39 PM PDT 24 7544856384 ps
T1184 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1326475091 Jun 02 04:04:54 PM PDT 24 Jun 02 04:14:08 PM PDT 24 3201100066 ps
T1185 /workspace/coverage/default/1.chip_sw_otbn_smoketest.160642565 Jun 02 03:50:54 PM PDT 24 Jun 02 04:23:38 PM PDT 24 9364463440 ps
T1186 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2066892013 Jun 02 03:57:20 PM PDT 24 Jun 02 05:21:11 PM PDT 24 46609464052 ps
T738 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2708134442 Jun 02 04:13:01 PM PDT 24 Jun 02 04:22:27 PM PDT 24 4383295930 ps
T746 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885521991 Jun 02 04:11:40 PM PDT 24 Jun 02 04:18:39 PM PDT 24 3303557146 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1861889141 Jun 02 03:45:55 PM PDT 24 Jun 02 04:06:04 PM PDT 24 6572825188 ps
T1187 /workspace/coverage/default/2.chip_sw_uart_smoketest.3768178166 Jun 02 04:04:13 PM PDT 24 Jun 02 04:08:25 PM PDT 24 2992989600 ps
T1188 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2412067749 Jun 02 04:07:48 PM PDT 24 Jun 02 04:50:18 PM PDT 24 13163194096 ps
T1189 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3848577521 Jun 02 04:03:24 PM PDT 24 Jun 02 04:12:49 PM PDT 24 5147038623 ps
T258 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1818704367 Jun 02 04:02:16 PM PDT 24 Jun 02 04:13:05 PM PDT 24 4618931494 ps
T1190 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3951188894 Jun 02 03:46:28 PM PDT 24 Jun 02 03:56:47 PM PDT 24 4949186486 ps
T1191 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1510551189 Jun 02 03:46:03 PM PDT 24 Jun 02 04:53:54 PM PDT 24 18090184190 ps
T1192 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2709118958 Jun 02 04:14:29 PM PDT 24 Jun 02 04:26:19 PM PDT 24 5733221738 ps
T1193 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1686298895 Jun 02 03:50:11 PM PDT 24 Jun 02 03:57:32 PM PDT 24 5313472840 ps
T1194 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3266118862 Jun 02 03:43:01 PM PDT 24 Jun 02 04:03:54 PM PDT 24 7828311600 ps
T14 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3941573832 Jun 02 03:44:39 PM PDT 24 Jun 02 03:49:09 PM PDT 24 3579557964 ps
T1195 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1068829623 Jun 02 04:11:08 PM PDT 24 Jun 02 04:17:51 PM PDT 24 3309116508 ps
T208 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3178783005 Jun 02 03:58:32 PM PDT 24 Jun 02 04:10:09 PM PDT 24 4715305383 ps
T1196 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3618167308 Jun 02 04:13:03 PM PDT 24 Jun 02 04:24:11 PM PDT 24 5903386254 ps
T1197 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.750876904 Jun 02 03:45:37 PM PDT 24 Jun 02 03:52:48 PM PDT 24 3462824924 ps
T1198 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093599863 Jun 02 04:05:26 PM PDT 24 Jun 02 04:12:47 PM PDT 24 4115351524 ps
T1199 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3349774161 Jun 02 03:43:59 PM PDT 24 Jun 02 03:49:18 PM PDT 24 4045675492 ps
T1200 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3463699845 Jun 02 03:47:11 PM PDT 24 Jun 02 04:05:15 PM PDT 24 5775353296 ps
T747 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336840075 Jun 02 04:11:48 PM PDT 24 Jun 02 04:17:44 PM PDT 24 3615464210 ps
T1201 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.848667986 Jun 02 04:05:48 PM PDT 24 Jun 02 04:18:24 PM PDT 24 4530421504 ps
T191 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2996999784 Jun 02 03:56:13 PM PDT 24 Jun 02 04:08:04 PM PDT 24 6280357174 ps
T1202 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1787160538 Jun 02 03:42:27 PM PDT 24 Jun 02 03:45:10 PM PDT 24 2217842744 ps
T1203 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2225851669 Jun 02 03:41:14 PM PDT 24 Jun 02 03:48:49 PM PDT 24 4449500376 ps
T743 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1298756101 Jun 02 04:13:35 PM PDT 24 Jun 02 04:23:08 PM PDT 24 4921009970 ps
T1204 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3072449833 Jun 02 03:57:18 PM PDT 24 Jun 02 05:25:19 PM PDT 24 45841161240 ps
T1205 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2730295323 Jun 02 03:51:34 PM PDT 24 Jun 02 05:37:31 PM PDT 24 22204388288 ps
T1206 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1333707838 Jun 02 04:07:50 PM PDT 24 Jun 02 04:18:29 PM PDT 24 5470009794 ps
T209 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.440108875 Jun 02 03:49:37 PM PDT 24 Jun 02 03:59:15 PM PDT 24 3999587199 ps
T1207 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3821891856 Jun 02 03:50:57 PM PDT 24 Jun 02 04:04:21 PM PDT 24 4669022105 ps
T463 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3278957461 Jun 02 04:03:15 PM PDT 24 Jun 02 04:07:37 PM PDT 24 2671548080 ps
T1208 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1293372214 Jun 02 04:09:27 PM PDT 24 Jun 02 04:17:01 PM PDT 24 3974662820 ps
T1209 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.462931944 Jun 02 03:55:45 PM PDT 24 Jun 02 04:08:19 PM PDT 24 4581123258 ps
T775 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860103138 Jun 02 04:12:55 PM PDT 24 Jun 02 04:20:25 PM PDT 24 4284163266 ps
T1210 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2241759114 Jun 02 04:00:06 PM PDT 24 Jun 02 04:08:49 PM PDT 24 5656373020 ps
T201 /workspace/coverage/default/2.chip_jtag_mem_access.654208068 Jun 02 03:53:42 PM PDT 24 Jun 02 04:18:22 PM PDT 24 14053848785 ps
T1211 /workspace/coverage/default/2.chip_sw_edn_auto_mode.3859247129 Jun 02 03:58:53 PM PDT 24 Jun 02 04:23:14 PM PDT 24 4474736770 ps
T1212 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3311130134 Jun 02 03:55:03 PM PDT 24 Jun 02 04:07:47 PM PDT 24 3534869076 ps
T1213 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4088852987 Jun 02 04:00:35 PM PDT 24 Jun 02 07:32:48 PM PDT 24 255408852840 ps
T1214 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1506466991 Jun 02 04:04:05 PM PDT 24 Jun 02 04:15:23 PM PDT 24 4201583160 ps
T1215 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2600493944 Jun 02 03:44:38 PM PDT 24 Jun 02 04:32:32 PM PDT 24 12580585496 ps
T1216 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3750883705 Jun 02 04:03:30 PM PDT 24 Jun 02 04:23:57 PM PDT 24 8799626988 ps
T420 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1600086672 Jun 02 03:49:08 PM PDT 24 Jun 02 03:56:24 PM PDT 24 3439812344 ps
T1217 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2900156597 Jun 02 03:48:48 PM PDT 24 Jun 02 03:53:32 PM PDT 24 3435073073 ps
T251 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2549077102 Jun 02 04:05:58 PM PDT 24 Jun 02 04:11:30 PM PDT 24 3134033856 ps
T385 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2160864892 Jun 02 04:01:10 PM PDT 24 Jun 02 04:09:27 PM PDT 24 5639427000 ps
T740 /workspace/coverage/default/73.chip_sw_all_escalation_resets.627336024 Jun 02 04:11:58 PM PDT 24 Jun 02 04:21:21 PM PDT 24 5757236894 ps
T1218 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2239203680 Jun 02 04:03:50 PM PDT 24 Jun 02 04:20:49 PM PDT 24 5481198340 ps
T268 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1871730388 Jun 02 03:46:51 PM PDT 24 Jun 02 03:54:49 PM PDT 24 4399723930 ps
T1219 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1912369412 Jun 02 03:49:15 PM PDT 24 Jun 02 03:57:26 PM PDT 24 3747261460 ps
T318 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2083789278 Jun 02 04:13:16 PM PDT 24 Jun 02 04:23:42 PM PDT 24 4778996320 ps
T1220 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.815237228 Jun 02 03:50:18 PM PDT 24 Jun 02 04:52:22 PM PDT 24 14207652880 ps
T319 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935912925 Jun 02 04:12:32 PM PDT 24 Jun 02 04:19:22 PM PDT 24 3311942262 ps
T1221 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.759004462 Jun 02 03:57:38 PM PDT 24 Jun 02 04:32:29 PM PDT 24 11887368188 ps
T688 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.839338521 Jun 02 03:45:30 PM PDT 24 Jun 02 03:50:12 PM PDT 24 2640357694 ps
T1222 /workspace/coverage/default/1.chip_sw_example_rom.2918372904 Jun 02 03:47:56 PM PDT 24 Jun 02 03:50:05 PM PDT 24 2231506194 ps
T1223 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2708319664 Jun 02 04:03:12 PM PDT 24 Jun 02 04:14:14 PM PDT 24 5552394888 ps
T422 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1021967285 Jun 02 03:42:20 PM PDT 24 Jun 02 03:49:32 PM PDT 24 7618397760 ps
T1224 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3178516465 Jun 02 04:05:39 PM PDT 24 Jun 02 04:20:37 PM PDT 24 11531843882 ps
T55 /workspace/coverage/default/1.chip_sw_spi_device_tpm.2050649627 Jun 02 03:45:31 PM PDT 24 Jun 02 03:51:54 PM PDT 24 3125659492 ps
T1225 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1352024481 Jun 02 03:47:33 PM PDT 24 Jun 02 05:21:03 PM PDT 24 21604717963 ps
T783 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1331345175 Jun 02 04:06:59 PM PDT 24 Jun 02 04:17:10 PM PDT 24 4255970672 ps
T1226 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3400737153 Jun 02 04:12:42 PM PDT 24 Jun 02 04:18:21 PM PDT 24 3870891144 ps
T1227 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.355394175 Jun 02 03:58:53 PM PDT 24 Jun 02 04:53:51 PM PDT 24 14352481962 ps
T749 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2218905201 Jun 02 04:14:29 PM PDT 24 Jun 02 04:23:28 PM PDT 24 5710671548 ps
T1228 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.146422014 Jun 02 03:43:39 PM PDT 24 Jun 02 03:45:34 PM PDT 24 1724094139 ps
T1229 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3157163042 Jun 02 03:50:59 PM PDT 24 Jun 02 04:47:24 PM PDT 24 13800278224 ps
T1230 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1841545091 Jun 02 04:02:13 PM PDT 24 Jun 02 04:17:07 PM PDT 24 6078340654 ps
T1231 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3414076270 Jun 02 03:48:52 PM PDT 24 Jun 02 04:54:45 PM PDT 24 14618090200 ps
T203 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1778771691 Jun 02 03:40:13 PM PDT 24 Jun 02 04:08:37 PM PDT 24 7905890292 ps
T1232 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3581620231 Jun 02 03:41:51 PM PDT 24 Jun 02 03:59:19 PM PDT 24 8367792580 ps
T1233 /workspace/coverage/default/2.rom_volatile_raw_unlock.4053486045 Jun 02 04:03:00 PM PDT 24 Jun 02 04:04:40 PM PDT 24 2212363742 ps
T359 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1308684345 Jun 02 04:02:38 PM PDT 24 Jun 02 04:06:50 PM PDT 24 2463620734 ps
T1234 /workspace/coverage/default/3.chip_tap_straps_dev.1268181572 Jun 02 04:05:39 PM PDT 24 Jun 02 04:08:56 PM PDT 24 2884892162 ps
T1235 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2714587650 Jun 02 04:05:26 PM PDT 24 Jun 02 04:16:07 PM PDT 24 6116477364 ps
T1236 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3602242043 Jun 02 03:42:10 PM PDT 24 Jun 02 06:59:32 PM PDT 24 64424074540 ps
T1237 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2490698955 Jun 02 03:48:56 PM PDT 24 Jun 02 04:58:57 PM PDT 24 16228469598 ps
T1238 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1992498083 Jun 02 03:48:38 PM PDT 24 Jun 02 03:58:15 PM PDT 24 4295673900 ps
T1239 /workspace/coverage/default/0.chip_tap_straps_prod.2696915700 Jun 02 03:46:11 PM PDT 24 Jun 02 04:17:22 PM PDT 24 16523075019 ps
T1240 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.24698648 Jun 02 03:56:59 PM PDT 24 Jun 02 04:14:50 PM PDT 24 6241923278 ps
T1241 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2385310304 Jun 02 03:50:46 PM PDT 24 Jun 02 03:55:21 PM PDT 24 2632880734 ps
T1242 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3259893787 Jun 02 03:46:28 PM PDT 24 Jun 02 04:02:01 PM PDT 24 9244547500 ps
T1243 /workspace/coverage/default/0.chip_sw_aes_enc.2730474647 Jun 02 03:47:57 PM PDT 24 Jun 02 03:51:58 PM PDT 24 2752359182 ps
T1244 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3051354664 Jun 02 03:46:17 PM PDT 24 Jun 02 04:12:10 PM PDT 24 11757196408 ps
T464 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.429008744 Jun 02 03:48:58 PM PDT 24 Jun 02 03:58:38 PM PDT 24 8762897951 ps
T1245 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1908160936 Jun 02 04:11:36 PM PDT 24 Jun 02 04:22:33 PM PDT 24 5124994704 ps
T1246 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4266056953 Jun 02 03:46:18 PM PDT 24 Jun 02 03:52:58 PM PDT 24 4866601373 ps
T1247 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1960770604 Jun 02 03:46:48 PM PDT 24 Jun 02 03:54:25 PM PDT 24 4646953196 ps
T1248 /workspace/coverage/default/4.chip_tap_straps_dev.2281515543 Jun 02 04:05:43 PM PDT 24 Jun 02 04:09:39 PM PDT 24 3010821839 ps
T1249 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1466228735 Jun 02 04:00:41 PM PDT 24 Jun 02 04:11:24 PM PDT 24 4388503018 ps
T1250 /workspace/coverage/default/2.chip_tap_straps_rma.2406576817 Jun 02 04:01:54 PM PDT 24 Jun 02 04:10:34 PM PDT 24 5706470414 ps
T1251 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4261992393 Jun 02 03:44:07 PM PDT 24 Jun 02 03:46:12 PM PDT 24 2872053764 ps
T1252 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1988102767 Jun 02 03:45:30 PM PDT 24 Jun 02 03:50:09 PM PDT 24 3170848593 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2221301019 Jun 02 04:00:28 PM PDT 24 Jun 02 04:22:52 PM PDT 24 7501470280 ps
T1253 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.376034014 Jun 02 03:49:28 PM PDT 24 Jun 02 04:01:36 PM PDT 24 5194284903 ps
T1254 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2171909543 Jun 02 04:05:14 PM PDT 24 Jun 02 04:24:18 PM PDT 24 7769959380 ps
T1255 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3723954707 Jun 02 03:47:35 PM PDT 24 Jun 02 04:11:08 PM PDT 24 14539288130 ps
T1256 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2947313569 Jun 02 03:41:00 PM PDT 24 Jun 02 03:44:45 PM PDT 24 2913557440 ps
T375 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3341618020 Jun 02 03:42:38 PM PDT 24 Jun 02 03:49:03 PM PDT 24 4250019080 ps
T1257 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1107614471 Jun 02 04:02:36 PM PDT 24 Jun 02 04:14:11 PM PDT 24 4345455190 ps
T1258 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.690051854 Jun 02 03:56:02 PM PDT 24 Jun 02 04:03:46 PM PDT 24 3803699905 ps
T1259 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1046397765 Jun 02 03:47:51 PM PDT 24 Jun 02 03:55:48 PM PDT 24 3702755764 ps
T1260 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1844726631 Jun 02 04:02:35 PM PDT 24 Jun 02 04:07:50 PM PDT 24 2521408313 ps
T805 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1517507626 Jun 02 04:09:03 PM PDT 24 Jun 02 04:17:18 PM PDT 24 3943826890 ps
T1261 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3246515947 Jun 02 04:04:41 PM PDT 24 Jun 02 04:09:19 PM PDT 24 2623280272 ps
T1262 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.964976370 Jun 02 04:06:21 PM PDT 24 Jun 02 04:15:30 PM PDT 24 3911025866 ps
T1263 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.767695035 Jun 02 03:48:33 PM PDT 24 Jun 02 03:54:07 PM PDT 24 3814667715 ps
T1264 /workspace/coverage/default/0.chip_sw_flash_crash_alert.561652890 Jun 02 03:49:05 PM PDT 24 Jun 02 04:02:30 PM PDT 24 5163480088 ps
T8 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3423675974 Jun 02 03:51:02 PM PDT 24 Jun 02 03:58:04 PM PDT 24 3887639232 ps
T701 /workspace/coverage/default/2.chip_sw_example_rom.3233751292 Jun 02 03:52:21 PM PDT 24 Jun 02 03:54:13 PM PDT 24 2526425400 ps
T386 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.716244293 Jun 02 03:47:38 PM PDT 24 Jun 02 03:54:11 PM PDT 24 6039079520 ps
T702 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.44360245 Jun 02 03:53:50 PM PDT 24 Jun 02 04:15:04 PM PDT 24 5785538150 ps
T703 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2991446004 Jun 02 03:44:58 PM PDT 24 Jun 02 04:05:52 PM PDT 24 8905890188 ps
T704 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2329821520 Jun 02 03:45:51 PM PDT 24 Jun 02 04:12:03 PM PDT 24 10867817294 ps
T472 /workspace/coverage/default/2.chip_sw_edn_boot_mode.290305100 Jun 02 03:58:30 PM PDT 24 Jun 02 04:08:29 PM PDT 24 3039959038 ps
T705 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3048109222 Jun 02 04:01:53 PM PDT 24 Jun 02 04:06:46 PM PDT 24 3496997746 ps
T706 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2347930650 Jun 02 03:51:11 PM PDT 24 Jun 02 04:41:01 PM PDT 24 10868330584 ps
T707 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2697679089 Jun 02 03:43:35 PM PDT 24 Jun 02 03:54:27 PM PDT 24 4540699176 ps
T1265 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3247476708 Jun 02 03:45:55 PM PDT 24 Jun 02 03:57:27 PM PDT 24 4667787984 ps
T1266 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.931233705 Jun 02 03:45:17 PM PDT 24 Jun 02 04:16:50 PM PDT 24 12294620032 ps
T141 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.803235082 Jun 02 03:48:53 PM PDT 24 Jun 02 04:33:26 PM PDT 24 17520477178 ps
T1267 /workspace/coverage/default/0.chip_sw_example_manufacturer.3278381961 Jun 02 03:48:48 PM PDT 24 Jun 02 03:54:26 PM PDT 24 2707709460 ps
T408 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1962679892 Jun 02 03:44:32 PM PDT 24 Jun 02 03:58:10 PM PDT 24 4884743384 ps
T17 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2698204192 Jun 02 04:02:02 PM PDT 24 Jun 02 04:34:28 PM PDT 24 18670348676 ps
T1268 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.209261579 Jun 02 03:56:28 PM PDT 24 Jun 02 04:08:13 PM PDT 24 4823471700 ps
T1269 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1697776852 Jun 02 04:12:58 PM PDT 24 Jun 02 04:23:18 PM PDT 24 4854336992 ps
T1270 /workspace/coverage/default/2.chip_sival_flash_info_access.1808468616 Jun 02 03:53:42 PM PDT 24 Jun 02 03:59:12 PM PDT 24 2796132582 ps
T1271 /workspace/coverage/default/1.rom_e2e_shutdown_output.471782031 Jun 02 03:53:16 PM PDT 24 Jun 02 04:45:56 PM PDT 24 25271783304 ps
T465 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3488669247 Jun 02 03:59:39 PM PDT 24 Jun 02 04:09:37 PM PDT 24 8868736149 ps
T1272 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1906036945 Jun 02 03:46:16 PM PDT 24 Jun 02 03:55:09 PM PDT 24 5921825816 ps
T785 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2104253004 Jun 02 04:06:24 PM PDT 24 Jun 02 04:16:27 PM PDT 24 3905096382 ps
T234 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2764939677 Jun 02 03:46:45 PM PDT 24 Jun 02 04:48:42 PM PDT 24 12733510820 ps
T1273 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.4251783482 Jun 02 03:44:28 PM PDT 24 Jun 02 03:54:23 PM PDT 24 4263163024 ps
T1274 /workspace/coverage/default/1.chip_sw_aes_smoketest.3527924868 Jun 02 03:51:25 PM PDT 24 Jun 02 03:55:12 PM PDT 24 2372779800 ps
T1275 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.588885937 Jun 02 03:42:40 PM PDT 24 Jun 02 03:47:12 PM PDT 24 2687646484 ps
T1276 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2991598138 Jun 02 03:45:25 PM PDT 24 Jun 02 04:09:12 PM PDT 24 10613289558 ps
T313 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.333100968 Jun 02 03:45:25 PM PDT 24 Jun 02 04:03:09 PM PDT 24 9994919007 ps
T162 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3480363797 Jun 02 03:44:09 PM PDT 24 Jun 02 03:46:03 PM PDT 24 1724224416 ps
T1277 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1533638304 Jun 02 04:00:47 PM PDT 24 Jun 02 04:06:44 PM PDT 24 3062478770 ps
T716 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3418490160 Jun 02 04:13:19 PM PDT 24 Jun 02 04:25:52 PM PDT 24 5916283360 ps
T1278 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4257333323 Jun 02 03:47:03 PM PDT 24 Jun 02 05:35:08 PM PDT 24 22062786824 ps
T1279 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3160056657 Jun 02 03:42:25 PM PDT 24 Jun 02 04:11:53 PM PDT 24 16516098441 ps
T801 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3908901348 Jun 02 04:06:30 PM PDT 24 Jun 02 04:18:18 PM PDT 24 5117837052 ps
T1280 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4030737885 Jun 02 03:58:16 PM PDT 24 Jun 02 04:35:04 PM PDT 24 17625185092 ps
T1281 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2004898726 Jun 02 04:11:05 PM PDT 24 Jun 02 04:20:52 PM PDT 24 4393190880 ps
T1282 /workspace/coverage/default/0.chip_sw_power_idle_load.2100722386 Jun 02 03:42:34 PM PDT 24 Jun 02 03:52:46 PM PDT 24 4100551484 ps
T758 /workspace/coverage/default/84.chip_sw_all_escalation_resets.4192263661 Jun 02 04:12:51 PM PDT 24 Jun 02 04:26:10 PM PDT 24 4640238264 ps
T1283 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4015596906 Jun 02 04:06:16 PM PDT 24 Jun 02 04:40:50 PM PDT 24 8844413080 ps
T1284 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3243005579 Jun 02 03:44:50 PM PDT 24 Jun 02 03:48:25 PM PDT 24 2874186051 ps
T1285 /workspace/coverage/default/1.chip_sw_example_flash.2150600937 Jun 02 03:44:32 PM PDT 24 Jun 02 03:47:40 PM PDT 24 1952087750 ps
T1286 /workspace/coverage/default/3.chip_tap_straps_testunlock0.1156060611 Jun 02 04:03:02 PM PDT 24 Jun 02 04:07:45 PM PDT 24 3174872693 ps
T259 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2586221798 Jun 02 03:48:38 PM PDT 24 Jun 02 03:55:48 PM PDT 24 4426621444 ps
T1287 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1477097705 Jun 02 03:53:26 PM PDT 24 Jun 02 03:58:13 PM PDT 24 4392969380 ps
T1288 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.491126231 Jun 02 03:44:29 PM PDT 24 Jun 02 03:53:32 PM PDT 24 4542769890 ps
T1289 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3981808545 Jun 02 03:46:40 PM PDT 24 Jun 02 03:49:06 PM PDT 24 3158459530 ps
T1290 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2239321144 Jun 02 03:45:01 PM PDT 24 Jun 02 03:51:25 PM PDT 24 3491563408 ps
T1291 /workspace/coverage/default/0.chip_sw_example_concurrency.1610225490 Jun 02 03:44:57 PM PDT 24 Jun 02 03:48:08 PM PDT 24 2381765806 ps
T1292 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4132843032 Jun 02 04:06:28 PM PDT 24 Jun 02 06:07:13 PM PDT 24 35955112444 ps
T1293 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.871254353 Jun 02 03:41:54 PM PDT 24 Jun 02 03:52:08 PM PDT 24 9316499873 ps
T1294 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2283971909 Jun 02 03:49:40 PM PDT 24 Jun 02 04:54:09 PM PDT 24 14052094460 ps
T1295 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.492123914 Jun 02 04:05:14 PM PDT 24 Jun 02 04:17:39 PM PDT 24 4057685804 ps
T717 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2218346957 Jun 02 04:08:00 PM PDT 24 Jun 02 04:19:18 PM PDT 24 6116477196 ps
T1296 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3949161104 Jun 02 04:09:01 PM PDT 24 Jun 02 04:20:13 PM PDT 24 5652559880 ps
T1297 /workspace/coverage/default/0.chip_sw_aes_masking_off.2401099863 Jun 02 03:49:10 PM PDT 24 Jun 02 03:54:27 PM PDT 24 3390195732 ps
T1298 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366346425 Jun 02 04:08:36 PM PDT 24 Jun 02 04:14:56 PM PDT 24 3951018830 ps
T709 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3968128671 Jun 02 03:58:49 PM PDT 24 Jun 02 04:11:10 PM PDT 24 5147277324 ps
T153 /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1423157641 Jun 02 04:15:38 PM PDT 24 Jun 02 04:15:46 PM PDT 24 66797299 ps
T76 /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.144631188 Jun 02 04:20:18 PM PDT 24 Jun 02 04:34:15 PM PDT 24 45350355196 ps
T77 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2501599497 Jun 02 04:16:26 PM PDT 24 Jun 02 04:22:38 PM PDT 24 2784178292 ps
T78 /workspace/coverage/cover_reg_top/17.xbar_smoke.788149777 Jun 02 04:15:31 PM PDT 24 Jun 02 04:15:40 PM PDT 24 130740266 ps
T79 /workspace/coverage/cover_reg_top/89.xbar_random.2311137559 Jun 02 04:27:54 PM PDT 24 Jun 02 04:29:04 PM PDT 24 1718959894 ps
T473 /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1624694722 Jun 02 04:13:08 PM PDT 24 Jun 02 04:13:53 PM PDT 24 881073636 ps
T252 /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2839049625 Jun 02 04:20:07 PM PDT 24 Jun 02 04:20:38 PM PDT 24 696504813 ps
T474 /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.3970236486 Jun 02 04:16:22 PM PDT 24 Jun 02 04:16:42 PM PDT 24 413474350 ps
T444 /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2548647461 Jun 02 04:12:12 PM PDT 24 Jun 02 04:26:11 PM PDT 24 47005849788 ps
T445 /workspace/coverage/cover_reg_top/16.xbar_same_source.3325458716 Jun 02 04:15:21 PM PDT 24 Jun 02 04:16:05 PM PDT 24 1296999044 ps
T550 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1023169526 Jun 02 04:25:27 PM PDT 24 Jun 02 04:25:42 PM PDT 24 134322820 ps
T456 /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3594022426 Jun 02 04:19:24 PM PDT 24 Jun 02 04:32:19 PM PDT 24 67491160783 ps
T435 /workspace/coverage/cover_reg_top/60.xbar_stress_all.3176035588 Jun 02 04:23:46 PM PDT 24 Jun 02 04:26:25 PM PDT 24 1562430761 ps
T822 /workspace/coverage/cover_reg_top/77.xbar_access_same_device.545627262 Jun 02 04:26:14 PM PDT 24 Jun 02 04:26:29 PM PDT 24 311278975 ps
T146 /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1379650377 Jun 02 04:09:26 PM PDT 24 Jun 02 05:24:08 PM PDT 24 43893829125 ps
T549 /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.4075599928 Jun 02 04:27:53 PM PDT 24 Jun 02 04:28:09 PM PDT 24 111364100 ps
T546 /workspace/coverage/cover_reg_top/16.chip_tl_errors.3894936363 Jun 02 04:15:13 PM PDT 24 Jun 02 04:20:15 PM PDT 24 3780524871 ps
T446 /workspace/coverage/cover_reg_top/20.xbar_same_source.161873697 Jun 02 04:16:35 PM PDT 24 Jun 02 04:16:55 PM PDT 24 575716726 ps
T660 /workspace/coverage/cover_reg_top/89.xbar_error_random.539967746 Jun 02 04:27:52 PM PDT 24 Jun 02 04:27:59 PM PDT 24 36561768 ps
T548 /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2873886503 Jun 02 04:20:51 PM PDT 24 Jun 02 04:22:56 PM PDT 24 10337840390 ps
T552 /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.2856201428 Jun 02 04:26:01 PM PDT 24 Jun 02 04:27:05 PM PDT 24 3583459870 ps
T501 /workspace/coverage/cover_reg_top/37.xbar_stress_all.454304056 Jun 02 04:20:07 PM PDT 24 Jun 02 04:22:04 PM PDT 24 1180043926 ps
T677 /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4279710329 Jun 02 04:07:45 PM PDT 24 Jun 02 04:34:33 PM PDT 24 90596966821 ps
T443 /workspace/coverage/cover_reg_top/81.xbar_random.2545505157 Jun 02 04:26:50 PM PDT 24 Jun 02 04:27:46 PM PDT 24 1423219556 ps
T392 /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.77353021 Jun 02 04:10:58 PM PDT 24 Jun 02 05:06:06 PM PDT 24 29432936380 ps
T553 /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.258118764 Jun 02 04:15:56 PM PDT 24 Jun 02 04:16:10 PM PDT 24 89876364 ps
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