Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.06			85.06

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	84.88			84.88
tb.dut.top_earlgrey.u_i2c1	84.97			84.97
tb.dut.top_earlgrey.u_i2c2	84.97			84.97

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.88			84.88

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.88			84.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.97			84.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.97			84.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.97			84.97

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.97			84.97

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	348	296	85.06
Total Bits 0->1	174	148	85.06
Total Bits 1->0	174	148	85.06

Ports	52	40	76.92
Port Bits	348	296	85.06
Port Bits 0->1	174	148	85.06
Port Bits 1->0	174	148	85.06

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T123,T206,T207	Yes	T123,T206,T207	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T123,T206,T207	Yes	T123,T206,T207	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	INPUT
tl_o.a_ready	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T206,T207	Yes	T123,T206,T207	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T123,*T132,*T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T123,*T206,*T207	Yes	T123,T206,T207	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T209	Yes	T72,T115,T210	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T210	Yes	T72,T115,T209	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_scl_i	Yes	Yes	T206,T207,T211	Yes	T206,T207,T211	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T206,T211,T212	Yes	T206,T211,T212	OUTPUT
cio_sda_i	Yes	Yes	T206,T207,T211	Yes	T206,T207,T211	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T206,T207,T211	Yes	T206,T207,T211	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T123,T206,T211	Yes	T123,T206,T211	OUTPUT
intr_rx_threshold_o	Yes	Yes	T123,T206,T211	Yes	T123,T206,T211	OUTPUT
intr_acq_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_controller_halt_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_scl_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_unstable_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_cmd_complete_o	Yes	Yes	T123,T206,T207	Yes	T123,T206,T207	OUTPUT
intr_tx_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_tx_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_acq_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_unexp_stop_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_host_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	344	292	84.88
Total Bits 0->1	172	146	84.88
Total Bits 1->0	172	146	84.88

Ports	52	40	76.92
Port Bits	344	292	84.88
Port Bits 0->1	172	146	84.88
Port Bits 1->0	172	146	84.88

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T123,T207,T212	Yes	T123,T207,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T123,T207,T212	Yes	T123,T207,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	INPUT
tl_o.a_ready	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T207,T212	Yes	T123,T207,T212	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T123,*T132,*T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T123,*T207,*T212	Yes	T123,T207,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T210	Yes	T72,T115,T210	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T210	Yes	T72,T115,T210	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_scl_i	Yes	Yes	T207,T212,T213	Yes	T207,T212,T213	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
cio_sda_i	Yes	Yes	T207,T212,T213	Yes	T207,T212,T213	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T207,T212,T213	Yes	T207,T212,T213	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T123,T212,T200	Yes	T123,T212,T200	OUTPUT
intr_rx_threshold_o	Yes	Yes	T123,T212,T200	Yes	T123,T212,T200	OUTPUT
intr_acq_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_controller_halt_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_scl_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_unstable_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_cmd_complete_o	Yes	Yes	T123,T207,T212	Yes	T123,T207,T212	OUTPUT
intr_tx_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_tx_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_acq_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_unexp_stop_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_host_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	294	84.97
Total Bits 0->1	173	147	84.97
Total Bits 1->0	173	147	84.97

Ports	52	40	76.92
Port Bits	346	294	84.97
Port Bits 0->1	173	147	84.97
Port Bits 1->0	173	147	84.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	INPUT
tl_o.a_ready	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T123,*T153,*T211	Yes	T6,T123,T108	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T123,*T211,*T200	Yes	T123,T211,T200	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T210	Yes	T72,T115,T210	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T210	Yes	T72,T115,T210	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_scl_i	Yes	Yes	T211,T215,T216	Yes	T211,T215,T216	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T211,T215,T216	Yes	T211,T215,T216	OUTPUT
cio_sda_i	Yes	Yes	T211,T215,T216	Yes	T211,T215,T216	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T211,T215,T216	Yes	T211,T215,T216	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	OUTPUT
intr_rx_threshold_o	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	OUTPUT
intr_acq_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_controller_halt_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_scl_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_unstable_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_cmd_complete_o	Yes	Yes	T123,T211,T200	Yes	T123,T211,T200	OUTPUT
intr_tx_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_tx_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_acq_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_unexp_stop_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_host_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	52	40	76.92
Total Bits	346	294	84.97
Total Bits 0->1	173	147	84.97
Total Bits 1->0	173	147	84.97

Ports	52	40	76.92
Port Bits	346	294	84.97
Port Bits 0->1	173	147	84.97
Port Bits 1->0	173	147	84.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	INPUT
tl_o.a_ready	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T123,T132,T153	Yes	T6,T123,T132	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T123,*T153,*T206	Yes	T6,T123,T108	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T208	Yes	T6,T123,T132	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T123,*T206,*T200	Yes	T123,T206,T200	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T123,T132	Yes	T6,T123,T132	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T209	Yes	T72,T115,T210	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T210	Yes	T72,T115,T209	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_scl_i	Yes	Yes	T206,T217,T218	Yes	T206,T217,T218	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T206,T217,T218	Yes	T206,T217,T218	OUTPUT
cio_sda_i	Yes	Yes	T206,T217,T218	Yes	T206,T217,T218	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T206,T217,T218	Yes	T206,T217,T218	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	OUTPUT
intr_rx_threshold_o	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	OUTPUT
intr_acq_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_rx_overflow_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_controller_halt_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_scl_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_interference_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_sda_unstable_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_cmd_complete_o	Yes	Yes	T123,T206,T200	Yes	T123,T206,T200	OUTPUT
intr_tx_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_tx_threshold_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_acq_stretch_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_unexp_stop_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT
intr_host_timeout_o	Yes	Yes	T123,T200,T201	Yes	T123,T200,T201	OUTPUT

*Tests covering at least one bit in the range