Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.14			94.14

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main	93.99			93.99
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	94.72			94.72

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.99			93.99

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.99			93.99

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.72			94.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.72			94.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	64	45	70.31
Total Bits	1160	1092	94.14
Total Bits 0->1	580	546	94.14
Total Bits 1->0	580	546	94.14

Ports	64	45	70.31
Port Bits	1160	1092	94.14
Port Bits 0->1	580	546	94.14
Port Bits 1->0	580	546	94.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T6,*T57,*T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_o.a_ready	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	T75,*T170,T172	Yes	T75,T170,T172	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T21,*T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,*T21,*T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T75,T21,T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T64,*T75,*T21	Yes	T64,T57,T58	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T75,T21,T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T170,*T172	Yes	T75,T169,T170	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T169	Yes	T6,T72,T169	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T169	Yes	T6,T72,T169	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	INPUT
sram_otp_key_o.req	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T57,T44	Yes	T5,T6,T17	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T5,T57,T43	INPUT
sram_otp_key_i.ack	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	60	40	66.67
Total Bits	1132	1064	93.99
Total Bits 0->1	566	532	93.99
Total Bits 1->0	566	532	93.99

Ports	60	40	66.67
Port Bits	1132	1064	93.99
Port Bits 0->1	566	532	93.99
Port Bits 1->0	566	532	93.99

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_source[5]	No	No		No		INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[0]	No	No		No		INPUT
ram_tl_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T6,T57,T43	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_user.cmd_intg[0]	Yes	Yes	*T6,*T57,*T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T75,T169,T170	Yes	T75,T169,T170	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T6,*T57,*T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[4:2]	Yes	Yes	*T57,*T58,*T59	Yes	T57,T58,T59	INPUT
regs_tl_i.a_address[5]	No	No		No		INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T6,*T57,*T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T6,*T57,*T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[1:0]	Yes	Yes	*T64,*T57,*T58	Yes	T64,T57,T58	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T75,T169,T170	Yes	T75,T169,T170	INPUT
regs_tl_i.a_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_o.a_ready	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T170,*T171,*T64	Yes	T170,T171,T64	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T21,*T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T75,*T21,*T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T75,T21,T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T64,*T75,*T21	Yes	T64,T57,T58	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T75,T21,T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T170,*T172	Yes	T75,T169,T170	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T169	Yes	T6,T72,T169	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T169	Yes	T6,T72,T169	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	INPUT
sram_otp_key_o.req	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T57,T44	Yes	T5,T6,T17	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T5,T57,T43	INPUT
sram_otp_key_i.ack	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	58	42	72.41
Total Bits	1098	1040	94.72
Total Bits 0->1	549	520	94.72
Total Bits 1->0	549	520	94.72

Ports	58	42	72.41
Port Bits	1098	1040	94.72
Port Bits 0->1	549	520	94.72
Port Bits 1->0	549	520	94.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T57,T43	Yes	T4,T57,T43	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
ram_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[11:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T57,T43	Yes	T4,T57,T43	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T57,T43	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T57,T43	Yes	T4,T57,T43	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[1:0]	Yes	Yes	*T65,*T66,*T167	Yes	T65,T66,T167	OUTPUT
ram_tl_o.d_source[5:2]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	INPUT
regs_tl_o.a_ready	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T75,*T172,*T189	Yes	T75,T172,T189	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T75,T21,*T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T21,*T55,*T56	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T75,T21,T55	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T64,*T75,*T275	Yes	T64,T75,T275	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T21,T55,T56	Yes	T6,T57,T58	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T75,*T172,*T189	Yes	T75,T172,T318	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T6,T57,T58	Yes	T6,T57,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T75,T172,T189	Yes	T75,T172,T189	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T57,T44	Yes	T5,T6,T17	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T5,T57,T43	INPUT
sram_otp_key_i.ack	Yes	Yes	T75,T172,T189	Yes	T75,T172,T189	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range