Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.07			90.07
tb.dut.top_earlgrey.u_uart1	90.13			90.13
tb.dut.top_earlgrey.u_uart2	90.13			90.13
tb.dut.top_earlgrey.u_uart3	90.20			90.20

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.07			90.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T57,T124,T58	Yes	T57,T124,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T57,T124,T58	Yes	T57,T124,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	INPUT
tl_o.a_ready	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T124,T104,T21	Yes	T124,T104,T21	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T124,T104,T21	Yes	T6,T57,T124	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T21,*T132,T152	Yes	T6,T57,T124	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T124,T104,T21	Yes	T6,T57,T124	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T154,*T57,*T124	Yes	T154,T57,T124	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T21,T132,T152	Yes	T6,T57,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T124,*T104,*T21	Yes	T124,T104,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T188,T72	Yes	T6,T188,T72	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T348	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T348	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T188,T72	Yes	T6,T188,T72	OUTPUT
cio_rx_i	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T104,T21,T308	Yes	T104,T21,T308	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T78,T308	Yes	T104,T78,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T78,T308	Yes	T104,T78,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T78,T308	Yes	T104,T78,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T78,T308	Yes	T104,T78,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	302	272	90.07
Total Bits 0->1	151	136	90.07
Total Bits 1->0	151	136	90.07

Ports	39	31	79.49
Port Bits	302	272	90.07
Port Bits 0->1	151	136	90.07
Port Bits 1->0	151	136	90.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T57,T124,T58	Yes	T57,T124,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T57,T124,T58	Yes	T57,T124,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	INPUT
tl_o.a_ready	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T124,T21,T308	Yes	T124,T21,T308	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T124,T21,T308	Yes	T6,T57,T124	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T21,*T132,T152	Yes	T6,T57,T124	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T124,T21,T308	Yes	T6,T57,T124	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T154,*T57,*T124	Yes	T154,T57,T124	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T21,T132,T152	Yes	T6,T57,T124	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T124,*T21,*T308	Yes	T124,T21,T308	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T57,T124	Yes	T6,T57,T124	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_rx_i	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T21,T308,T324	Yes	T21,T308,T324	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T308,T324,T298	Yes	T308,T324,T298	OUTPUT
intr_rx_watermark_o	Yes	Yes	T308,T324,T298	Yes	T308,T324,T298	OUTPUT
intr_tx_empty_o	Yes	Yes	T308,T324,T298	Yes	T308,T324,T298	OUTPUT
intr_rx_overflow_o	Yes	Yes	T308,T324,T298	Yes	T308,T324,T298	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T132,T108	Yes	T6,T132,T108	INPUT
tl_o.a_ready	Yes	Yes	T6,T132,T108	Yes	T6,T132,T108	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T132,T153,T309	Yes	T6,T132,T108	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,*T154	Yes	T6,T132,T108	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T132,T153,T309	Yes	T6,T132,T108	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T154,*T153,*T309	Yes	T154,T153,T309	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T154	Yes	T6,T132,T108	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T309,*T310,*T203	Yes	T309,T310,T203	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T132,T108	Yes	T6,T132,T108	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T188,T72	Yes	T6,T188,T72	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T348	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T348	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T188,T72	Yes	T6,T188,T72	OUTPUT
cio_rx_i	Yes	Yes	T309,T310,T349	Yes	T309,T310,T11	INPUT
cio_tx_o	Yes	Yes	T309,T310,T349	Yes	T309,T310,T349	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	OUTPUT
intr_rx_watermark_o	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	OUTPUT
intr_tx_empty_o	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	OUTPUT
intr_rx_overflow_o	Yes	Yes	T309,T310,T203	Yes	T309,T310,T203	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	39	31	79.49
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T104,T78	Yes	T6,T104,T78	INPUT
tl_o.a_ready	Yes	Yes	T6,T104,T78	Yes	T6,T104,T78	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T104,T78,T132	Yes	T6,T104,T78	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,*T154	Yes	T6,T104,T78	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T104,T78,T132	Yes	T6,T104,T78	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T154,*T104,*T78	Yes	T154,T104,T78	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T154	Yes	T6,T104,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T104,*T78,*T311	Yes	T104,T78,T311	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T104,T78	Yes	T6,T104,T78	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_rx_i	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	INPUT
cio_tx_o	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
intr_rx_watermark_o	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
intr_tx_empty_o	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T104,T78,T311	Yes	T104,T78,T311	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	31	79.49
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	39	31	79.49
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T6,T28,T132	Yes	T6,T28,T132	INPUT
tl_o.a_ready	Yes	Yes	T6,T28,T132	Yes	T6,T28,T132	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T28,T132,T312	Yes	T6,T28,T132	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T132,*T153,*T154	Yes	T6,T28,T132	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T132,T312	Yes	T6,T28,T132	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T154,*T28,*T312	Yes	T154,T28,T312	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T132,T153,T154	Yes	T6,T28,T132	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T312,*T80	Yes	T28,T312,T80	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T28,T132	Yes	T6,T28,T132	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T132	Yes	T6,T72,T132	OUTPUT
cio_rx_i	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	INPUT
cio_tx_o	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T312,T80	Yes	T28,T312,T80	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_break_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_timeout_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT

*Tests covering at least one bit in the range