Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.09	96.47	89.29	86.51		100.00	68.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	88.31	96.47	89.29	87.59		100.00	68.18

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.31	96.47	89.29	87.59		100.00	68.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.71	96.59	82.33	90.70		96.77	92.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.38			96.38
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	93.62	96.72	81.13			96.64	100.00
u_sim_win_rsp	89.32	77.27	80.00			100.00	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T75,T247,T248
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T169,T249,T250
1	0	Covered	T60,T21,T159

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T169,T21

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T9

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T108,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T60,T132

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T109

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T9

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T60,T169,T21
0	1	0	Covered	T75,T247,T248
1	0	0	Covered	T251,T252,T253

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T57
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	91	75.21
Total Bits	1624	1405	86.51
Total Bits 0->1	812	703	86.58
Total Bits 1->0	812	702	86.45

Ports	121	91	75.21
Port Bits	1624	1405	86.51
Port Bits 0->1	812	703	86.58
Port Bits 1->0	812	702	86.45

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T57,T254,T255	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T56,*T170,*T256	Yes	T56,T170,T256	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T61,T138,T139	Yes	T61,T138,T139	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T61,*T138,*T139	Yes	T61,T138,T139	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T66,T9,T140	Yes	T66,T9,T140	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T66,T9,T140	Yes	T66,T9,T140	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T66,T9,T40	Yes	T66,T9,T40	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T18,T110,T141	Yes	T18,T110,T141	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_timer_i	Yes	Yes	T260,T135,T261	Yes	T260,T135,T261	INPUT
irq_external_i	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
nmi_wdog_i	Yes	Yes	T123,T262,T105	Yes	T123,T262,T105	INPUT
debug_req_i	Yes	Yes	T61,T142,T143	Yes	T61,T142,T143	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T9,*T4,*T5	Yes	T9,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T9	Yes	T9	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T57	Yes	T4,T17,T57	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T17,T57	Yes	T4,T17,T57	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T9,*T4,*T5	Yes	T9,T4,T5	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T17,T57,T44	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T162,T263,T85	Yes	T87,T162,T264	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T190,T170,T191	Yes	T190,T170,T191	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T57,T44	Yes	T5,T6,T17	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T5,T57,T43	INPUT
icache_otp_key_i.ack	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T6,T60,T72	Yes	T6,T60,T72	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T6,T75,T72	Yes	T6,T75,T72	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T6,T60,T72	Yes	T6,T60,T72	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T6,T75,T72	Yes	T6,T75,T72	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T60,T169,T21
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T169,T249,T250
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T57
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	484059368	8	0	0
FpvSecCmIbexFetchEnable1_A	484059368	24169278	0	104
FpvSecCmIbexFetchEnable2_A	484059368	64590728	0	96
FpvSecCmIbexFetchEnable3Rev_A	484059368	415021906	0	1970
FpvSecCmIbexFetchEnable3_A	484059368	415023748	0	1851
FpvSecCmIbexInstrIntgErrCheck_A	484059368	152	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	484059368	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	484059368	0	0	0
FpvSecCmIbexPcMismatchCheck_A	484059368	0	0	0
FpvSecCmIbexRfEccErrCheck_A	484059368	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	484059368	0	0	0
FpvSecCmRegWeOnehotCheck_A	484059368	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	484059368	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	484059368	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	484059368	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	988	988	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	988	988	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	484059368	189	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	484059368	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	8	0	0
T21	113158	0	0	0
T67	40237	0	0	0
T81	411997	0	0	0
T147	70069	0	0	0
T159	233139	0	0	0
T160	72380	0	0	0
T169	264687	1	0	0
T247	175966	0	0	0
T249	0	1	0	0
T250	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	544644	0	0	0
T271	66466	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	24169278	0	104
T4	140224	9919	0	0
T5	84690	9923	0	0
T6	100784	9927	0	0
T17	104156	9923	0	0
T18	260781	40474	0	0
T19	991451	406064	0	0
T20	0	0	0	2
T21	0	0	0	2
T43	500350	19846	0	0
T44	288369	41107	0	0
T55	0	0	0	2
T56	0	0	0	2
T57	207417	9927	0	0
T67	0	0	0	2
T117	81945	9931	0	0
T128	0	0	0	2
T186	0	0	0	2
T272	0	0	0	2
T273	0	0	0	2
T274	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	64590728	0	96
T4	140224	37817	0	0
T5	84690	34775	0	0
T6	100784	34775	0	0
T17	104156	34775	0	0
T18	260781	69554	0	0
T19	991451	591171	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T43	500350	69555	0	0
T44	288369	69554	0	0
T55	0	0	0	2
T56	0	0	0	2
T57	207417	34775	0	0
T117	81945	34775	0	0
T128	0	0	0	2
T186	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T277	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	415021906	0	1970
T4	140224	102351	0	2
T5	84690	49861	0	2
T6	100784	65944	0	2
T17	104156	69327	0	2
T18	260781	170488	0	2
T19	991451	360736	0	2
T43	500350	430676	0	2
T44	288369	197447	0	2
T57	207417	203933	0	2
T117	81945	47109	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	415023748	0	1851
T4	140224	102354	0	2
T5	84690	49862	0	2
T6	100784	65945	0	2
T17	104156	69328	0	2
T18	260781	170490	0	2
T19	991451	360744	0	2
T43	500350	430678	0	2
T44	288369	197449	0	2
T57	207417	203934	0	2
T117	81945	47110	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	152	0	0
T107	189471	0	0	0
T230	115977	0	0	0
T278	267551	76	0	0
T279	0	76	0	0
T280	113526	0	0	0
T281	150196	0	0	0
T282	112784	0	0	0
T283	156564	0	0	0
T284	70860	0	0	0
T285	78028	0	0	0
T286	455709	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	586	0	0
T1	133336	0	0	0
T2	110076	0	0	0
T60	227713	0	0	0
T72	465275	0	0	0
T75	182367	32	0	0
T84	357112	0	0	0
T128	137519	0	0	0
T129	252391	0	0	0
T130	86554	0	0	0
T172	0	31	0	0
T188	244413	0	0	0
T189	0	32	0	0
T247	0	100	0	0
T248	0	99	0	0
T256	0	1	0	0
T287	0	1	0	0
T288	0	32	0	0
T289	0	31	0	0
T290	0	1	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	6	0	0
T30	623261	0	0	0
T68	745716	0	0	0
T251	263581	1	0	0
T252	250319	1	0	0
T253	0	1	0	0
T291	0	1	0	0
T292	0	1	0	0
T293	0	1	0	0
T294	247066	0	0	0
T295	235444	0	0	0
T296	246948	0	0	0
T297	280656	0	0	0
T298	595686	0	0	0
T299	183622	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	189	0	0
T8	186350	0	0	0
T50	156960	0	0	0
T144	989053	0	0	0
T170	254523	0	0	0
T186	106149	0	0	0
T190	104957	32	0	0
T191	0	32	0	0
T192	0	32	0	0
T300	0	16	0	0
T301	0	32	0	0
T302	0	45	0	0
T303	137609	0	0	0
T304	133226	0	0	0
T305	156225	0	0	0
T306	107188	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	197	0	0
T8	186350	0	0	0
T50	156960	0	0	0
T144	989053	0	0	0
T170	254523	16	0	0
T171	0	16	0	0
T186	106149	0	0	0
T190	104957	42	0	0
T191	0	8	0	0
T192	0	42	0	0
T300	0	4	0	0
T301	0	42	0	0
T302	0	11	0	0
T303	137609	0	0	0
T304	133226	0	0	0
T305	156225	0	0	0
T306	107188	0	0	0
T307	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	492	3	3	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
ALWAYS	518	8	8	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	703	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	739	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
ALWAYS	792	11	11	100.00
ALWAYS	808	7	7	100.00
CONT_ASSIGN	819	1	1	100.00
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	0	0.00
CONT_ASSIGN	847	0	0
CONT_ASSIGN	886	1	1	100.00
ALWAYS	945	0	0
CONT_ASSIGN	986	1	0	0.00
CONT_ASSIGN	988	1	0	0.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	994	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
492	1	1
493	1	1
495	1	1
512	1	1
513	1	1
514	1	1
515	1	1
518	1	1
519	1	1
520	1	1
521	1	1
522	1	1
523	1	1
524	1	1
525	1	1
			MISSING_ELSE
702	2	2
703	2	2
704	2	2
708	2	2
709	2	2
710	2	2
717	1	1
718	1	1
719	1	1
722	1	1
724	1	1
726	1	1
728	1	1
735	1	1
737	1	1
739	1	1
741	1	1
751	1	1
752	1	1
753	1	1
754	1	1
757	1	1
760	1	1
792	1	1
793	1	1
794	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
			MISSING_ELSE
808	1	1
809	1	1
810	1	1
811	1	1
813	1	1
814	1	1
815	1	1
819	1	1
838	1	1
839	1	1
840	1	1
843	0	1
847		unreachable
886	1	1
945		unreachable
946		unreachable
947		unreachable
948		unreachable
			==> MISSING_ELSE
986	0	1
988	0	1
990	1	1
992	1	1
994	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T75,T247,T248
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T169,T249,T250
1	0	Covered	T60,T21,T159

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T60,T169,T21

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T9

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T108,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T60,T132

 LINE       739
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T109

 LINE       741
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T60,T132
1	0	Covered	T4,T5,T6
1	1	Covered	T6,T108,T9

 LINE       753
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T60,T169,T21
0	1	0	Covered	T75,T247,T248
1	0	0	Covered	T251,T252,T253

 LINE       800
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T57
1	1	Covered	T4,T5,T6

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	91	77.78
Total Bits	1604	1405	87.59
Total Bits 0->1	802	703	87.66
Total Bits 1->0	802	702	87.53

Ports	117	91	77.78
Port Bits	1604	1405	87.59
Port Bits 0->1	802	703	87.66
Port Bits 1->0	802	702	87.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_edn_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_edn_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
rst_cpu_n_o	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T57,T254,T255	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T56,*T170,*T256	Yes	T56,T170,T256	OUTPUT
corei_tl_h_o.a_address[31:30]	No	No		No		OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_error	Yes	Yes	T61,T138,T139	Yes	T61,T138,T139	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T61,*T138,*T139	Yes	T61,T138,T139	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T66,T9,T140	Yes	T66,T9,T140	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T66,T9,T140	Yes	T66,T9,T140	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T66,T9,T40	Yes	T66,T9,T40	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_error	Yes	Yes	T18,T110,T141	Yes	T18,T110,T141	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
irq_software_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
irq_timer_i	Yes	Yes	T260,T135,T261	Yes	T260,T135,T261	INPUT
irq_external_i	Yes	Yes	T4,T17,T18	Yes	T4,T17,T18	INPUT
esc_tx_i.esc_n	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
esc_tx_i.esc_p	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
esc_rx_o.resp_n	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
nmi_wdog_i	Yes	Yes	T123,T262,T105	Yes	T123,T262,T105	INPUT
debug_req_i	Yes	Yes	T61,T142,T143	Yes	T61,T142,T143	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T9,*T4,*T5	Yes	T9,T4,T5	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T9	Yes	T9	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T4,T17,T57	Yes	T4,T17,T57	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T4,T17,T57	Yes	T4,T17,T57	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T9,*T4,*T5	Yes	T9,T4,T5	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_o.edn_req	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T17,T57,T44	Yes	T4,T5,T6	INPUT
edn_i.edn_fips	Yes	Yes	T162,T263,T85	Yes	T87,T162,T264	INPUT
edn_i.edn_ack	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
icache_otp_key_o.req	Yes	Yes	T190,T170,T191	Yes	T190,T170,T191	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T57,T44	Yes	T5,T6,T17	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T4,T5,T6	Yes	T5,T57,T43	INPUT
icache_otp_key_i.ack	Yes	Yes	T190,T191,T192	Yes	T190,T191,T192	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T6,T60,T72	Yes	T6,T60,T72	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T6,T75,T72	Yes	T6,T75,T72	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T6,T60,T72	Yes	T6,T60,T72	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T6,T75,T72	Yes	T6,T75,T72	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T6,T72,T115	Yes	T6,T72,T115	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	492	2	2	100.00
IF	518	3	3	100.00
IF	796	3	3	100.00
IF	808	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T60,T169,T21
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	492	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	518	if ((!rst_ni))
-2-:	522	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T169,T249,T250
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	796	if (reg2hw.rnd_data.re)
-2-:	800	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T17,T57
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	808	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	15	68.18
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	15	68.18

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	484059368	8	0	0
FpvSecCmIbexFetchEnable1_A	484059368	24169278	0	104
FpvSecCmIbexFetchEnable2_A	484059368	64590728	0	96
FpvSecCmIbexFetchEnable3Rev_A	484059368	415021906	0	1970
FpvSecCmIbexFetchEnable3_A	484059368	415023748	0	1851
FpvSecCmIbexInstrIntgErrCheck_A	484059368	152	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	484059368	586	0	0
FpvSecCmIbexLockstepResetCountAlertCheck_A	484059368	0	0	0
FpvSecCmIbexPcMismatchCheck_A	484059368	0	0	0
FpvSecCmIbexRfEccErrCheck_A	484059368	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	484059368	0	0	0
FpvSecCmRegWeOnehotCheck_A	484059368	6	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	484059368	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	484059368	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	484059368	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	988	988	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	988	988	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	988	988	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	484059368	189	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	484059368	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	8	0	0
T21	113158	0	0	0
T67	40237	0	0	0
T81	411997	0	0	0
T147	70069	0	0	0
T159	233139	0	0	0
T160	72380	0	0	0
T169	264687	1	0	0
T247	175966	0	0	0
T249	0	1	0	0
T250	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	544644	0	0	0
T271	66466	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	24169278	0	104
T4	140224	9919	0	0
T5	84690	9923	0	0
T6	100784	9927	0	0
T17	104156	9923	0	0
T18	260781	40474	0	0
T19	991451	406064	0	0
T20	0	0	0	2
T21	0	0	0	2
T43	500350	19846	0	0
T44	288369	41107	0	0
T55	0	0	0	2
T56	0	0	0	2
T57	207417	9927	0	0
T67	0	0	0	2
T117	81945	9931	0	0
T128	0	0	0	2
T186	0	0	0	2
T272	0	0	0	2
T273	0	0	0	2
T274	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	64590728	0	96
T4	140224	37817	0	0
T5	84690	34775	0	0
T6	100784	34775	0	0
T17	104156	34775	0	0
T18	260781	69554	0	0
T19	991451	591171	0	0
T20	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T43	500350	69555	0	0
T44	288369	69554	0	0
T55	0	0	0	2
T56	0	0	0	2
T57	207417	34775	0	0
T117	81945	34775	0	0
T128	0	0	0	2
T186	0	0	0	2
T275	0	0	0	2
T276	0	0	0	2
T277	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	415021906	0	1970
T4	140224	102351	0	2
T5	84690	49861	0	2
T6	100784	65944	0	2
T17	104156	69327	0	2
T18	260781	170488	0	2
T19	991451	360736	0	2
T43	500350	430676	0	2
T44	288369	197447	0	2
T57	207417	203933	0	2
T117	81945	47109	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	415023748	0	1851
T4	140224	102354	0	2
T5	84690	49862	0	2
T6	100784	65945	0	2
T17	104156	69328	0	2
T18	260781	170490	0	2
T19	991451	360744	0	2
T43	500350	430678	0	2
T44	288369	197449	0	2
T57	207417	203934	0	2
T117	81945	47110	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	152	0	0
T107	189471	0	0	0
T230	115977	0	0	0
T278	267551	76	0	0
T279	0	76	0	0
T280	113526	0	0	0
T281	150196	0	0	0
T282	112784	0	0	0
T283	156564	0	0	0
T284	70860	0	0	0
T285	78028	0	0	0
T286	455709	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	586	0	0
T1	133336	0	0	0
T2	110076	0	0	0
T60	227713	0	0	0
T72	465275	0	0	0
T75	182367	32	0	0
T84	357112	0	0	0
T128	137519	0	0	0
T129	252391	0	0	0
T130	86554	0	0	0
T172	0	31	0	0
T188	244413	0	0	0
T189	0	32	0	0
T247	0	100	0	0
T248	0	99	0	0
T256	0	1	0	0
T287	0	1	0	0
T288	0	32	0	0
T289	0	31	0	0
T290	0	1	0	0

FpvSecCmIbexLockstepResetCountAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	6	0	0
T30	623261	0	0	0
T68	745716	0	0	0
T251	263581	1	0	0
T252	250319	1	0	0
T253	0	1	0	0
T291	0	1	0	0
T292	0	1	0	0
T293	0	1	0	0
T294	247066	0	0	0
T295	235444	0	0	0
T296	246948	0	0	0
T297	280656	0	0	0
T298	595686	0	0	0
T299	183622	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T43	1	1	0	0
T44	1	1	0	0
T57	1	1	0	0
T117	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	189	0	0
T8	186350	0	0	0
T50	156960	0	0	0
T144	989053	0	0	0
T170	254523	0	0	0
T186	106149	0	0	0
T190	104957	32	0	0
T191	0	32	0	0
T192	0	32	0	0
T300	0	16	0	0
T301	0	32	0	0
T302	0	45	0	0
T303	137609	0	0	0
T304	133226	0	0	0
T305	156225	0	0	0
T306	107188	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484059368	197	0	0
T8	186350	0	0	0
T50	156960	0	0	0
T144	989053	0	0	0
T170	254523	16	0	0
T171	0	16	0	0
T186	106149	0	0	0
T190	104957	42	0	0
T191	0	8	0	0
T192	0	42	0	0
T300	0	4	0	0
T301	0	42	0	0
T302	0	11	0	0
T303	137609	0	0	0
T304	133226	0	0	0
T305	156225	0	0	0
T306	107188	0	0	0
T307	0	16	0	0