Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.65 81.65

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 81.65 81.65


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.65 81.65


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.65 81.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.87 90.68 87.93 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 301 54.73
Total Bits 6824 5572 81.65
Total Bits 0->1 3412 2786 81.65
Total Bits 1->0 3412 2786 81.65

Ports 550 301 54.73
Port Bits 6824 5572 81.65
Port Bits 0->1 3412 2786 81.65
Port Bits 1->0 3412 2786 81.65

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T61,T138,T139 Yes T61,T138,T139 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T61,*T138,*T139 Yes T61,T138,T139 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T64,T65,T66 Yes T64,T65,T66 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T66,T9,T140 Yes T66,T9,T140 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T66,T9,T40 Yes T66,T9,T40 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T18,T110,T141 Yes T18,T110,T141 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T61,T62,T100 Yes T61,T62,T100 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T43,*T18,*T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T61,T62,T100 Yes T61,T62,T100 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T61,T62,T100 Yes T61,T62,T100 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T43,T18,T44 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T61,T62,T100 Yes T61,T62,T100 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T62,T100,T63 Yes T62,T100,T63 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes *T61,T62,T100 Yes T61,T62,T100 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T61,T100,T101 Yes T61,T100,T101 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T61,T62,T100 Yes T61,T62,T100 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T61,*T62,*T100 Yes T61,T62,T100 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T61,T62,T100 Yes T61,T62,T100 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T43,T18,T44 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0] Yes Yes *T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0] Yes Yes *T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[19:0] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_data[20] No No No OUTPUT
tl_rv_dm__regs_o.a_data[31:21] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[0] Yes Yes *T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_source[5:1] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[0] No No No OUTPUT
tl_rv_dm__regs_o.a_size[1] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_opcode[2] Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T9 Yes T9 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0] Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4] Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[0] Yes Yes *T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_source[5:1] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[0] No No No INPUT
tl_rv_dm__regs_i.d_size[1] Yes Yes T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T9 Yes T9 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T9 Yes T9 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T43,T18,T44 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T61,*T142,*T143 Yes T61,T142,T143 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T61,T142,T64 Yes T61,T142,T64 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T5,T6 Yes T43,T18,T44 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T61,T142,T143 Yes T61,T142,T143 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T61,*T142,*T64 Yes T61,T142,T64 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T61,*T142,*T64 Yes T61,T142,T64 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T43,T18,T44 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T61,*T142,*T143 Yes T61,T142,T143 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T61,T142,T64 Yes T61,T142,T64 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T43,T18,T44 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T61,T142,T64 Yes T61,T142,T64 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T144,T145,T146 Yes T144,T145,T146 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T6,T43,T18 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T6,T108,T9 Yes T6,T108,T9 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T6,T147,T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T6,*T147,*T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T6,T147,T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T6,T108,T9 Yes T6,T108,T9 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T6,T147,T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0] Yes Yes *T9,*T6,*T147 Yes T9,T6,T147 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T6,T147,T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T147,T148,T9 Yes T147,T148,T9 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T6,T147,T108 Yes T6,T147,T108 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T6,T147,T108 Yes T6,T147,T108 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T147,T148,T149 Yes T147,T148,T149 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0] Yes Yes T9,*T6,*T108 Yes T6,T108,T9 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T9,T150,T151 Yes T6,T147,T108 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T147,T148,T9 Yes T6,T147,T108 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[1:0] Yes Yes *T9,*T147,*T148 Yes T9,T6,T147 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T9,T150,T151 Yes T6,T147,T108 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T9,*T150,*T151 Yes T147,T148,T9 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T6,T147,T108 Yes T6,T147,T108 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T61,*T62,*T63 Yes T61,T62,T63 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T64,*T65,*T66 Yes T64,T65,T66 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T18,T44,T110 Yes T18,T44,T110 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T61,*T62,*T63 Yes T61,T62,T63 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T40,T41,T42 Yes T40,T41,T42 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T6,*T132,*T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T6,*T132,*T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T64,*T132,*T25 Yes T64,T132,T25 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T27,*T133,*T134 Yes T27,T133,T134 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T25,T152,T135 Yes T25,T152,T135 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T6,T132,T25 Yes T6,T132,T25 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T6,T132,T25 Yes T6,T132,T25 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T25,T135,T26 Yes T25,T135,T26 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T132,T25,T152 Yes T6,T132,T25 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes *T132,T152,*T153 Yes T6,T132,T25 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T25,T135,T26 Yes T25,T135,T26 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T64,*T132,*T25 Yes T64,T132,T25 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T132,T152,T153 Yes T6,T132,T25 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T25,*T152,*T135 Yes T25,T152,T135 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T6,T132,T25 Yes T6,T132,T25 INPUT
tl_spi_host1_o.d_ready Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T6,T108,T135 Yes T6,T108,T135 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T6,*T152,*T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T6,T108,T135 Yes T6,T108,T135 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T64,*T152,*T135 Yes T64,T152,T135 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T152,T135,T136 Yes T152,T135,T136 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T6,T152,T108 Yes T6,T152,T108 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T6,T152,T108 Yes T6,T152,T108 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T135,T136,T64 Yes T135,T136,T64 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T152,T135,T136 Yes T6,T152,T108 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T152,T64,T46 Yes T6,T152,T108 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T135,T136,T64 Yes T135,T136,T64 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T64,*T152,*T135 Yes T64,T152,T135 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T152,T64,T46 Yes T6,T152,T108 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T152,*T135,*T136 Yes T152,T135,T136 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T6,T152,T108 Yes T6,T152,T108 INPUT
tl_usbdev_o.d_ready Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T6,*T1,*T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[1:0] Yes Yes *T154,*T1,*T30 Yes T154,T1,T30 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T30,T32,T155 Yes T30,T32,T155 OUTPUT
tl_usbdev_o.a_valid Yes Yes T6,T1,T30 Yes T6,T1,T30 OUTPUT
tl_usbdev_i.a_ready Yes Yes T6,T1,T30 Yes T6,T1,T30 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T30,T32,T155 Yes T30,T32,T155 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T30,T32,T155 Yes T30,T32,T155 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T30,T31,T32 Yes T6,T1,T30 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T6,T1,T30 Yes T30,T31,T32 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[1:0] Yes Yes *T154,*T30,*T31 Yes T154,T1,T30 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T30,T31,T32 Yes T6,T1,T30 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T6,*T1,*T30 Yes T30,T31,T32 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T6,T1,T30 Yes T6,T1,T30 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T43,T18,T44 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T57,T43,T18 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T57,T43,T18 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[0] No No No INPUT
tl_flash_ctrl__core_i.d_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T57,T43,T18 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T43,T18,T44 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_valid No No No OUTPUT
tl_flash_ctrl__prim_i.a_ready No No No INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] No No No INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[5:0] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] No No No INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid No No No INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T43,T18,T44 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T6,T17,T57 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T6,*T17,*T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[0] No No No OUTPUT
tl_hmac_o.a_source[1] Yes Yes *T6,*T17,*T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T17,*T73,*T156 Yes T17,T73,T156 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T17,T57,T123 Yes T17,T57,T123 OUTPUT
tl_hmac_o.a_valid Yes Yes T6,T17,T57 Yes T6,T17,T57 OUTPUT
tl_hmac_i.a_ready Yes Yes T6,T17,T57 Yes T6,T17,T57 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T17,T57,T123 Yes T17,T57,T123 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T17,T57,T123 Yes T17,T57,T123 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T17,T57,T73 Yes T6,T17,T57 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T6,T17,T57 Yes T17,T57,T123 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[0] No No No INPUT
tl_hmac_i.d_source[1] Yes Yes *T17,*T57,*T123 Yes T6,T17,T57 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T17,T57,T73 Yes T6,T17,T57 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T6,*T17,*T57 Yes T17,T57,T123 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T6,T17,T57 Yes T6,T17,T57 INPUT
tl_kmac_o.d_ready Yes Yes T6,T43,T18 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T6,*T43,*T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[0] No No No OUTPUT
tl_kmac_o.a_source[1] Yes Yes *T6,*T43,*T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T130,*T157,*T158 Yes T130,T157,T158 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T43,T130,T157 Yes T43,T130,T157 OUTPUT
tl_kmac_o.a_valid Yes Yes T6,T43,T130 Yes T6,T43,T130 OUTPUT
tl_kmac_i.a_ready Yes Yes T6,T43,T130 Yes T6,T43,T130 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T43,T130,T157 Yes T43,T130,T157 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T43,T130,T157 Yes T43,T130,T157 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T130,T157,*T159 Yes T6,T43,T130 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T6,T43,T130 Yes T130,T157,T158 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[0] No No No INPUT
tl_kmac_i.d_source[1] Yes Yes *T6,*T43,*T130 Yes T6,T43,T130 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T130,T157,T159 Yes T6,T43,T130 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T6,*T43,*T130 Yes T130,T157,T158 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T6,T43,T130 Yes T6,T43,T130 INPUT
tl_aes_o.d_ready Yes Yes T6,T43,T18 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T6,T160,T161 Yes T6,T160,T161 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T6,*T160,*T161 Yes T6,T160,T161 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T162,T160,T159 Yes T162,T160,T159 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T6,*T162,*T160 Yes T6,T162,T160 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T6,T162,T160 Yes T6,T162,T160 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T6,T160,T161 Yes T6,T160,T161 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T6,T162,T160 Yes T6,T162,T160 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[0] No No No OUTPUT
tl_aes_o.a_source[1] Yes Yes *T6,*T162,*T160 Yes T6,T162,T160 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T6,T162,T160 Yes T6,T162,T160 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T162,T160,T159 Yes T162,T160,T159 OUTPUT
tl_aes_o.a_valid Yes Yes T6,T162,T160 Yes T6,T162,T160 OUTPUT
tl_aes_i.a_ready Yes Yes T6,T162,T160 Yes T6,T162,T160 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T162,T160,T159 Yes T162,T160,T159 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T162,T160,T161 Yes T6,T162,T160 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T159,*T163,*T164 Yes T6,T162,T160 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T162,T160,T159 Yes T6,T162,T160 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[0] No No No INPUT
tl_aes_i.d_source[1] Yes Yes *T6,*T162,*T160 Yes T6,T162,T160 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T159,T163,T164 Yes T6,T162,T160 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T162,*T160,*T159 Yes T162,T160,T159 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T6,T162,T160 Yes T6,T162,T160 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[0] No No No OUTPUT
tl_entropy_src_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T57,T43,T87 Yes T57,T43,T87 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T43,T87,T123 Yes T43,T87,T123 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T57,T43,T18 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes T43,*T18,*T44 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T57,T43,T18 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[0] No No No INPUT
tl_entropy_src_i.d_source[1] Yes Yes *T6,*T57,*T43 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T43,*T87,*T123 Yes T57,T43,T87 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T5,T6,T43 Yes T5,T6,T43 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[0] No No No OUTPUT
tl_csrng_o.a_source[1] Yes Yes *T5,*T6,*T43 Yes T5,T6,T43 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T5,T43,T87 Yes T5,T43,T87 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T5,T43,T87 Yes T5,T43,T87 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T5,T43,T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes T43,*T18,*T44 Yes T4,T5,T6 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T5,T43,T18 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[0] No No No INPUT
tl_csrng_i.d_source[1] Yes Yes *T5,*T6,*T43 Yes T5,T6,T43 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T5,*T43,*T87 Yes T5,T43,T87 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[0] No No No OUTPUT
tl_edn0_o.a_source[1] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T43,T87,T123 Yes T43,T87,T123 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[0] Yes Yes *T43,*T87,*T123 Yes T43,T87,T123 INPUT
tl_edn0_i.d_user.data_intg[1] No No No INPUT
tl_edn0_i.d_user.data_intg[6:2] Yes Yes T43,T87,T123 Yes T43,T87,T123 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes T43,*T18,*T44 Yes T4,T5,T6 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[0] No No No INPUT
tl_edn0_i.d_source[1] Yes Yes *T6,*T43,*T18 Yes T4,T5,T6 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T43,*T87,*T123 Yes T43,T87,T123 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T6,T43,T18 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T6,*T43,*T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T6,*T43,*T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[0] No No No OUTPUT
tl_edn1_o.a_source[1] Yes Yes *T6,*T43,*T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T43,T87,T123 Yes T43,T87,T123 OUTPUT
tl_edn1_o.a_valid Yes Yes T6,T43,T87 Yes T6,T43,T87 OUTPUT
tl_edn1_i.a_ready Yes Yes T6,T43,T87 Yes T6,T43,T87 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T43,T87,T123 Yes T43,T87,T123 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T43,T87,T123 Yes T6,T43,T87 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes *T165,*T88,*T166 Yes T6,T43,T87 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T43,T87,T123 Yes T6,T43,T87 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[0] No No No INPUT
tl_edn1_i.d_source[1] Yes Yes *T6,*T43,*T87 Yes T6,T43,T87 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T165,T88,T166 Yes T6,T43,T87 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T43,*T87,*T123 Yes T43,T87,T123 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T6,T43,T87 Yes T6,T43,T87 INPUT
tl_rv_plic_o.d_ready Yes Yes T4,T6,T17 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T4,*T6,*T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T64,*T4,*T17 Yes T64,T4,T17 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T4,T17,T18 Yes T4,T17,T18 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T4,T6,T17 Yes T4,T6,T17 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T4,T6,T17 Yes T4,T6,T17 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T17,T18,T44 Yes T17,T18,T44 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T4,T17,T18 Yes T4,T6,T17 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T18,T44,T110 Yes T4,T6,T17 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T4,T17,T18 Yes T4,T6,T17 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T64,*T4,*T17 Yes T64,T4,T17 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T18,T44,T110 Yes T4,T6,T17 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T4,*T17,*T18 Yes T4,T17,T18 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T4,T6,T17 Yes T4,T6,T17 INPUT
tl_otbn_o.d_ready Yes Yes T6,T57,T43 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T6,*T57,*T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T65,*T66,*T167 Yes T65,T66,T167 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T57,T58,T59 Yes T57,T58,T59 OUTPUT
tl_otbn_o.a_valid Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_otbn_i.a_ready Yes Yes T6,T57,T58 Yes T6,T57,T58 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T57,T58,T59 Yes T57,T58,T59 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T57,T58,T59 Yes T57,T58,T59 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T57,T58,T59 Yes T6,T57,T58 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T6,T57,T58 Yes T57,T58,T59 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T65,*T66,*T167 Yes T65,T66,T167 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T57,T58,T59 Yes T6,T57,T58 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T6,*T57,*T58 Yes T57,T58,T59 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T6,T57,T58 Yes T6,T57,T58 INPUT
tl_keymgr_o.d_ready Yes Yes T6,T57,T43 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T6,*T57,*T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T6,*T57,*T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[0] No No No OUTPUT
tl_keymgr_o.a_source[1] Yes Yes *T6,*T57,*T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T57,T43,T58 Yes T57,T43,T58 OUTPUT
tl_keymgr_o.a_valid Yes Yes T6,T57,T43 Yes T6,T57,T43 OUTPUT
tl_keymgr_i.a_ready Yes Yes T6,T57,T43 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T43,T60,T168 Yes T43,T60,T168 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T57,T43,T58 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T60,T7,T111 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T57,T43,T58 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[0] No No No INPUT
tl_keymgr_i.d_source[1] Yes Yes *T6,*T57,*T43 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T60,T7,T111 Yes T6,T57,T43 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T57,*T43,*T58 Yes T57,T43,T58 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T6,T57,T43 Yes T6,T57,T43 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0] Yes Yes *T9,*T4,*T5 Yes T9,T4,T5 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T9 Yes T9 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T4,T17,T57 Yes T4,T17,T57 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T4,T17,T57 Yes T4,T17,T57 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0] Yes Yes *T9,*T4,*T5 Yes T9,T4,T5 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T43,T18,T44 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T6,T57,T43 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T6,*T57,*T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T75,T169,T170 Yes T75,T169,T170 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T6,*T57,*T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T64,*T57,*T58 Yes T64,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T75,T169,T170 Yes T75,T169,T170 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T6,T57,T58 Yes T6,T57,T58 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T6,T57,T58 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T170,*T171,*T64 Yes T170,T171,T64 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T75,T21,*T55 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes T75,*T21,*T55 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T75,T21,T55 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T64,*T75,*T21 Yes T64,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T75,T21,T55 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T75,*T170,*T172 Yes T75,T169,T170 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T6,T57,T58 Yes T6,T57,T58 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T43,T18,T44 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%