Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.07			93.07

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon	93.07			93.07

---

Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.07			93.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.07			93.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.87	90.68		87.93			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	84	75	89.29
Total Bits	462	430	93.07
Total Bits 0->1	231	215	93.07
Total Bits 1->0	231	215	93.07

Ports	84	75	89.29
Port Bits	462	430	93.07
Port Bits 0->1	231	215	93.07
Port Bits 1->0	231	215	93.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_slow_ni	Yes	Yes	T19,T20,T21	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T19,T20,T21	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T19,T20,T72	Yes	T4,T5,T6	INPUT
clk_lc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_lc_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
clk_esc_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_esc_ni	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T57,T58	Yes	T4,T57,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T57,T58	Yes	T4,T57,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T64,*T65,*T66	Yes	T64,T65,T66	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T4,T57,T58	Yes	T4,T6,T57	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T21,*T317,*T55	Yes	T4,T6,T57	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T57,T58	Yes	T4,T6,T57	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T9,*T4,*T57	Yes	T9,T4,T6	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T21,T317,T55	Yes	T4,T6,T57	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T57,*T58	Yes	T4,T57,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T6,T141,T129	Yes	T6,T141,T129	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T72,T115,T116	Yes	T72,T115,T116	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T6,T141,T129	Yes	T6,T141,T129	OUTPUT
pwr_ast_i.main_pok	Yes	Yes	T19,T20,T72	Yes	T4,T5,T6	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	INPUT
pwr_ast_i.slow_clk_val	Yes	Yes	T78,T79,T80	Yes	T4,T5,T6	INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T4,T19,T20	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.slow_clk_en	No	No		No		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T4,T5,T6	Yes	T19,T20,T72	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T4,T5,T6	Yes	T19,T20,T72	OUTPUT
pwr_ast_o.main_pd_n	Yes	Yes	T72,T33,T34	Yes	T72,T33,T34	OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T4,T5,T6	Yes	T4,T43,T18	OUTPUT
pwr_rst_o.rstreqs[4:0]	Yes	Yes	T270,T33,T34	Yes	T270,T33,T34	OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	INPUT
pwr_clk_i.io_status	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	INPUT
pwr_clk_i.main_status	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	INPUT
pwr_otp_i.otp_idle	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_otp_i.otp_done	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_otp_o.otp_init	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
pwr_lc_i.lc_idle	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_lc_i.lc_done	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
pwr_lc_o.lc_init	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
pwr_flash_i.flash_idle	Yes	Yes	T43,T74,T180	Yes	T43,T74,T180	INPUT
pwr_cpu_i.core_sleeping	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
fetch_en_o[3:0]	Yes	Yes	T4,T43,T18	Yes	T4,T5,T6	OUTPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T43,T18,T44	Yes	T4,T5,T6	INPUT
wakeups_i[5:0]	Yes	Yes	T1,T270,T33	Yes	T1,T270,T33	INPUT
rstreqs_i[1:0]	Yes	Yes	T270,T33,T34	Yes	T270,T33,T34	INPUT
ndmreset_req_i	Yes	Yes	T61,T7,T8	Yes	T61,T7,T8	INPUT
strap_o	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
low_power_o	Yes	Yes	T4,T5,T6	Yes	T4,T19,T20	OUTPUT
rom_ctrl_i.good[3:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	INPUT
rom_ctrl_i.done[3:0]	Yes	Yes	T4,T5,T6	Yes	T43,T18,T44	INPUT
sw_rst_req_i[3:0]	Yes	Yes	T43,T19,T75	Yes	T43,T19,T75	INPUT
esc_rst_tx_i.esc_n	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	INPUT
esc_rst_tx_i.esc_p	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	INPUT
esc_rst_rx_o.resp_n	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	OUTPUT
esc_rst_rx_o.resp_p	Yes	Yes	T18,T44,T110	Yes	T18,T44,T110	OUTPUT
intr_wakeup_o	Yes	Yes	T4,T1,T2	Yes	T4,T1,T2	OUTPUT

*Tests covering at least one bit in the range